MR2A16A

MR2A16A_1 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Single 3.3-V power supply
• Commercial temperature range (0˚C to 70˚C), Industrial temperature range ( -40˚C to 85˚C) and Extended temperature range -40˚C to 105˚C)
• Symmetrical high-speed read and write with fast access time (35 ns)
• Flexible data bus control — 8 bit or 16 bit access
• Equal address and chip-enable access times
• Automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss
• All inputs and outputs are transistor-transistor logic (TTL) compatible
• Fully static operation
• Full nonvolatile operation with 20 years minimum data retention 256K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM MR2A16A 44-TSOP Case 924A-02

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Figure 1. Block Diagram Figure 2. MR2A16A in 44-Pin TSOP Type II Package Table 1. Pin Functions

greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. Table 2. Operating Modes

1 H = high, L = low, X = don’t care

2 Hi-Z = high impedance

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Table 3. Absolute Maximum Ratings1 fields could affect device reliability. 2 All voltages are referenced to VSS. 3 Power dissipation capability depends on package characteristics and use environment.

Table 4. Operating Conditions

1 After power up or if V DD falls below VWI, a waiting period of 2 μs must be observed, and E and W

2 After power up or if V DD falls below VWI, a waiting period of 2 ms must be observed, and E and W

3 VIH (max) = VDD + 0.3 Vdc; VIH (max) = VDD + 2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

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Table 5. dc Characteristics Table 6. Power Supply Characteristics 1 All active current measurements are measured with one address transition per cycle.

Figure 3. Output Load for ac Test Table 7. Capacitance1 1 f = 1.0 MHz, dV = 3.0 V, TA = 25˚C, periodically sampled rather than 100% tested. Table 8. ac Measurement Conditions

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Table 9. Read Cycle Timing1, 2

2 Due to product sensitivities to noise, power supplies must be properly grounded and

3 Addresses valid before or at the same time E goes low. 4 This parameter is sampled and not 100% tested. 5 Transition is measured ±200 mV from steady-state voltage.

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Table 10. Write Cycle Timing 1 (W Controlled)1, 2, 3, 4, 5 1 A write occurs during the overlap of E low and W low.

2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and

bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.

4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum

5 The minimum time betweenE being asserted low in one cycle toE being asserted low in a subsequent

cycle is the same as the minimum cycle time allowed for the device. 6 All write cycle timings are referenced from the last valid address to the first transition address. 7 This parameter is sampled and not 100% tested. 8 Transition is measured ±200 mV from steady-state voltage. 9 At any given voltage or temperature, tWLQZ max < tWHQX min.

Figure 6. Write Cycle 1 (W Controlled)

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Table 11. Write Cycle Timing 2 (E Controlled)1, 2, 3, 4, 5 1 A write occurs during the overlap of E low and W low.

2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled

and bus contention conditions must be minimized or eliminated during read and write cycles.

3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance

4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a

5 The minimum time between E being asserted low in one cycle to E being asserted low in a

subsequent cycle is the same as the minimum cycle time allowed for the device. 6 All write cycle timings are referenced from the last valid address to the first transition address.

7 If E goes low at the same time or after W goes low, the output will remain in a high-impedance

8 If E goes high at the same time or beforeW goes high, the output will remain in a high-impedance

Figure 7. Write Cycle 2 (E Controlled)

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Table 12. Write Cycle Timing 3 (LB/UB Controlled)1, 2, 3, 4, 5, 6 1 A write occurs during the overlap of E low and W low. bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.

5 If both byte control signals are asserted, the two signals must have no more than 2 ns skew between

6 The minimum time betweenE being asserted low in one cycle toE being asserted low in a subsequent

cycle is the same as the minimum cycle time allowed for the device. 7 All write cycle timings are referenced from the last valid address to the first transition address.

Figure 8. Write Cycle 3 (LB/UB Controlled)

MR2A16A Data Sheet, Rev. 4

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Ordering Information

This product is available in Commercial, Industrial, and Extended temperature versions. Freescale's semiconductor products can be classified into the following tiers: "Commercial", "Industrial" and “Extended.” A product should only be used in applications appropriate to its tier as shown below. For questions, please contact a Freescale sales representative.

• Commercial — Typically 5 year applications - personal computers, PDA's, portable telecom products, consumer electronics, etc.
• Industrial, Extended — Typically 10 year applications - installed telecom equipment, workstations, servers, etc. These products can also be used in Commercial applications. Current Part Numbering System (Industrial and Extended devices) Legacy Part Numbering System (Commercial devices) (Order by Full Part Number) MR Freescale MRAM Memory Prefix Density Code (0 = 1 Mb, 1 = 2 Mb, Timing Set (35 = 35 ns) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits) 2 16A A V YS 35 Memory Type (A = async, S = sync) 2 = 4 Mb, 4 = 16 Mb) Package Type (YS = TSOP II) Operating Temperature Range (C = -40°C to 85°C, V = -40°C to 105°C) (Order by Full Part Number) MR Freescale MRAM Memory Prefix Density Code (0 = 1 Mb, 1 = 2 Mb, Operating Temperature Range (C = 0°C to 70°C) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits) 2 16A A TS 35 C Memory Type (A = async, S = sync) 2 = 4 Mb, 4 = 16 Mb) Timing Set (35 = 35 ns) Package Type (TS = TSOP II)

Package Information

MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 17

Revision History

The following pages detail the package available to MR2A16A. Table 13. Package Information Revision Date Description of Change 4 18 Jun 2007 Added new Industrial and Extended temperature product information; updated part ordering information; changed to 2 ms delay after power up; power supply characteristics values updated to TBD for industrial and extended temperature devices.

Rev. 4, 6/2007 How to Reach Us: USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P .O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor H.K. Ltd.

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