L6983I STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 56
Technical content
Datasheet sections
- 1 Pin configuration
- 2 Typical application circuit
- 3 Maximum ratings
- 3.1 Absolute maximum ratings
- 3.2 ESD protection
- 3.3 Thermal characteristics
- 4 Electrical characteristics
- 4.1 Frequency selection table
- 5 Functional description
- 5.1 Primary side
- 5.1.1 Enable
- 5.1.2 Soft-start
- 5.1.3 Undervoltage lockout
- 5.1.4 Minimum on-time
- 5.1.5 Switch-over feature
- 5.1.6 Spread spectrum
- 5.2 Transformer
- 5.3 Secondary side
- 5.4 Iso-buck operation principle
- 6 Iso-buck performances
- 6.1 Output voltage line regulation
- 6.2 Output voltage load regulation
- 6.3 Efficiency
- 7 Device protections
- 7.1 Overvoltage protection
- 7.2 Overcurrent protection
- 7.3 Thermal shutdown
- 7.4 Power good
- 8 Closing the loop
- 8.1 GCO(s)control to output transfer function
- 8.2 Error amplifier compensation network
- 8.3 Voltage divider
- 9 Application notes
- 9.1 Output voltage adjustment
Features
- Designed for iso-buck topology
- 3.5 V to 38 V operating input voltage
- Primary output voltage regulation / no optocoupler required
- 4.5 A source / sink peak primary current capability
- Peak current mode architecture in forced PWM operation
- 390 ns blanking time
- 200 kHz to 1 MHz programmable switching frequency. Stable with low ESR capacitor: min 2 µF
- Internal compensation network
- 2 μA shutdown current
- Internal soft-start
- Enable
- Overvoltage protection
- Output voltage sequencing
- Thermal protection
- Optional spread spectrum for improved EMC
- Power Good
- Synchronization to external clock
- QFN16 (3x3 mm) package
Applications
- Isolated IGBT/SiC MOSFET gate drive supply
- OBC (On-board charger) for HEV/EV
- Electric traction systems
Description
The L6983I is a device specifically designed for isolated buck topology. The primary output voltage can be accurately adjusted, whereas the isolated secondary output is derived by using a given transformer ratio. No optocoupler is required. The primary sink capability up to -4.5 A (even during soft-start) allows a proper energy transfer to the secondary side as well as enabling a tracked soft-start of the secondary output. The control loop is based on a peak current mode architecture and the device operates in forced PWM. The 390 ns blanking time filters oscillations, generated by the transformer leakage inductance, making the solution more robust. The compact QFN16 3x3 mm package and the internal compensation of the L6983I help minimize design complexity and size. The switching frequency can be programmed in the 200 kHz - 1 MHz range with optional spread spectrum for improved EMC. The EN pin provides enable/disable functionality. The typical shutdown current is 2 μA when disabled. As soon as the EN pin is pulled up the device is enabled and the internal 1.3 ms soft-start takes place. The L6983I features Power Good open collector that monitors the FB voltage. Pulse by pulse current sensing on both power elements implements an effective constant current protection and thermal shutdown prevents thermal run-away. QFN16 (3 x 3 mm) Maturity status link L6983I
38 V, 10 W synchronous iso-buck converter for isolated applications
DS14040 - Rev 1 - October 2022 For further information contact your local STMicroelectronics sales office.
1 Pin configuration
Figure 1. Pin connection (top view) Table 1. Pin description
1 VIN DC input voltage
2 VINLDO DC input voltage connects to the supply rail with a simple RC filter.
3 AGND Analog ground
4 EN / CLKIN
signal, which synchronizes the device.
5 PGOOD
6 VBIAS
7 FB FB is output voltage sensing with external voltage divider.
8 FSW Connect an external resistor to program the oscillator frequency and
capacitor (≥ 1 μF) to filter internal voltage reference.
10 AGND Analog ground
Pin n° Symbol Function
11 BOOT
Connect an external capacitor (100 nF typ.) between BOOT and SW pins. The gate charge required to drive the internal nMOS is refreshed during the low-side switch conduction time.
12 VIN DC input voltage
13 PGND Power ground
14 SW Switching node
15 SW Switching node
16 PGND Power ground
- Exposed PAD Exposed pad must be connect to AGND, PGND. L6983I Pin configuration DS14040 - Rev 1 page 3/56
2 Typical application circuit
Figure 2. Basic application Table 2. Typical application component
3 Maximum ratings
3.1 Absolute maximum ratings
rating conditions may affect device reliability. Table 3. Absolute maximum ratings
- Negative peak voltage during switching activities caused by parasitic layout elements.
3.2 ESD protection
Table 4. ESD performance
3.3 Thermal characteristics
Table 5. Thermal data
4 Electrical characteristics
TJ = 25 °C, VIN = 12 V unless otherwise specified. Table 6. Electrical characteristics
Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit VCLKIN_T (3) Synchronization pulse ON and OFF- time 2.3 ≤ VCLKIN_TH ≤ 2.5 V VCLKIN_TH = 2.3 V 60 ns Synchronization pulse ON and OFF- time VCLKIN_TH > 2.5 V 20 ns Power good VTHR PGOOD threshold - 40 °C ≤ TJ ≤ 125 °C (2) 87 90 93 % VTHR_HYST PGOOD hysteresis (QFN version only) VPGOOD PGOOD open collector output VIN > VINH and VFB < VTH 4 mA sinking load 0.4 V 2 < VIN < VINH 4 mA sinking load 0.8 V TSHDWN (3) Thermal shutdown temperature 165 °C THYS (3) Thermal shutdown hysteresis 30 °C 1. Parameter tested in the static condition during testing phase. The parameter value may change over a dynamic application condition. 2. Specifications in the -40 to 125 °C temperature range are assured by characterization and statistical correlation. 3. Not tested in production. L6983I
4.1 Frequency selection table
All the populations tested at TJ = 25 °C, VIN = 12 V unless otherwise specified. Table 7. FSW selection Figure 3. Frequency setting with dithering (left) and without (right)
5 Functional description
- Primary side, the regulation loop of the peak current mode architecture regulates the primary voltage (blue area in the image below)
- A two-windings transformer (in gray)
- The secondary side, which generates the isolated output voltage (in green) given the selected transformer ratio.
Figure 4. Iso-buck general schematic
5.1 Primary side
hence transferring energy to the secondary coil during the off-time.
- Embedded power elements
- A fully integrated adjustable oscillator, which is able to set five different switching frequencies from 200 kHz to 1 MHz
- The ramp for the slope compensation avoiding subharmonic instability
- A transconductance error amplifier with integrated compensation network
- The high-side current sense amplifier to sense the inductor current
- A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
- The soft-start block ramps up the reference voltage on error amplifier thus decreasing the inrush current at power-up. The EN pin inhibits the device when driven low
- The EN/CLK pin section, which allows synchronizing the device to an external clock generator
- The pulse-by-pulse high-side / low-side switch current sensing to implement the constant current protection
- A circuit to implement the thermal protection function
- The OVP circuitry to discharge the output capacitor in case of overvoltage event
- The switchover capability of the internal regulator to supply a portion of the quiescent current when the VBIAS pin is connected to an external output voltage
- Enable / disable dithering operation. L6983I Functional description DS14040 - Rev 1 page 9/56
Figure 5. Block diagram
5.1.1 Enable
The EN pin is a digital input that turns the device on or off.
- The Wake-up threshold, V WAKE_UP = 0.5 V (see Section 4 Electrical characteristics).
- The Start-up threshold, V EN = 1.2 V (see Section 4 Electrical characteristics.) The following image shows
Figure 6. Power-up/down procedure increasing the current consumption. Once the voltage becomes lower than VEN THR, FALLING, the device interrupts the switching activities. reducing the current consumption. Please refer to Table 6. Electrical characteristics for the reported thresholds.
5.1.2 Soft-start
The soft-start (SS) limits the inrush current surge and makes the output voltage increase monotonically. The soft-start duration is fixed and has a typical value of 1.3 ms.
Figure 7. Soft-start procedure
- EN pin rising over VEN threshold. Please refer to Table 6. Electrical characteristics
so implementing a tracked soft-start. Figure 8. Tracked soft-start at secondary side
5.1.3 Undervoltage lockout
UVLO lasts more than 10 μs, the internal logic resets the device by turning off both LS and HS. After the reset, if the EN pin is still high, the device repeats the soft-start procedure.
5.1.4 Minimum on-time
on-time (masking time, from which the parameter TON MIN derives). Figure 9. Simulation with different masking times: insufficient (< 100 ns, left) and appropriate (390 ns, Figure 10. Remaining oscillations (left) and their filtering with RC snubber (right) VIN = 12 V, N = 6, IOUTiso
5.1.5 Switch-over feature
efficiency, especially at lower currents. Figure 11. Switch-over selection must be disabled when the voltage on the EN pin is lower than VWAKE_UP. The effect on the efficiency for both the primary output and the secondary isolated output are shown in Figure 12. Figure 12. Effect of the switch-over on the efficiency for primary output (left) and isolated secondary
5.1.6 Spread spectrum
changes the switching frequency in a range of ± 5%.
- Ramps up in 63 steps from minimum to maximum FSW
- Ramps down in 63 steps from maximum to minimum FSW The modulation shape is almost triangular with a frequency of: F Di t ℎer i ng = F sw 126 (2) A visual explanation about how the switching frequency varies when the spread spectrum feature is used can be observed in Figure 13. L6983I Primary side DS14040 - Rev 1 page 14/56
Figure 13. Switching frequency trend with spread spectrum feature activated
5.2 Transformer
energy transfer to the secondary side, hence generating the secondary isolated output voltage.
5.3 Secondary side
and the rectifying element (Schottky diode).
5.4 Iso-buck operation principle
The picture below describes the operation principle of the iso-buck converter. winding. The load connected to the secondary output is supplied by COUT2. When the low-side MOSFET is turned on, the voltage applied at the transformer windings inverts its polarity. winding to COUT and the load. Under this condition the energy transfer from primary to secondary side occurs. Figure 14. Iso-buck basic operating principle Figure 15. Iso-buck primary and secondary current waveforms
6 Iso-buck performances
Figure 16. Reference schematic for measurements of line and load regulation and efficiency
6.1 Output voltage line regulation
voltage range up to 32 V for L6983I with VOUT_prim = 5 V, at three different output currents (N = 6). Figure 17. Primary output line regulation (VOUT_prim = 5 V, fSW = 400 kHz) affected by the transformer and in particular by its leakage inductance. isolated output voltage to slightly increase, as shown in Figure 18.
6.2 Output voltage load regulation
the entire output current range for the L6983I with VOUTprim = 5 V. Figure 20. Load regulation of the primary not isolated output voltage (VIN = 12 V, VOUT_prim = 5 V, fSW = 400 mentioned parameters leads to a better load regulation. Figure 21. Load regulation of the secondary isolated output voltage (VIN = 12 V, VOUT_prim = 5 V, fSW = 400
transformer with a higher leakage inductance (twice as much the other transformer). Figure 22. Effect of the transformer leakage inductance on the isolated output load regulation (VIN = 12 V,
6.3 Efficiency
Figure 23. Primary output efficiency (VOUT_prim = 5 V, fSW = 400 kHz, secondary isolated output not
7 Device protections
7.1 Overvoltage protection
overvoltage threshold even during the worst-case scenario in terms of load transitions.
7.2 Overcurrent protection
current (see Table 6. Electrical characteristics) in an overcurrent condition. the low-side sensing “valley”. Figure 28. Effects of the peak and valley current protections on duty cycle and frequency
ratio, D the duty cycle and ΔIL the current ripple in the primary winding. Figure 31. Peak currents in LS and HS MOSFET depending on the isolated output current (VIN = 12 V, Figure 32. Left: VIN = 12 V, IPRIM exceeds IVY_SINK. Right: VIN = 18 V, IPRIM exceeds IPK. diode of the HS MOSFET until it reaches zero. Both HS and LS MOSFET remain off until the next clock cycle.
7.3 Thermal shutdown
7.4 Power good
- When the FB pin voltage is lower than 90 % (typ.) of the nominal internal reference for more than 10 µs.
- When the FB pin voltage is higher than 120% (typ.) of the nominal internal reference for more than 10 µs.
- During the soft-start procedure also with pre-charged V OUT.
- If a thermal shutdown event occurs.
The PGOOD pin is VIN compatible. Figure 33. PGOOD thresholds
8 Closing the loop
primary winding) as well as all the equations and calculations in the next sections. Figure 34. Block diagram of the loop
8.1 GCO(s)control to output transfer function
introduces a double pole at one half of the switching frequency.
Where ISLOPE is equal to 1 [A]. implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%.
8.2 Error amplifier compensation network
The following figure shows the typical compensation network required to stabilize the system. Figure 35. Transconductance embedded error amplifier
8.3 Voltage divider
Figure 36. Contribution of the resistor divider
f P = 1 2 ∙ π ∙ R 1 ∙ R 2 R 1 + R 2 ∙ C R 1 (19) f z <f P (20) So closing the loop, the loop gain is: G s = G D I V s ∙ G CO s ∙ A O s (21) L6983I Voltage divider DS14040 - Rev 1 page 30/56
9 Application notes
9.1 Output voltage adjustment
where RFB1 and RFB2 are the resistors used in the output divider (see figure below). Figure 37. Primary output voltage regulation limiting the time in which the energy transfer to the secondary side takes place. transformer and LLEAK the leakage inductance of the transformer.
9.2 Switching frequency
Section 4.1 Frequency selection table). Connecting the resistor between the pins FSW and VCC, the internal dithering circuit is turned on (see Figure 3). The switching frequency affects the selection of the primary inductance as well as the transformer construction. The efficiency also varies with the switching frequency (see Figure 24 and Figure 26).
9.3 Programmable power-up threshold
Figure 40. Programming power-up threshold
9.4 Output External synchronization
The device allows a direct connection between a clock source and the EN/CLKIN pin. Figure 41. External synchronization (direct connection) average value of the applied signal. Table 6. Electrical characteristics). Considering, for example, a clock source with VPP = 5.0 V, the minimum duty The device also allows the AC coupling.
Figure 42. External synchronization (AC coupling) to the EN/CLKIN pin and described in Section 9.3 Programmable power-up threshold. the synchronization by keeping the selected power-up and down thresholds. Table 8. External synchronization AC coupling suggested operation range The minimum amplitude for the external clock signal is, for both the configurations, equal to 2.3 V. capacitor equal to 1 nF is a correct choice.
10 Design of the external components
10.1 Input capacitor selection
capacitor are, together with its value, the maximum operating voltage and the RMS current capability. The input capacitor voltage rating must be higher than the maximum input operating voltage of the application. In the ideal case of efficiency η = 1, the RMS current reaches its maximum value when D = 0.5. Where ΔVHS and ΔVLS are the voltage drop across the high-side and low-side MOSFETs respectively. Figure 43. Input capacitor AC current
Considering the ideal case of η = 1, the equation above reaches its maximum value when D = 0.5. Therefore, the minimum input capacitance value can be defined as follows: CIN≥ CINmin = IOUT_pri+IOUT_sec∙ Nsec Npri 4∙ VPP∙ fSW ∙ (36) Typically, CIN is dimensioned to keep the maximum peak to peak voltage across the input filter in the order of 5% of VINmax. L6983I Input capacitor selection DS14040 - Rev 1 page 37/56
10.2 Transformer selection
The transformer has two essential tasks:
- Providing the isolation between the primary and secondary side in accordance with the application requirements
- Generating the necessary secondary output voltage from the regulated primary voltage with the most suitable turn ratio The transformer selection implies the definition of the following parameters:
- Isolation voltage
- Turn ratio
- Primary inductance
- Peak and RMS currents
- Windings resistance
- Leakage inductance
- Parasitic capacitances Isolation voltage The isolation of the transformer in terms of voltage capability (1.5 kV, 4 kV, and so on) and type (functional basic, reinforced, etc.) is mainly driven by the application. Both parameters normally affect the size of the transformer as well as other electrical characteristics (for example, winding resistance, leakage inductance, etc.). Turn ratio Naming Npri and Nsec the number of turns of the primary and secondary windings respectively, the turn ratio is so defined: N = Nsec Nprim (37) Considering Eq. (24), the turn ratio must be defined so that the voltage at the secondary output is the desired one over the whole secondary output current range: N ≥ VOUT_sec+ Rwind_sec∙ IOUT_sec + VFD1 VOUT_pri+IOUTpri∙ RDS on LS+Rwind_pri (38) If no current is drawn from the primary output, the turn ratio should only be chosen to compensate the drops due to the secondary winding resistance and the Schottky diode. The effect of the leakage inductance on the secondary output voltage regulation (not included in the equation above) should be taken into account too. Figure 17 clearly shows how the secondary output voltage can drift due to the leakage inductance. Primary inductance The choice of the primary inductance does not differ so much from a standard buck. The magnetizing current, (see Figure 44) which combines the two winding currents, has the same shape as the buck inductor current and can be defined as: IL_mag = Ipri+N∙ Isec (39) L6983I Transformer selection DS14040 - Rev 1 page 38/56
Figure 44. Primary winding current (blue), secondary winding current (magenta) and magnetizing current kHz, the inductor value should be 22 µH. RMS currents that the transformer should fulfill. leakage. Therefore, the measured peak value can differ from the one provided by this equation. affecting the negative peak current at the primary side. regulations. They also contribute to power losses, and so affect the efficiency of the total solution.
Figure 48. RC snubber network
- Capacitance across each winding (C P and CS, in the image below) due to the capacitive coupling between the coil and the core. As already mentioned, the winding capacitances are involved in the ringing observed during transition from off to on-phase of the primary side.
- Interwinding capacitance (C WW), that is the capacitance between windings. The interwinding capacitance should be reduced in order to limit disturbance on the primary side due to possible steep voltage transitions present in the load connected to the secondary output.
Figure 49. Transformer parasitic capacitances
10.3 Schottky diode
- Maximum forward current, mainly defined by the secondary output current demand (see Eq. (44))
- Forward voltage drop, which affects the secondary output voltage regulation
- Maximum peak reverse voltage. During the on-phase of the primary side, when in the secondary side no current flows, the diode is reverse biased and must withstand this voltage: VD1_rev = N∙ VINmax − VOUT_pri +VOUT_sec (45)
- Junction capacitance, which should be as low as possible in order to reduce the ringing described in the previous section L6983I Schottky diode DS14040 - Rev 1 page 42/56
10.4 Output capacitors selection
As in a standard buck converter, the primary output capacitor is involved in:
- Determining the output voltage ripple
- Supporting load transient
- Loop stability, by setting one pole and one zero in the transfer function Considering the output voltage ripple requirement, the primary output capacitance should be selected according to the following equation: COUT_pri= ΔIpri 8∙ fSW∙ ΔVOUT_pri − ESR∙ ΔIpri (46) Normally, MLCC capacitors are the best choice for the output capacitor, therefore the ESR contribution is negligible and Eq. (46) can be simplified. Secondary output capacitor The secondary output capacitor supplies the secondary output load current during the tON (when diode D1 is reverse biased) and its value defines the secondary output voltage ripple (ΔVOUT). COUT_sec= IOUT_sec∙ D ΔVOUT_sec∙ fSW (47) L6983I Output capacitors selection DS14040 - Rev 1 page 43/56
The application board (STEVAL-L6983IV1) schematic is shown in the figure below. Figure 50. Schematic of the application board (unregulated isolated output) resistors should be placed at Rf1 and Rf2. in the BOM below (Table 9 ) are assumed for a dual voltage 18 V / - 5 V. Figure 51. Proposed circuitry for post-regulation (not mounted, bottom side) for dual voltage (18 V / - 5 V)
Table 9. BOM
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
12.1 QFN16 (3x3 mm) package information
Figure 54. QFN16 (3x3 mm) package outline
Package information
DS14040 - Rev 1 page 47/56
Table 11. Order code
Ordering information
DS14040 - Rev 1 page 49/56
Revision history
Table 12. Document revision history 04-Oct-2022 1 Initial release.
Contents
DS14040 - Rev 1 page 52/56
IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved L6983I DS14040 - Rev 1 page 56/56