MPXS3015VMM1R

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Data Sheet: Advance Information Document Number: PXS30 Rev. 1, 09/2011 © Freescale Semiconductor, Inc., 2011. All rights reserved. Preliminary—Subject to Change Without Notice This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. PXS30

257 MAPBGA

(14 x 14 mm)

473 MAPBGA

(19 x 19 mm) The PXS30 family represents a new generation of 32-bit microcontrollers based on the Power Architecture®. These devices provide a cost-effective, single chip display solution for the industrial market. An integrated TFT driver with digital video input ability from an external video source, significant on-chip memory, and low power design methodologies provide flexibility and reliability in meeting display demands in rugged environments. The advanced processor core offers high performance processing optimized for low power consumption, operating at speeds as high as 64 MHz. The family itself is fully scalable from 512 KB to 1 MB internal flash memory. The memory capacity can be further expanded via the on-chip QuadSPI serial flash controller module. The PXS30 family platform has a single level of memory hierarchy supporting on-chip SRAM and flash memories. The 1 MB flash version features

160 KB of on-chip graphics SRAM to buffer cost

effective color TFT displays driven via the on-chip Display Control Unit (DCU). See Table 1 for specific memory size and feature sets of the product family members. The PXS30 family benefits from the extensive development infrastructure for Power Architecture devices, which is already well established. This includes full support from available software drivers, operating systems, and configuration code PXS30 Microcontroller Data Sheet 3.5 Electromagnetic interference (EMI) characteristics . . . 74

3.8 Power Management Controller (PMC) electrical

3.20 RESET

to assist with users’ implementations. See Section 3, Developer support, for more information.

1 Introduction

1.1 Document overview

highlights important electrical and physical characteristics of the devices.

1.2 Device comparison

Table 1. PXS30 Family Feature Set

Table 1. PXS30 Family Feature Set (continued)

1.3 Block diagram

Figure 1 shows a top-level block diagram of the PXS30 device.

1.2 V low-voltage

1.2 V high-voltage

2.7 V low-voltage

2 Does not include Test or Shadow Flash memory space. 3 Available only on 473-pin package.

Figure 1. PXS30 block diagram

2 MB Flash (ECC)

512 KB SRAM (ECC)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor6

1.4 Feature list

• High-performance e200z7d dual core — 32-bit Power Architecture  technology CPU — Up to 180 MHz core frequency — Dual-issue core — Variable length encoding (VLE) — Memory management unit (MMU) with 64 entries — 16 KB instruction cache and 16 KB data cache
• Memory available — Up to 2 MB Code flash memory with ECC — 64 KB Data flash memory with ECC — Up to 512 KB on-chip SRAM with ECC
• SIL3/ASILD innovative safety concept: LockStep mode and fail-safe protection — Sphere of replication (SoR) for key components — Redundancy checking units on outputs of the SoR connected to FCCU — Fault collection and control unit (FCCU) — Boot-time built-in self-test for memory (MBI ST) and logic (LBIST) triggered by hardware — Boot-time built-in self-tes t for ADC and flash memory — Replicated safety-enhanced watchdog timer — Junction temperature sensor — Non-maskable interrupt (NMI) — 16-region memory protection unit (MPU) — Clock monitoring units (CMU) — Power management unit (PMU) — Cyclic redundancy check (CRC) units
• Decoupled Parallel mode for high-pe rformance use of replicated cores
• Nexus Class 3+ interface
• Interrupts — Replicated 16-priority interrupt controller — Replicated 32-channel eDMA controller
• GPIOs individually programmable as input, output, or special function
• 3 general-purpose eTimer units (6 channels each)
• 3 FlexPWM units with four 16-bit channels per module
• Communications interfaces — 4 LINFlex modules — 3 DSPI modules with automa tic chip select generation — 4 FlexCAN interfaces (2.0B Ac tive) with 32 message objects

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 7 — FlexRay module (V2.1) with dual channel, up to 128 message objects and up to 10 Mbit/s — Fast Ethernet Controller (FEC) —3 I 2C modules

• Four 12-bit analog-to-dig ital converters (ADCs) — 22 input channels — Programmable cross triggering unit (CTU) to synchronize ADC conversion with timer and PWM
• External bus interface
• 16-bit external DDR memory controller
• Parallel digital interface (PDI)
• On-chip CAN/UART bootstrap loader
• Capable of operating on a single 3.3 V voltage supply — 3.3 V-only modules: I/O, oscillators, flash memory — 3.3 V or 5 V modules: ADCs, supply to internal VREG — 1.8–3.3 V supply range: DRAM/PDI
• Operating junction temperature range –40 to 150 °C

1.5 Feature details

1.5.1 High-performance e2 00z7d core processor

• Dual 32-bit Power Architecture  processor core
• Loose or tight core coupling
• Freescale Variable Length Encoding (VLE) en hancements for code size footprint reduction
• Thirty-two 64-bit genera l-purpose registers (GPRs)
• Memory management unit (MMU) with 64-entry fu lly-associative translation look-aside buffer (TLB)
• Branch processing unit
• Fully pipelined load/store unit
• 16 KB Instruction and 16 KB Data caches per core with line locking — Four way set associative — Two 32-bit fetches per clock — Eight-entry store buffer — Way locking — Supports tag and data parity
• Vectored interrupt support
• Signal processing engine 2 (SPE2) auxiliary processing unit (APU) operating on 64-bit general purpose registers

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor8

• Floating point —I E E E  754 compatible with software wrapper — Single precision in hardware; double precision with software library — Conversion instructions between single precision floating point and fixed point
• Long cycle time instructions (except for guarded lo ads) do not increase interrupt latency in the PXS30
• To reduce latency, long cycle time instru ctions are aborted upon interrupt requests
• Extensive system developmen t support through Nexus debug module

1.5.2 Crossbar switch (XBAR)

• 32-bit address bus, 64-bit data bus
• Simultaneous accesses from differen t masters to different slaves (there is no clock penalty when a parked master accesses a slave)

1.5.3 Memory Protection Unit (MPU)

The Memory Protection Unit splits the physical memory into 16 different regions. Each master (DMA, FlexRay, CPU) can be assigned different access rights to each region.

• 16-region MPU with concurrent ch ecks against each master access
• 32-byte granularity for protected address region

1.5.4 Enhanced Direct Memo ry Access (eDMA) controller

• 32 channels support independent 8-, 16-, 32-bit single value or block transfers
• Supports variable-sized que ues and circular queues
• Source and destination address regi sters are independently configured to post-increment or remain constant
• Each transfer is initiated by a peri pheral, CPU, or eDMA channel request
• Each eDMA channel can optionally send an interr upt request to the CPU on completion of a single value or block transfer

1.5.5 Interrupt Controller (INTC)

• 208 peripheral interrupt requests
• 8 software settable sources
• Unique 9-bit vector per interrupt source
• 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source
• Priority elevation for shared resources

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 9

1.5.6 Frequency-Modulated Ph ase-Locked Loop (FMPLL)

Two FMPLLs are available on each device. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor and output clock divider ratio are software configurable. The FMPLLs have the following major features:

• Input frequency: 4–40 MHz continuous ra nge (limited by the crystal oscillator)
• V oltage controlled oscillator (VCO) range: 256–512 MHz
• Frequency modulation via so ftware control to reduce and control emission peaks — Modulation depth ±2% if centere d or 0% to –4% if downshifted via software control register — Modulation frequency: triangular modulation with 25 kHz nominal rate
• Option to switch modulation on and off via software interface
• Reduced frequency divider (RFD) for re duced frequency operation without re-lock
• 2 modes of operation — Normal PLL mode with cr ystal reference (default) — Normal PLL mode with external reference
• Lock monitor circuitry with lock status
• Loss-of-lock detection for re ference and feedback clocks
• Self-clocked mode (SCM) operation
• Auxiliary FMPLL — Used for FlexRay due to precise symb ol rate requirement by the protocol — Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers as well as jitter-free control — Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop — Allows running motor control periphery at differ ent (precisely lower, equal, or higher ,as required) frequency than the system to ensure higher resolution

1.5.7 External Bus Interface (EBI)

• Available on 473-pin devices
• Data and address options: — 16-bit data and address (non-muxed) — 32-bit data and address (bus-muxed)
• MPC5561 324 BGA compatibility mode: 16-bit data bus, 24-bit address bus is default ADDR[8:31], but configurable to 26-bit address bus.
• Memory controller with sup port for various memory types — Non-burst and burst mode SDR flash and SRAM — Asynchronous/legacy flash and SRAM

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor10

• Configurable bus speed modes
• Support for 2 MB address space
• Chip select and write/byte en able options as presented in the pin-muxing table in Section 2, Package pinouts and signal descriptions
• Configurable wait states (via chip selects)
• Optional automatic CLKOUT gating to save power and reduce EMI

1.5.8 On-chip flash memory

• Up to 2 MB Code flash memory with ECC
• 64 KB Data flash memory with ECC
• Censorship protection scheme to prevent flash content visibility
• Multiple block sizes to support features such as boot block, operating system block, and EEPROM emulation
• Read-while-write with multiple partitions
• Parallel programming mode to suppor t rapid end of line programming
• Hardware programming state machine

1.5.9 Cache memory

• Harvard architecture cache
• 16 KB instruction / 16 KB data
• Four-way set-associative Harvard (instruction and data) 256-bit long cache — Two 32-bit fetches per clock — Eight-entry store buffer — Way locking — Supports tag and data parity

1.5.10 On-chip internal static RAM (SRAM)

• Up to 512 KB general-purpose SRAM
• ECC performs single-bit corr ection, double-bit error detection — Address included in ECC checkbase

1.5.11 DRAM controller

The DRAM controller (available only on 473-pin devices) is a multi-port controller that monitors incoming requests on the three AHB slave ports and decides (at each rising clock edge) what command needs to be sent to the external DRAM. The DRAM controller on this device supports the following types of memories:

• Mobile DDR (mDDR)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 11

• DDR 1
• DDR 2 (optional)
• S D R The controller has the following features:
• Optimized timing for 32-byte bursts a nd single read accesses on the AHB interface
• Optimized timing for 8-byte and 16-byte bursts on the DRAMC interface
• Supports priority elevation on the slave ports for single accesses
• 16-bit wide DRAM interface
• One chip select (CS)
• mDDR memory controller — 16-bit external interface — Address range up to 8 MB

1.5.12 Boot Assist Module (BAM)

• Enables booting via serial mode (FlexCAN, LINFlex)
• Handles static mode in case of an erroneous boot procedure
• Implemented in 8 KB ROM
• Supports Lock Step Mode (LSM) and Decoupled Parallel Mode (DPM)

1.5.13 Parallel Data Interface (PDI)

• Support for external ADC and CMOS image sensors
• Parallel interface operation up to MCU system bus frequency
• Selectable data capture fr om rising or falling edge
• Receive FIFO with adjust able trigger thresholds
• Data width for 8, 10, 12, 14, and 16 bits
• Data Packing Unit to pack input data on 64-bit words — data packed on 8- or 16- bit boundary, depending on input data width
• Binary increasing channel select that allows as many as eight channels to be selected
• Frame synchronization th rough Vsync, Hsync, PIXCLK

1.5.14 Deserial Serial Peripher al Interface (DSPI) modules

• Three Serial Peripheral Interfaces — Full duplex communication ports with interrupt and eDMA request support — Support for all functional modes from Q SPI submodule of QSMCM (MPC5xx family) — Support for queues in RAM — Six chip selects, expandable to 64 with external demultiplexers — Programmable frame size, baud rate, clock de lay, and clock phase on a per-frame basis

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor12 — Modified SPI mode for interfacing to peri pherals with longer setup time requirements

• Support for up to 60 Mbit/s in Slave Only Rx mode

1.5.15 Serial communication interface module (LINFlex)

The LINFlex on this device features the following:

• Supports LIN Master mode, LIN Slave mode, and UART mode
• LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
• Manages LIN frame transmission a nd reception without CPU intervention
• LIN features — Autonomous LIN frame handling — Message buffer to store as many as 8 data bytes — Supports messages as long as 64 bytes — Detection and flagging of LIN er rors (Sync field, delimiter, ID parity, bit framing, checksum and time-out errors) — Classic or extended checksum calculation — Configurable break duration of up to 36-bit times — Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) — Diagnostic features (Loop back, LI N bus stuck dominant detection) — Interrupt-driven operation with 16 interrupt sources
• LIN slave mode features — Autonomous LIN header handling — Autonomous LIN response handling
• UART mode — Full-duplex operation — Standard non return-to-zero (NRZ) mark/space format — Data buffers with 4-byte receive, 4-byte transmit — Configurable word length (8-b it, 9-bit, or 16-bit words) — Configurable parity scheme: none, odd, even, always 0 — Speed as fast as 2 Mbit/s — Error detection and flagging (parity, noise, and framing errors) — Interrupt-driven operation wi th four interrupt sources — Separate transmitter and r eceiver CPU interrupt sources — 16-bit programmable baud-rate modul us counter and 16-bit fractional — Two receiver wake-up methods
• Support for DMA-enabled transfers

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 13

1.5.16 FlexCAN

• Thirty-two message buffers each
• Full implementation of the CAN pr otocol specification, Version 2.0B
• Programmable acceptance filters
• Individual Rx filtering per message buffer
• Short latency time for high priority transmit messages
• Arbitration scheme according to me ssage ID or message buffer number
• Listen-only mode capabilities
• Programmable clock source: syst em clock or oscillator clock
• Reception queue possible by sett ing more than one Rx message buffer with the same ID
• Backwards compatible with previous FlexCAN modules
• Safety CAN features on 1 CAN m odule as implemented on MPC5604P

1.5.17 Dual-channel FlexRay controller

• Full implementation of Flex Ray Protocol Specification 2.1
• Sixty-four configurable me ssage buffers can be handled
• Message buffers configurab le as Tx, Rx, or RxFIFO
• Message buffer size configurable
• Message filtering for all messa ge buffers based on FrameID, cycle count, and message ID
• Programmable acceptance filters for RxFIFO message buffers
• Dual channel, each at up to 10 Mbit/s data rate

1.5.18 Periodic Interrupt Timer (PIT)

The PIT module implements the features below:

• Four general-purpose interrupt timers
• 32-bit counter resolution
• Clocked by system clock frequency
• 32-bit counter for real time interrupt, clocked from main external oscillator
• Can be used for software tick or DMA trigger operation

1.5.19 System Timer Module (STM)

The STM implements the features below:

• Duplicated periphery to guarantee that safety targets (SIL3) are achieved
• Up-counter with four output compare registers
• OS task protection and hardware tick implemen tation as per current state-of-the-art AUTOSAR requirement

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor14

1.5.20 Motor control (MOTC) peripherals

The peripherals in this section can be used for general-purpose applications, but are specifically designed for motor control (MOTC) applications.

1.5.20.1 FlexPWM

The pulse width modulator module (FlexPWM) contains three PWM channels, each of which is configured to control a single half-bridge power stage. There may also be one or more fault channels. This PWM is capable of controlling most motor types: AC induction motors (ACIM), Permanent Magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors. A FlexPWM module implements the following features:

• 16 bits of resolution for center, edge aligned, and asymmetrical PWMs
• Maximum operating frequency lower than or equal to platform frequency
• Clock source not modulated a nd independent from system clock (generated via auxiliary PLL)
• Fine granularity control for enha nced resolution of the PWM period
• PWM outputs can operate as compleme ntary pairs or independent channels
• Ability to accept signed numbers for PWM generation
• Independent control of both edges of each PWM output
• Synchronization to external hard ware or other PWM is supported
• Double-buffered PWM registers — Integral reload rates from 1 to 16 — Half-cycle reload capability
• Multiple ADC trigger events can be generated per PWM cycle via hardware
• Fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Independent top and botto m deadtime insertion
• Each complementary pair can operate with its own PWM frequency and deadtime values
• Individual software control for each PWM output
• All outputs can be forced to a value simultaneously
• PWMX pin can optionally output a third signal from each channel
• Channels not used for PWM generation can be used for buffered output compare functions
• Channels not used for PWM generation ca n be used for input capture functions
• Enhanced dual-edge capture functionality
• Option to supply the source for each complement ary PWM signal pair from any of the following: — External digital pin — Internal timer channel

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 15 — External ADC input, taking into account valu es set in ADC high and low limit registers

• DMA support

1.5.20.2 Cross Triggering Unit (CTU)

The CTU provides automatic generation of ADC conversion requests on user selected conditions without CPU load during the PWM period and with minimized CPU load for dynamic configuration. The CTU implements the following features:

• Cross triggering between ADC, Flex PWM, eTimer, and external pins
• Double-buffered trigger generation uni t with as many as eight independent triggers generated from external triggers
• Maximum operating frequency lowe r than or equal to platform
• Trigger generation unit configurable in sequential mode or in triggered mode
• Trigger delay unit to compensate th e delay of external low-pass filter
• Double-buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
• Double-buffered ADC command list point ers to minimize ADC-trigger unit update
• Double-buffered ADC conversion command list with as many as twenty-four ADC commands
• Each trigger has the capability to generate consecutive commands
• ADC conversion command allows controlli ng ADC channel from each ADC, single or synchronous sampling, independent result queue selection
• DMA support with safety features

1.5.20.3 Analog-to-Digital Converter (ADC)

• Four independent ADCs wi th 12-bit A/D resolution
• Common mode conversion range of 0–5 V or 0–3.3 V
• Twenty-two single-ended input channels
• Supports eight FIFO queues with fixed priority
• Queue modes with priority-based preemption; init iated by software command, internal, or external triggers
• DMA and interrupt request support 1.5.20.4 eTimer module Three 16-bit general purpose up/down timer/counters per module are implemented with the following features:
• Ability to operate up to platform frequency
• Individual channel capability — Input capture trigger — Output compare

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor16 — Double buffer (to capture rising edge and falling edge) — Separate prescaler for each counter — Selectable clock source — 0–100% pulse measurement — Rotation direction flag (Quad decoder mode)

• Maximum count rate — Equals peripheral clock/2 for external event counting — Equals peripheral clock for internal clock counting
• Cascadeable counters
• Programmable count modulo
• Quadrature dec ode capabilities
• Counters can share available input pins
• Count once or repeatedly
• Preloadable counters
• Pins available as GPIO when timer functionality not in use
• DMA support

1.5.21 Redundancy Control and Checker Unit (RCCU)

The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:

• Duplicated module to guarantee highest possi ble diagnostic coverage (check of checker)
• Replicated IP to be used as checkers on th e PBRIDGE output, flash controller output, SRAM Output, DMA Channel Mux inputs

1.5.22 Software Watchdog Timer (SWT)

This module implements the features below:

• Duplicated periphery to guarantee that safety targets (SIL3) are achieved
• Fault-tolerant output
• Safe internal RC oscillator as reference clock
• Windowed watchdog
• Program flow control monitor with 16-bit pseudorandom key generation
• Allows high level of safety (SIL3 monitor)

1.5.23 Fault Collection an d Control Unit (FCCU)

The FCCU module has the following features:

• Redundant collection of hardware checker results
• Redundant collection of error information and latc h of faults from critical modules on the device

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 17

• Collection of test results
• Configurable and graded fault control — Internal reactions (no internal reaction, NMI, reset, or safe mode) — External reaction (failure is reported to the outside world via configurable output pins)

1.5.24 System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The SIUL provides the following features:

• Centralized pad control on per-pin basis — Pin function selection — Configurable weak pullup/pulldown — Configurable slew rate c ontrol (slow/medium/fast) — Hysteresis on GPIO pins — Configurable automatic safe mode pad control
• Input filtering for external interrupts

1.5.25 Cyclic Redundan cy Checker (CRC) unit

The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to an input register. The CRC unit has the following features:

• Three sets of register s to allow three concurrent contexts with possibly different CRC computations, each with a selectable polynomial and seed
• Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores the result in an internal register
• Implements the following standard CRC polynomials: — x16 + x12 + x5 + 1 [16-bit CRC-CCITT] — x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 [32-bit CRC-ethernet(32)]
• Key engine to be coupled with communication periphery where CRC application is added to allow implementation of safe communication protocol
• Offloads the core from cycle-consuming CRC a nd helps in checking the configuration signature for safe start-up or periodic procedures
• Connected as a peripheral on the internal peripheral bus
• Provides DMA support

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor18

1.5.26 Non-maskable interrupt (NMI)

The non-maskable interrupt with de-glitching filter is available to support high priority core exceptions.

1.5.27 System Status and Co nfiguration Module (SSCM)

The SSCM on the PXS30 features the following:

• System configuration and status
• Debug port status and debug port enable
• Multiple boot code starting locati ons out of reset through implementation of search for valid Reset Configuration Half Word
• Sets up the MMU to allow user boot code to execute as either Classic PowerPC Book E code (default) or as Freescale VLE code out of flash
• Supports serial bootloading of either Classic Po werPC Book E code (default) or Freescale VLE code
• Detection of user boot code
• Automatic switch to serial boot mode if internal flash is blank or invalid

1.5.28 Nexus Development Interface (NDI)

• Per IEEE-ISTO 5001-2008
• Real-time development support fo r Power Architecture core through Nexus class 3 (some class 4 support)
• Nexus support to snoop system SRAM traffic
• Data trace of FlexRay accesses
• Read and write access
• Configured via the IEEE 1149.1 (JTAG) port
• High bandwidth mode for fast message transmission
• Reduced bandwidth mode for reduced pin usage 1.5.29 IEEE 1149.1 JTAG controller (JTAGC)
• IEEE 1149.1-2001 Test Access Port (TAP) interface
• JCOMP input that provides the ability to shar e the TAP —selectable modes of operation include JTAGC/debug or normal system operation
• 5-bit instruction register that sup ports IEEE 1149.1-2001 defined instructions
• 5-bit instruction register that su pports additional public instructions
• Three test data registers: — Bypass register — Boundary scan register — Device identifi cation register
• TAP controller state machine that controls the ope ration of the data registers, instruction register, and associated circuitry

2 Package pinouts and signal descriptions

2.1 Package pinouts

Figure 2. PXS30 257 MAPBGA pinout (top view)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Package pinouts and signal descriptions Freescale Semiconductor22

2.2 Pin descriptions

The following sections provide signal descriptions and related information about the functionality and configuration for this device.

2.2.1 Pad types

Table 2 lists the pad types used on the PXS30.

2.2.2 Power supply and reference voltage pins

Table 3 shows the supply pins for the PXS30 in the 257 MAPBGA package. Table 5 shows the supply pins for the PXS30 in the 473 MAPBGA package. Table 4 and Table 6 show the pins not populated on the PXS30 257 MAPBGA and 473 MAPBGA packages, respectively. T a b l e2 . P a d t y p e s Pad Type Description GP Slow Slow buffer with CMOS Sc hmitt trigger and pullup/pulldown. GP Slow/Fast Programmable slow/fast buffer with CMOS Schmitt trigger, pullup/pulldown. GP Slow/Medium Programmable slow/medium buffer with CMOS Schmitt trigger, pullup/pulldown. Programmable slow/medium buffer with CMOS Schmitt trigger, pullup/pulldown and Injection proof analog switch. GP Slow/Symmetric Programmable slow/symmetric buffer with CMOS Schmitt trigger, pullup/pulldown. PDI Medium Medium slew-rate output with four sele ctable slew rates. Contains an input buffer and weak pullup/pulldown. PDI Fast Fast slew-rate output with four selectable slew rates. Contains an input buffer and weak pullup/pulldown. DRAM ACC Bidirectional DDR pad. Can be conf igured to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half strength, DDR2 full strength, and SDR. DRAM CLK Differential clock driver DRAM DQ Bidirectional DDR pad with integrated ODT. Can be configured to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half strength, DDR2 full strength, and SDR. DRAM ODT CTL Enable On Die Termination control Analog CMOS Schmitt trigger cell with injection proof analog switch. Analog Shared CMOS Schmitt trigger cell with two injection-proof analog switches.

Table 3. 257 MAPBGA supply pins

Table 5. 473 MAPBGA supply pins Table 3. 257 MAPBGA supply pins (continued)

Table 5. 473 MAPBGA supply pins (continued)

2.2.3 System pins

pins for the PXS30 in the 473 MAPBGA package.

Table 7. 257 MAPBGA system pins 1 Do not connect pin directly to a power supply or ground. Table 8. 473 MAPBGA system pins 1 Do not connect pin directly to a power supply or ground.

2.2.4 Multiplexed pins

Table 9. 257 MAPBGA pin multiplexing

Table 9. 257 MAPBGA pin multiplexing (continued)

1 Do not connect pin directly to a power supply or ground.

Table 10. 473 MAPBGA pin multiplexing

Table 10. 473 MAPBGA pin multiplexing (continued)

1 Do not connect pin directly to a power supply or ground.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

Electrical characteristics

3 Electrical characteristics

3.1 Introduction

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for this device. The “Symbol” column of the electrical parameter and timings tables may contain an additional column

• “SR” identifies system requireme nts—conditions that must be pr ovided to ensure normal device operation. An example is the input voltage of a voltage regulator.
• “CC” identifies specifications that define norm al device operation. Where available, the letters “P”, “C”, “T” or “D” replace the letter “CC” and apply to these controller characteristics. They specify how each characteristic is guaranteed. — P: parameter is guaranteed by production testing of each individual device. — C: parameter is guaranteed by design charac terization. Measurements are taken from a statistically relevant sample size across process variations. — T: parameter is guaranteed by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category. — D: parameters are derived mainly from simulations.

3.2 Absolute maximum ratings

Table 11. Absolute maximum ratings1

13 V DD_HV_ADRx

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 71

3.3 Recommended operating conditions

15 V DD_HV_ADV SR ADC supply voltage —– 0 . 3 3 . 6 4,5 V 16 V SS_HV_ADV SR ADC supply ground —– 0 . 1 0 . 1 V 17 V DD_LV_COR SR Core supply voltage digital logic —– 0 . 3 1 . 3 2 7 V 18 V SS_LV_COR SR Core supply voltage ground digital logic —– 0 . 1 0 . 1 V 19 V DD_LV_PLL SR PLL supply voltage —– 0 . 3 1 . 4 V 20 V SS_LV_PLL SR PLL reference voltage —– 0 . 1 0 . 1 V

21 TV DD SR Slope characteristics on all V DD during power

—— 2 5 m V / µ s

22 V IN SR Voltage on any pin with respect to its supply rail

VDD_HV_xxx Relative to V DD_HV_xxx –0.3 VDD_HV_xxx +0 . 38 V

23 I INJPAD SR Injected input current on any pin during

overload condition (incl. analog pins TBD) — –10 10 mA

24 I INJPADA SR Injected input current on any analog pin during

— –3 3 mA during overload condition — –50 50 mA

26 T STG SR Storage temperature — –55 150 °C

27 T SDR SR Maximum Solder Temperature 9

28 MSL SR Moisture Sensitivity Level 10 —— 3 —

NOTES: 1 Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 TBD V for 10 hours cumulative time, 5.0 V + 10% for time remaining. 4 5.3 V for 10 hours cumulative over lifetime of device, 3.63 V for time remaining. 5 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 6 All VDD_HV_ADRx rails must be operated at the same supply voltage. 7 2.0 V for 10 hours cumulative time, 1.2 V + 10% for time remaining. 8 Only when VDD_HV_xxx < 5.2 V. 9 Solder profile per CDF-AEC-Q100. 10 Moisture sensitivity per JEDEC test method A112. Table 12. Recommended operating conditions1 Table 11. Absolute maximum ratings1 (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 2V SS_HV_PMU SR Voltage regulator supply ground —0 0 V 3V DD_HV_IO SR Input/output supply voltage —3 . 0 3 . 6 V 4V SS_HV_IO SR Input/output supply ground —0 0 V 5V DD_HV_FLA SR Flash supply voltage —3 . 0 3 . 6 V 6V SS_HV_FLA SR Flash supply ground —0 0 V 7V DD_HV_OSC SR Crystal oscillator amplifier supply voltage —3 . 0 3 . 6 V 8V SS_HV_OSC SR Crystal oscillator amplifier supply ground —0 0 V 9V DD_HV_PDI SR PDI interface supply voltage — 1.62 3.6 V

10 V SS_HV_PDI SR PDI interface supply ground —0 0 V

11 V DD_HV_DRAM SR DRAM interface supply voltage — 1.62 3.6 V

12 V SS_HV_DRAM SR DRAM interface supply ground —0 0 V

13 V DD_HV_ADRx SR ADC x high reference voltage —3 . 0 3 . 6 V Alternate input voltage 4.5 5.5

14 V SS_HV_ADRx SR ADC x low reference voltage —0 0 V

15 V DD_HV_ADV SR ADC supply voltage —3 . 0 3 . 6 V

16 V SS_HV_ADV SR ADC supply ground —0 0 V

17 V DD_LV_COR SR Core supply voltage digital logic 2 External VREG

1.14 1.32 V 17a CC Internal VREG Mode 1.14 1.32 V

18 V SS_LV_COR SR Core supply voltage ground digital logic —0 0 V

19 V DD_LV_PLL SR PLL supply voltage 2 External VREG

1.14 1.32 V 19a CC Internal VREG Mode 1.14 1.32 V

20 V SS_LV_PLL SR PLL reference voltage —0 0 V

21 T A SR Ambient temperature under bias 3 257 MAPBGA –40 105 4 °C

473 MAPBGA –40 125 °C

22 T J SR Junction temperature under bias 257 MAPBGA –40 150 °C

473 MAPBGA –40 150

NOTES: 1 These specifications are design targets and are subject to change per device characterization. 2 The jitter specifications for both PLLs holds true only up to 50 mV noise (peak to peak) on VDD_LV_COR and VDD_LV_PLL. 3 See Table 1 for available frequency and package options. 4 Preliminary data. Table 12. Recommended operating conditions1 (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 73

3.4 Thermal characteristics

3.4.1 General notes for specificatio ns at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from Equation 1: TJ =T A +( RJA ×P D) Eqn. 1 where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer Table 13. Thermal characteristics for package options1 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. meets JEDEC specification for this package. specification for the specified package. temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. parameter is written as Psi-JT.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA =R JC + RCA Eqn. 2 where: RJA = junction to ambient thermal resistance (°C/W) RJC = junction to case thermal resistance (°C/W) RCA = case to ambient thermal resistance (°C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: TJ =T T +( JT ×P D) Eqn. 3 where: TT = thermocouple temperature on top of the package (°C) JT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. See [6] to [10] in Section 6, Reference documents, for more information.

3.5 Electromagnetic interference (EMI) characteristics

3.5.1 Test Setup

Electromagnetic emission tests are performed by TEM cell [2] and via direct coupling [3] (150 Ohm) measurements. Electromagnetic immunity are measured by DPI [4].

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 75 See Section 6, Reference documents, for more information.

3.5.2 Test parameters

The following test parameters shall be used: In case of only narrow band disturbances the maximum of the results will not change. In case of broadband signals the emission has to be below the limits.

3.6 Electrostatic discharge (ESD) characteristics

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.

3.7 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply over voltage is applied to each power supply pin.
• A current injection is applied to eac h input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 14. EMC test parameters

150 Ohm 1 MHz to 1000 MHz 1 MHz 500 kHz

Table 15. ESD ratings1, 2 3 Data based on characterization results, not tested in production.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.8 Power Management Controller (PMC) electrical characteristics

3.8.1 PMC electrical specifications

This section contains electrical characteristics for the PMC. Table 16. Latch-up results Table 17. PMC electrical specifications

7 PorReg CC POR rising on VDDREG

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 77

3.8.2 PMC board schematic and components

Figure 7 shows a sample application for the PMC. Figure 7. PMU mandatory external components Table 18. VRC SMPS recommended external devices

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.9 Supply current characteristics

3.10 Temperature sensor electrical characteristics

Table 19. Current consumption characteristics1 code flash 1, FMPLL_1 active at 120 MHz. 2 Total current on IDD_LV_PLL needs to be multiplied with the number of active PLLs. 3 Total current on IDD_HV_ADV needs to be multiplied with the number of active ADCs. 5 Total current on IDD_HV_ADRxx is the sum of both references if both ADCs are powered on. 6 ADC0 includes 0.7 mA dissipation for the temperature sensor (TSENS).

4 CC Maximum reference

7 CC Maximum reference

10 I DD_HV_ADR23

Table 20. Temperature sensor electrical characteristics

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 79

3.11 Main oscillator electrical characteristics

The PXS30 provides an oscillator/resonator driver.

3.12 FMPLL electrical characteristics

2T S D Minimum sampling period — 4 — µs Table 21. Main oscillator electrical characteristics 1 VDD = 3.0 V to 3.6 V, TJ = –40 to 150 °C, unless otherwise specified. Table 22. FMPLL electrical characteristics Table 20. Temperature sensor electrical characteristics (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice tLOCK P Lock time Stable oscillator (f PLLIN = 4 MHz), stable VDD — — 200 µs tlpll D FMPLL lock time 5, 6 —— — TBD s tdc D Duty cycle of reference —4 0 — 6 0 % CJITTER T CLKOUT period jitter 7,8,9,10 Peak-to-peak (clock edge to clock edge), fSYS maximum TBD — TBD ps Long-term jitter (avg. over 2 ms interval), fSYS maximum TBD — TBD ns tPKJIT T Single period jitter (peak to peak) PHI @ 16 MHz, Input clock @ 4 MHz —— ±500 ps tLTJIT T Long term jitter PHI @ 16 MHz, Input clock @ 4 MHz —— ±6 ns fLCK D Frequency LOCK range — TBD — TBD % fsys fUL D Frequency un-LOCK range — TBD — TBD % fsys fCS fDS D Modulation Depth Center spread TBD — TBD % fsysDown Spread TBD — TBD fMOD D Modulation frequency 11 — TBD — TBD kHz NOTES: 1 Considering operation with FMPLL not bypassed. 2 “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked mode. 3 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the fLOR window. 4 fVCO is the frequency at the output of the VCO; its range is 256–512 MHz. fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz. fSYS =f VCOODF 5 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this FMPLL, load capacitors should not exceed these limits. 6 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 7 This value is determined by the crystal manufacturer and board design. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 9 Proper PC board layout procedures must be followed to achieve specifications. 10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 11 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz. Table 22. FMPLL electrical characteristics (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 81 3.13 16 MHz RC oscillator electrical characteristics

3.14 ADC electrical characteristics

The PXS30 provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter. Figure 8. ADC characteristics and error definitions Table 23. RC oscillator electrical characteristics

1 LSB (ideal)

1 LSB ideal =(VrefH-VrefL)/ 4096 =

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.14.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ =1 / ( fC CS), where fC represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS +R F +R L +R SW +R AD, the external circuit must be designed to respect the Equation 9: Eqn. 9 Equation 9 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 10. Input equivalent circuit

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Eqn. 16 Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 17 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 17 The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Figure 18. Spectral representation of input signal the time in which the sampling switch is closed.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 85 From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 20 Table 24. ADC conversion characteristics 1 VDD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF. 2 AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

5 D ADC input pin capacitance 2 —— — T B D p F

10 R AD

5 D Sample switching resistance — — — 825 

11 I INJ T Current injection Current injection on one ADC

12 INL P Integral non linearity —– 3 — 3 L S B

13 DNL P Differential non linearity

14 OFS T Offset error —– 4 — 4 L S B

15 GNE T Gain error —– 4 — 4 L S B

16 TUE P Total unadjusted error —– 6 — 6 L S B

17 TUE T Total unadjusted error with current injection — TBD — TBD LSB

18 SNR T Signal-to-noise ratio —6 9 — — d B

19 THD T Total harmonic distortion —T B D — — d B

20 SINAD T Signal-to-noise and distortion —6 5 — — d B

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 3 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. 4 This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result register with the conversion result. 5 See Figure 10. 6 No missing codes.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 87

3.15 Flash memory electrical characteristics

3.15.1 Program/Erase characteristics

Table 25 shows the Code flash memory program and erase characteristics. Table 26 shows the Data flash memory program and erase characteristics. Table 25. Code flash program and erase electrical specifications change pending device characterization. 3 Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values are characterized, but not tested. 4 Actual hardware programming times. This does not include software overhead. Table 26. Data flash program and erase electrical specifications change pending device characterization. 3 Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values are characterized, but not tested. 4 Actual hardware programming times. This does not include software overhead.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.15.2 Read access timing

3.15.3 Write access timing

Table 27. Flash module life Typical Endurance for Nonvolatile Memory.

16 KB blocks 100,000 — — cycles

2 Retention CC Minimum data retention at

2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range. Table 28. Code flash read access timing Table 29. Data flash read access timing Table 30. Code flash write access timing

3 TBD 60 MHz

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 89

3.16 SRAM memory electrical characteristics

3.16.1 Read access timing

3.16.2 Write access timing

3.17 GP pads specifications

This section specifies the electrical characteristics of the GP pads. Please refer to the tables in Section 2.2, Pin descriptions,” for a cross reference between package pins and pad types.

3.17.1 GP pads DC specifications

Table 34 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IO < 3.6 V). Table 31. Data flash write access timing Table 32. System SRAM memory read access timing Table 33. System SRAM memory write access timing

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Table 34. GP pads DC electrical characteristics 1,2 1 These specifications are design targets and subject to change per device characterization. 2 The values provided in this table are not applicable for PDI and EBI/DRAM interface. 3 “SR” parameter values must not exceed the absolute maximum ratings shown in Table 11.

0.35 VDD_HV_IO V

12 I PU CC Equivalent pull-up current VIN =V IL –130 — µA

13 I PD CC Equivalent pull-down current VIN =V IL 10 — µA

14 I IL CC Input leakage current

15 I IL CC Input leakage current

20 I PD CC RESET, equivalent pull-down current VIN =V IL 10 — µA

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 91

3.17.2 GP pads AC specifications

3.18 PDI pads specifications

This section specifies the electrical characteristics of the PDI pads. Please refer to the tables in Section 2.2, Pin descriptions,” for a cross reference between package pins and pad types. PDI pads feature list:

• Direction — Input — Output — Bidirectional
• Driver — Push/Pull/Open Drain — Configurable Four Drive Strengths on Fast driver pads

Table 35. GP pads AC electrical characteristics1 1 The values provided in this table are not applicable for PDI and EBI/DRAM interface. 2 Slope at rising/falling edge. 3 Data based on characterization results, not tested in production.

4 S y m m e t r i c1—8 1—5— — 5 03— 2 5 2 5

5 Pull Up/Down

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice — Configurable No Slew-R ate, Slow Slew-Rate, and Fast Slew-Rate on Slow, Medium, and SLR driver pads — VDD_HV_PDI NOTE: All pads ar e NOT 5 V TOLERANT. Pads are not capable of driving to or from voltages above their respective VDD_HV_PDI. In other words, you cannot connect a 3.3V external device to a pad supplied with 2.5 V . If a pad must be connected to a 3.3V device, its local VDD_HV_PDI must be 3.3V . Injection current is then handled by the intrinsic diodes from the pad transistors and by the ESD diodes. — VDD_HV_PDI range – 1.8 V nominal – 2.5 V nominal – 3.3 V nominal

• Receiver — Selectable hysteresis Input Buffer. — CMOS Input Buffer The electrical data provided in Section 3.18, PDI pads specifications,” applies to the pads listed in Table 36. 3.18.1 PDI pads electr ical specifications (VDD_HV_PDI = 3.3 V)

Table 36. PDI I/O pads slew-rates. Contains an input buffer and weak pullup/pulldown. selectable slew-rates. Contains an input buffer and weak pullup/pulldown. Table 37. PDI pads DC electrical characteristics (VDD_HV_PDI = 3.3 V)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 93 3.18.2 PDI pads electr ical specifications (VDD_HV_PDI = 2.5 V) Table 38. Drive Current, VDD_HV_PDI = 3.3 V (±10%) 1 IOH is defined as the current sourced by the pad to drive the output to VOH. 2 IOL is defined as the current sunk by the pad to drive the output to VOL. Table 39. PDI pads AC electrical characteristics (VDD_HV_PDI = 3.3 V) 1 L  H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay. Table 40. PDI pads DC electrical specifications (VDD_HV_PDI = 2.5 V)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 3V IH_C CC CMOS input buffer high voltage (hysteresis disabled) 0.54 × VDD_HV_PDI VDD_HV_PDI +0 . 3 V 4V IL_C CC CMOS input buffer low voltage (hysteresis enabled) Vss – 0.3 0.35 × V DD_HV_PDI V 5V IL_C CC CMOS input buffer low voltage (hysteresis disabled) Vss – 0.3 0.42 × V DD_HV_PDI V 6V HYS_C CC CMOS input buffer hysteresis 0.1 × VDD_HV_PDI V 7I ACT_S CC Selectable weak pullup/pulldown current1 25 150 µA 9V OH CC Output high voltage 0.8 × VDD_HV_PDI —V 10 V OL CC Output low voltage —0 . 2 × V DD_HV_PDI V Table 41. Drive Current @ VDD_HV_PDI = 2.5 V (±10%) 1 IOH is defined as the current sourced by the pad to drive the output to VOH. Table 42. PDI pads AC electrical specifications (VDD_HV_PDI = 2.5 V) Table 40. PDI pads DC electrical specifications (VDD_HV_PDI = 2.5 V) (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 95 3.18.3 PDI pads electr ical specifications (VDD_HV_PDI = 1.8 V) 2 PDI Fast 0.8/0.7 1.1/1.08 8.6/8.6 3/3 50 10 14/14 5.6/5.6 200 22/22 9.5/9.5 200 48/48 19/19 50 00 60/60 25/25 200 NOTES: 1 L  H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay. Table 43. PDI pads DC electrical specifications (VDD_HV_PDI = 1.8 V) Table 44. Drive current @ VDD_HV_PDI = 1.8 V (±10%) 1 IOH is defined as the current sourced by the pad to drive the output to VOH. 2 IOL is defined as the current sunk by the pad to drive the output to VOL. Table 42. PDI pads AC electrical specifications (VDD_HV_PDI = 2.5 V) (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.19 DRAM pad specifications

This section specifies the electrical characteristics of the DRAM pads. Please refer to the tables in Section 2.2, Pin descriptions,” for a cross reference between package pins and pad types. DRAM pads feature list:

• Driver — Configurable to support LPDDR half stre ngth, LPDDR full strength, DDR1, DDR2 half strength, DDR2 full strength, and SDR modes. — VDD_HV_DRAM Range of – 1.8 V nominal – 2.5 V nominal – 3.3 V nominal
• Receiver — Differential or pseudo-differential input buffer in all DRAM pads

Table 45. PDI pads AC electrical specifications (VDD_HV_PDI = 1.8 V) 1 L  H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay.

2 PDI Fast — 10/10 2/2 — 50 11

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 97 — All inputs are tolerant up to their VDD_HV_DRAM Absolute Maximum Rating — Data and strobe pads can be configured to support four signal termination options – Infinite/no termination – 50 Ohms – 75 Ohms – 150 Ohms The electrical data provided in Section 3.19, DRAM pad specifications,” applies to the pads listed in Table 46. All three pad types can be configured to support SDR, DDR, DDR2 half and full strength, and LPDDR half and full strength modes, according to Table 47. 3.19.1 DRAM pads electrical specifications (VDD_HV_DRAM = 3.3 V) Table 46. DRAM pads

1 All pads can be configured to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half

strength, DDR2 full strength, and SDR. Table 47. Mode configuration for DRAM pads 1 Configuration is selected in the corresponding PCR registers of the SIUL.

100 Not supported

101 Not supported

111 SDR

Table 48. DRAM pads DC electrical specifications (VDD_HV_DRAM = 3.3 V)

2 VDD_HV_DRAM_VREF CC Input reference

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3 VDD_HV_DRAM_VTT CC Termination voltage1 —V DD_HV_DRAM_VREF

× 0 . 0 5 VDD_HV_DRAM_VREF +0 . 0 5 V 4V IH CC Input high voltage —V DD_HV_DRAM_VREF + 0.20 5V IL CC Input low voltage —V DD_HV_DRAM_VREF × 0 . 2 V 6V OH CC Output high voltage ODT enabled2 VDD_HV_DRAM_VTT +0 . 8 ODT disabled3 0.8 × VDD_HV_DRAM —V 7V OL CC Output low voltage ODT enabled2 —V DD_HV_DRAM_VTT × 0 . 8 V ODT disabled3 —V DD_HV_DRAM ×0 . 2 V NOTES: 1 BGA473: Termination voltage can be supplied via package pins. BGA257 Termination voltage internally tied as the BGA257 does not provide DRAM interface. Disable ODT 2 Termination voltage is supplied by VDD_HV_DRAM_VTT.

3 Tie VDD_HV_DRAM_VTT to VSS and disable ODT

Table 49. Output drive current @ VDDE = 3.3 V (±10%)

1 DRAM ACC 111 –16 16

2 DRAM DQ

3 DRAM CLK

1 IOH is defined as the current sourced by the pad to drive the output to VOH. 2 IOL is defined as the current sunk by the pad to drive the output to VOL. Table 50. DRAM pads AC electrical specifications (VDD_HV_DRAM = 3.3 V) Table 48. DRAM pads DC electrical specifications (VDD_HV_DRAM (continued) = 3.3 V)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 99 3.19.2 DRAM pads electrical specification (VDD_HV_DRAM = 2.5 V) NOTES: 1 L  H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay. Table 51. DRAM pads DC electrical specifications (VDD_HV_DRAM = 2.5 V) 2 Termination voltage is supplied by VDD_HV_DRAM_VTT. Table 52. Output drive current @ VDDE = 2.5 V (±200 mV) 1 IOH is defined as the current sourced by the pad to drive the output to VOH. 2 IOL is defined as the current sunk by the pad to drive the output to VOL.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor100 3.19.3 DRAM pads electrical specification (VDD_HV_DRAM = 1.8 V) Table 53. DRAM pads AC electrical specifications (VDD_HV_DRAM = 2.5 V) 1 L  H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay. Table 54. DRAM pads DC electrical specifications (VDD_HV_DRAM = 1.8 V) 2 Termination voltage is supplied by VDD_HV_DRAM_VTT.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 101 Table 55. Output drive current @ VDDE = 1.8 V (±100 mV) 1 IOH is defined as the current sourced by the pad to drive the output to VOH. 2 IOL is defined as the current sunk by the pad to drive the output to VOL. Table 56. DRAM pads AC electrical specifications (VDD_HV_DRAM = 1.8 V)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor102

3.20 RESET characteristics

3.20.1 RESET pin characteristics

3.21 Reset sequence

This section shows the duration for different reset sequences. It describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences depending on internal or external VREG mode. NOTES: 1 L  H signifies low-to-high propagation delay and H  L signifies high-to-low propagation delay. Table 57. RESET pin characteristics Table 56. DRAM pads AC electrical specifications (VDD_HV_DRAM (continued) = 1.8 V)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 103

3.21.1 Reset sequence duration

Table 58 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in Section 3.21.2, Reset sequence description.”

3.21.2 Reset sequence description

The figures in this section show the internal states of the PXS30 during the five different reset sequences. The doted lines in the figures indicate the starting point and the end point for which the duration is specified in Table 58. The start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.21.3, Reset sequence trigger mapping.” With the beginning of DRUN mode, the first instruction is fetched and executed. At this point, application execution starts and the internal reset sequence is finished. The following figures show the internal states of the PXS30 during the execution of the reset sequence and the possible states of the RESET signal pin. NOTE RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an external reset generator or by the PXS30 internal reset circuitry. A high level on this pin can only be generated by an external pull up resistor which is strong enough to overdrive the weak internal pull down resistor. The rising edge on RESET in the following figures indicates the time when the device stops driving it low. The reset sequence durations given in Table 58 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET asserted low beyond the last PHASE3. Table 58. RESET sequences RESET by an external reset generator.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 105 Figure 24. Functional reset sequence long Figure 25. Functional reset sequence short

3.21.3 Reset sequence trigger mapping

sequence end indications that are the basis for the timing data provided in Table 58.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor106 Table 59. Reset sequence trigger—reset sequence 1 VREG Mode: I = Internal VREG Mode, E = External VREG Mode. 2 Whether BIST is executed or not depends on device configuration data stored in the shadow sector of the NVM. 4 In external VREG mode only. 5 The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 107

3.21.4 Reset sequence—start condition

The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration.

3.21.4.1 Internal VREG mode

Figure 26 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled. The last voltage rail crossing the levels shown in Figure 26 determines the start of the reset times specified in Table 58. Figure 26. Reset sequence start in internal VREG mode

3.21.4.2 External VREG mode

Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled. 8 If RESET is configured for short reset. reset source which triggered the reset sequence. Table 60. Voltage thresholds

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 109 3.21.4.3 external Reset via RESET Figure 29 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of RESET as specified in Table 59. Figure 29. Reset sequence start via RESET assertion

3.21.5 External w atchdog window

sequence can be used to determine the correct positioning of the trigger window for the external watchdog. sequence and the position of an external watchdog trigger window. Figure 30. Reset sequence—external watchdog trigger window position

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor110

3.22 Peripheral timing characteristics

3.22.1 SDRAM (DDR)

The PXS30 memory controller supports three types of DDR devices:

• DDR-1 (SSTL_2 class II interface)
• DDR-2 (SSTL_18 interface)
• LPDDR/Mobile-DDR (1.8V I/O supply voltage) JEDEC standards define the minimum set of requirements for compliant memory devices:
• JEDEC STANDARD, DDR2 SDRAM SPEC IFICATION, JESD79-2C, MAY 2006
• JEDEC STANDARD, Double Data Rate (D DR) SDRAM Specification, JESD79E, May 2005
• JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006 The PXS30 supports the configuration of two output drive strengths for DDR2 and LPDDR:
• Full drive strength
• Half drive strength (intended for lighter loads or point-to-point environments) The PXS30 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device. This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the Section 3.19, DRAM pad specifications.”

3.22.1.1 DDR and DDR2 SDRAM AC timing specifications

Table 61. DDR and DDR2 (DDR2-400) SDRAM timing specifications

2 VIX-AC CC MCK AC differential crosspoint voltage1 VDD_MEM_IO

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor114 Figure 37. JTAG boundary scan timing

3.22.3 Nexus timing

Table 63. Nexus debug port timing1

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 115 Figure 38. Nexus output timing

3.22.4 External interrupt timing (IRQ pins)

measured from 50% of MCKO and 50% of the respective signal. 2 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3 The system clock frequency needs to be three times faster than the TCK frequency. Table 64. External interrupt timing (NMI IRQ) 1 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. Table 65. External interrupt timing (GPIO IRQ) 1 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor116 Figure 39. External interrupt timing

3.22.5 FlexCAN timing

3.22.6 DSPI timing

Table 66. FlexCAN timing Table 67. DSPI timing

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 117 9t SUI CC Data setup time for inputs Master (MTFE = 0) 20 — ns Slave 2— Master (MTFE = 1, CPHA = 0) 5— Master (MTFE = 1, CPHA = 1) 20 — 10 t HI CC Data hold time for inputs Master (MTFE = 0) –5 — ns Slave 4— Master (MTFE = 1, CPHA = 0) 11 — Master (MTFE = 1, CPHA = 1) –5 — 11 t SUO CC Data valid (after SCK edge) Master (MTFE = 0) —4 n s Slave —2 3 Master (MTFE = 1, CPHA = 0) —1 1 Master (MTFE = 1, CPHA = 1) —5 12 t HO CC Data hold time for outputs Master (MTFE = 0) –2 — ns Slave 6— Master (MTFE = 1, CPHA = 0) 6— Master (MTFE = 1, CPHA = 1) –2 — 13 t DT CC Delay after Transfer (minimum CS negation time) Continuous mode Non-continuos mode2 134 ns NOTES: 1 Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. Note that in this mode, the DSPI can receive data on SIN, but no valid data is transmitted on SOUT. 2 In non-continuous mode, this value is always tSCK × DSPI_CTARn[DT] × DSPI_CTARn[PDT]. The minimum permissible value of DT is 2 and the minimum permissible value of PDT is 1. See the DSPI chapter of the PXS30 Reference Manual (PXS30RM) for more information. Table 67. DSPI timing (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor122 Figure 48. Example of non-continuous format (CPHA = 1, CONT = 0) Figure 49. Example of continuous transfer (CPHA = 1, CONT = 1) Figure 50. DSPI PCS strobe (PCSS) timing

3.22.7 PDI timing

Table 68. PDI electrical characteristics

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 123

3.22.8 Fast ethernet interface

MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V . Signals are not TTL compatible. They follow the CMOS electrical characteristics.

3.22.8.1 MII receive signal timing (R XD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency. 2t PDI_IS SR Input setup time1 —3 — n s 3t PDI_IH SR Input hold time1 —3 — n s NOTES: 1 Data can be captured at both launching and capturing edge of PDI_CLK. PDI timing Table 69. MII receive signal timing

1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5— n s

2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5— n s

3 RX_CLK pulse width high 40% 60% RX_CLK period

4 RX_CLK pulse width low 40% 60% RX_CLK period

Table 68. PDI electrical characteristics (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor124 Figure 51. MII receive signal timing diagram

3.22.8.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

Refer to the Ethernet chapter for details of this option and how to enable it. Figure 52. MII transmit signal timing diagram Table 70. MII transmit signal timing1 1 Output pads configured with SRC = 0b11.

5 TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5— n s

6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid —2 5 n s

7 TX_CLK pulse width high 40% 60% TX_CLK period

8 TX_CLK pulse width low 40% 60% TX_CLK period

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 125

3.22.8.3 MII async inputs sign al timing (CRS and COL)

Figure 53. MII async inputs timing diagram

3.22.8.4 MII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 5 MHz. Table 71. MII async inputs signal timing1 1 Output pads configured with SRC = 0b11. Table 72. MII serial management channel timing1 1 Output pads configured with SRC = 0b11.

10 MDC falling edge to MDIO output invalid (minimum propagation delay) 0— n s

11 MDC falling edge to MDIO output valid (max prop delay) —2 5 n s

12 MDIO (input) to MDC rising edge setup 10 — ns

13 MDIO (input) to MDC rising edge hold 0— n s

14 MDC pulse width high 40% 60% MDC period

15 MDC pulse width low 40% 60% MDC period

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor126 Figure 54. MII serial management channel timing diagram

3.22.9 External Bus Interface (EBI) timing

Table 73. EBI timing

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 127 6 tCOV CC D_CLKOUT posedge to output signal valid (output delay) D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3] —1 0 n s — 7 tCIS CC Input signal valid to D_CLKOUT posedge (setup time) D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 7.5 — ns — 8 tCIH CC D_CLKOUT posedge to input signal invalid (hold time) D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 1.0 — ns — 9 tAPW CC D_ALE pulse width 6.5 — ns The timing is for Asynchronous external memory system. 10 t AAI CC D_ALE negated to address invalid 1.5 — ns The timing is for Asynchronous external memory system. ALE is measured at 50% of VDDE. NOTES: 1 Speed is the nominal maximum frequency. Maximum core speed allowed is 180 MHz plus frequency modulation (FM). Table 73. EBI timing (continued)

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor130

3.22.10 I 2C Timing

Table 74. I2C SCL and SDA input timing specifications 1 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device. Table 75. I2C SCL and SDA output timing specifications listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device. or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.

PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 131 Figure 59. I2C input/output timing

3.22.11 LINFlex timing

The maximum bit rate is 1.875 MBit/s.

4 Package characteristics

4.1 Package mechanical data

Figure 60. 257 MAPBGA mechanical data (1 of 2)

Figure 61. 257 MAPBGA mechanical data (2 of 2)

Figure 62. 473 MAPBGA package mechanical data (1 of 3)

Figure 63. 473 MAPBGA package mechanical data (2 of 3)

Figure 64. 473 MAPBGA package mechanical data (3 of 3)

5 Orderable parts

Figure 65. PXS30 orderable part number description

6 Reference documents

1. Measurement of emission of ICs—IEC 61967-2
2. Measurement of emission of ICs—IEC 61967-4
3. Measurement of imm unity of ICs—IEC 62132-4
4. Semiconductor Equipment a nd Materials International

3081 Zanker Road

1. JEDEC specifications are avai lable at http://www.jedec.org
2. MIL-SPEC and EIA/JESD (JEDEC ) specifications are available from Global Engineering

Table 76. PXS30 orderable part number summary Note: Not all options are available on all devices. See Table 76 for more information.

1. C.E. Triplett and B. Joiner, “An Experiment al Characterization of a 272 PBGA Within an

Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

1. G . Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled

Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.

1. B. Joiner and V . Adams, “Measurement and Simulation of Junction to Board Thermal Resistance

and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.

7 Document revision history

Table 77 summarizes revisions to this document. Table 77. Revision history 1 30 Sep 2011 Initial release.

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