MPXN2010VMM80R

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Data Sheet: Advance Information Document Number: PXS20 Rev. 1, 09/2011 © Freescale Semiconductor, Inc., 2011. All rights reserved. Preliminary—Subject to Change Without Notice This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. PXS20 TBD MAPBGA–225 15 mm x 15 mm QFN12 SOT -343R PKG-TBD ## mm x ## mm

257 MAPBGA

(14 x 14 x 0.8 mm) (20 x 20 x 1.4 mm)

144 LQFP

• High-performance e200z4d dual core – 32-bit Power Architecture ® technology CPU – Core frequency as high as 120 MHz – Dual issue five-stage pipeline core – Variable Length Encoding (VLE) – Memory Management Unit (MMU) – 4 KB instruction cache with error detection code – Signal processing engine (SPE)
• Memory available – 1 MB flash memory with ECC – 128 KB on-chip SRAM with ECC – Built-in RWW capabilities for EEPROM emulation
• SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection – Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch) – Fault collection and control unit (FCCU) – Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU – Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware – Boot-time Built-In Self-Test for ADC and flash memory triggered by software – Replicated safety enhanced watchdog – Replicated junction temperature sensor – Non-maskable interrupt (NMI) – 16-region memory protection unit (MPU) – Clock monitoring units (CMU) – Power management unit (PMU) – Cyclic redundancy check (CRC) unit
• Decoupled Parallel mode for high-performance use of replicated cores
• Nexus Class 3+ interface
• Interrupts – Replicated 16-prio rity controller – Replicated 16-channel eDMA controller
• GPIOs individually programmable as input, output or special function
• Three 6-channel general-purpose eTimer units
• 2 FlexPWM units – Four 16-bit channels per module
• Communications interfaces – 2 LINFlexD channels – 3 DSPI channels with automatic chip select generation – 2 FlexCAN interfaces (2.0B Active) with 32 message objects – FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s
• Two 12-bit analog-to-digital converters (ADCs) – 16 input channels – Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM
• Sine wave generator (D/A with low pass filter)
• On-chip CAN/UART bootstrap loader
• Single 3.0 V to 3.6 V voltage supply
• Ambient temperature range –40 °C to 125 °C
• Junction temperature range –40 °C to 150 °C PXS20 Microcontroller Data Sheet

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor2 Table of Contents

1.5.14 Frequency-Modulated Phase-Locked Loop

1.5.17 Clock, Reset, Power Mode, and Test Control

Modules (MC_CGM, MC_RGM, MC_PCU, and

1.5.25 System Status and Configuration Module (SSCM) 15

1.5.28 Serial Communication Interface Module (UART)16

1.5.37 Redundancy Control and Checker Unit (RCCU)21

1.5.38 Voltage Regulator / Power Management Unit (PMU)21

3.4.1 General notes for specifications at maximum

3.5 Electromagnetic Interference (EMI) characteristics (cut1) 77

3.20.1 RESET

1 Introduction

1.1 Document overview

electrical and physical characteristics of the devices. PXS20 in a fail-safe system according to safety standard IEC 61508, see the Safety Application Guide for MPC5643L. this document. Functional differences between the two cuts are clearly identified with the labels “cut1” and “cut2”.

1.2 Description

converter, Controller Area Network, and an enhanced modular input-output system. systems and configuration code to assist with users’ implementations.

1.3 Device comparison

Table 1. PXS20 Family Feature Set

3.3 V with integrated bypassable ballast transistor

Table 1. PXS20 Family Feature Set (continued)

1.4 Block diagram

Figure 1 shows a top-level block diagram of the PXS20 device. Figure 1. PXS20 block diagram

1 MB Flash (ECC)

128 KB SRAM (ECC)

Figure 2. PXS20 block diagram (continued)

1.5 Feature details

1.5.1 High-Performance e200z4d Core

• 2 independent execution units, both supporting fixed-point and floating-point operations
• Dual issue 32-bit Power Architecture ® technology compliant — 5-stage pipeline (IF, DEC, EX1, EX2, WB) — In-order execution and instruction retirement
• Full support for Power Architecture ® instruction set and Variable Length Encoding (VLE) — Mix of classic 32-bit and 16-bit instruction allowed — Optimization of code size possible
• Thirty-two 64-bit general purpose registers (GPRs)
• Harvard bus (32-bit address, 64-bit data) — I-Bus interface capable of one outstanding transac tion plus one piped with no wait-on-data return — D-Bus interface capable of two trans actions outstanding to fill AHB pipe
• I-cache and I-cache controller — 4 KB, 256-bit cache line (pr ogrammable for 2- or 4-way)
• No data cache
• 16-entry MMU
• 8-entry branch table buffer
• Branch look-ahead instructio n buffer to accelerate branching
• Dedicated branch address calculator
• 3 cycles worst case for missed branch
• Load/store unit — Fully pipelined — Single-cycle load latency — Big- and little-endian modes supported ADC – Analog-to-digital converter BAM – Boot assist module CAN – Controller area network controller CMU – Clock monitoring unit CRC – Cyclic redundancy check unit CTU – Cross Triggering Unit ECC – Error correction code ECSM – Error correction status module eDMA – Enhanced direct memory access controller FCCU – Fault collection and control unit FMPLL – Frequency modulated phase locked loop INTC – Interrupt controller IRCOSC – Internal RC oscillator JTAG – Joint Test Action Group interface MC – Mode entry, clock, reset, & power PBRIDGE – Peripheral I/O bridge PIT – Periodic interrupt timer PMU – Power management unit PWM – Pulse width modulator module RC – Redundancy checker RTC – Real time clock SEMA4 – Semaphore unit SIUL – System integration unit lite SPI – Serial peripherals interface controller SSCM – System status and configuration module STM – System timer module SWG – Sine wave generator SWT – Software watchdog timer TSENS – Temperature sensor UART/LIN – Universal asynchronous receiver/transmitter/ local interconnect network WKPU – Wakeup unit XOSC – Crystal oscillator

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor8 — Misaligned access support — Single stall cycle on load to use

• Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
• 4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)
• Single precision floating-point unit — 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication — Target 9 cycles (worst case acceptable is 12 cy cles) throughput floating-point 32 × 32 division — Special square root and min/max function implemented
• Signal processing support: APU-SPE 1.1 — Support for vectorized mode: as many as two floating-point instructions per clock
• Vectored interrupt support
• Reservation instruction to support read-modify-write constructs
• Extensive system development and tracing support via Nexus debug port

1.5.2 Crossbar Switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. The crossbar provides the following features:

• 4 masters and 3 slaves suppor ted per each replicated crossbar — Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D access (2 masters), one eDMA, one FlexRay — Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1 redundant peripheral bus bridge
• 32-bit address bus and 64-bit data bus
• Programmable arbitration priority — Requesting masters can be treated with equal priority a nd are granted access to a slave port in round-robin method, based upon the ID of the last master to be granted access or a priority order can be assigned by software at application run time
• Temporary dynamic priori ty elevation of masters The XBAR is replicated for each processor.

1.5.3 Memory Protection Unit (MPU)

The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be assigned different access rights to each region.

• 16-region MPU with concurrent checks against each master access
• 32-byte granularity for protected address region The memory protection unit is replicated for each processor.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 9

1.5.4 Enhanced Direct Memory Access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is used to minimize the overall block size. The eDMA module provides the following features:

• 16 channels supporting 8-, 16-, and 32 -bit value single or block transfers
• Support variable sized queues and circular buffered queue
• Source and destination address registers independently configured to post-increment or stay constant
• Support major and minor loop offset
• Support minor and major loop done signals
• DMA task initiated either by hardware requestor or by software
• Each DMA task can optionally generate an inte rrupt at completion and retirement of the task
• Signal to indicate closure of last minor loop
• Transfer control descriptors mapped inside the SRAM The eDMA controller is replicated for each processor.

1.5.5 On-Chip Flash Memory with ECC

This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz. The flash memory module provides the following features

• 1 MB of flash memory in unique multi-partitioned hard macro
• Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
• EEPROM emulation (in software) within same module but on different partition
• 16 KB test sector and 16 KB shadow sector for test, censorship device and user option bits
• Wait states: — 3 wait states at 120 MHz — 2 wait states at 80 MHz — 1 wait state at 60 MHz
• Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
• Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
• 1-bit error correction, 2-bit error detection

1.5.6 On-Chip SRAM with ECC

The PXS20 SRAM provides a general-purpose single port memory. ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic coverage including the array internal address decoder. The SRAM module provides the following features:

• System SRAM: 128 KB

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor10

• ECC on 32-bit word (syndrome of 7 bits) — ECC covers SRAM bus address
• 1-bit error correction, 2-bit error detection
• Wait states: — 1 wait state at 120 MHz — 0 wait states at 80 MHz and 60 MHz

1.5.7 Platform Flash Memory Controller

The following list summarizes the key features of the flash memory controller:

• Single AHB port interface supports a 64-bi t data bus. All AHB aligned and unaligned reads within the 32-bit container are supported. Only aligned word writes are supported.
• Array interfaces support a 128- bit read data bus and a 64-bit write data bus for each bank.
• Code flash (bank0) interface provid es configurable read buffering and page prefetch support. — Four page-read buffers (each 128 bits wide) and a prefet ch controller support speculative reading and optimized flash access.
• Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a least-recently-used replacement algorithm to maximize performance.
• Data flash (bank1) interface includes a 12 8-bit register to temporarily hold a single flash page. This logic supports single-cycle read responses (0 AHB data-phase wait states) for accesses that hit in the holding register. — No prefetch support is provided for this bank.
• Programmable response for read-while-write sequences in cluding support for stall-while-write, optional stall notification interrupt, optional flash operation abort , and optional abort notification interrupt.
• Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies.
• Support of address-based read access timing for emulation of other memory types.
• Support for reporting of single- and multi-bit error events.
• Typical operating configuration loaded in to programming model by system reset. The platform flash controller is replicated for each processor.

1.5.8 Platform Static RAM Controller (SRAMC)

The SRAMC module is the platform SRAM array controller, with integrated error detection and correction. The main features of the SRAMC provide connectivity for the following interfaces:

• XBAR Slave Port (64-bit data path)
• ECSM (ECC Error Reporting, er ror injection and configuration)
• SRAM array The following functions are implemented:
• ECC encoding (32-bit boundary for data and complete address bus)
• ECC decoding (32-bit boundary and entire address)
• Address translation from the AHB protocol on the XBAR to the SRAM array The platform SRAM controller is replicated for each processor.

1.5.9 Memory Subsystem Access Time

slave being accessed is not parked on the requesting master in the crossbar. Table 2 shows the number of additional data phase wait states required for a range of memory accesses.

1.5.10 Error Correction Status Module (ECSM)

The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).

• ECC error status and configurat ion for flash memory and SRAM
• ECC error reporting for flash memory
• ECC error reporting for SRAM
• ECC error injection for SRAM

1.5.11 Peripheral Bridge (PBRIDGE)

• Duplicated periphery
• Master access right per peripheral (per mast er: read access enable; write access enable)
• Write buffering for peripherals
• Checker applied on PBRIDGE output toward periphery
• Byte endianess swap capability

1.5.12 Interrupt Controller (INTC)

Table 2. Platform Memory Access Time Summary

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor12 For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. The INTC provides the following features:

• Duplicated periphery
• Unique 9-bit vector per interrupt source
• 16 priority levels with fixed ha rdware arbitration within priority levels for each interrupt source
• Priority elevation for shared resource The INTC is replicated for each processor.

1.5.13 System Clocks and Clock Generation

The following list summarizes the system clock and clock generation on this device:

• Lock status continuously monitored by lock detect circuitry
• Loss-of-clock (LOC) detection fo r reference and feedback clocks
• On-chip loop filter (for improved electromagnetic interfer ence performance and fewer external components required)
• Programmable output clock divider of system clock ( 1, 2, 4, 8)
• PWM module and as many as three eT imer modules running on an auxiliary clock independent from system clock (with max frequency 120 MHz)
• On-chip crystal oscillator with automatic level control
• Dedicated internal 16 MHz internal RC oscillator for rapid start-up — Supports automated frequency trimming by hardwa re during device startup and by user application
• Auxiliary clock domain for motor control periphery (PWM, eTimer, CTU, ADC, and SWG)

1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)

Each device has two FMPLLs. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio are all software configurable. The FMPLLs have the following major features:

• Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
• V oltage controlled oscillator (VCO) range: 256–512 MHz
• Frequency modulation via software control to reduce and control emission peaks — Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register — Modulation frequency: triangular modulation with 25 kHz nominal rate
• Option to switch m odulation on and off via software interface
• Reduced frequency divider (RFD) for reduced frequency operation without re-lock
• 3 modes of operation — Bypass mode — Normal FMPLL mode with crystal reference (default) — Normal FMPLL mode with external reference
• Lock monitor circuitry with lock status

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 13

• Loss-of-lock detection for reference and feedback clocks
• Self-clocked mode (SCM) operation
• On-chip loop filter
• Auxiliary FMPLL — Used for FlexRay due to precise symbol rate requirement by the protocol — Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers and jitter-free control — Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop — Allows to run motor control periphery at different (preci sely lower, equal or higher as required) frequency than the system to ensure higher resolution

1.5.15 Main Oscillator

The main oscillator provides these features:

• Input frequency range 4–40 MHz
• Crystal input mode
• External reference clock (3.3 V) input mode
• FMPLL reference

1.5.16 Internal Referenc e Clock (RC) Oscillator

The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap reference voltage. The RC oscillator is the device safe clock. The RC oscillator provides these features:

• Nominal frequency 16 MHz
• ±5% variation over voltage and temperature after process trim
• Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the FMPLL
• RC oscillator is used as the default system clock during st artup and can be used as back-up input source of FMPLL(s) in case XOSC fails

1.5.17 Clock, Reset, Power Mode, an d Test Control Modules (MC_CGM,

MC_RGM, MC_PCU, and MC_ME) These modules provide the following:

• Clock gating and clock distribution control
• Halt, stop mode control
• Flexible configurable system and auxiliary clock dividers
• Various execution modes — Reset, Idle, Test, Safe — Various RUN modes with software selectable powered modules — No stand-by mode implemented (no internal switchable power domains)

1.5.18 Periodic Interrupt Timer Module (PIT)

The PIT module implements the following features:

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor14

• 4 general purpose interrupt timers
• 32-bit counter resolution
• Can be used for software tick or DMA trigger operation

1.5.19 System Timer Module (STM)

The STM implements the following features:

• Up-counter with 4 output compare registers The STM is replicated for each processor.

1.5.20 Software Watchdog Timer (SWT)

This module implements the following features:

• Fault tolerant output
• Safe internal RC oscillator as reference clock
• Windowed watchdog
• Program flow control monitor with 16-bit pseudorandom key generation
• Allows a high level of safety (SIL3 monitor) The SWT module is replicated for each processor.

1.5.21 Fault Collection and Control Unit (FCCU)

The FCCU module has the following features:

• Redundant collection of hardware checker results
• Redundant collection of error information and la tch of faults from critical modules on the device
• Collection of self-test results
• Configurable and graded fault control — Internal reactions (no inte rnal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered) — External reaction (failure is reported to the extern al/surrounding system via configurable output pins)

1.5.22 System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The SIU provides the following features:

• Centralized pad control on a per-pin basis — Pin function selection — Configurable weak pull-up/down — Configurable slew rate control (slow/medium/fast) — Hysteresis on GPIO pins — Configurable automatic safe mode pad control
• Input filtering for external interrupts

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 15

1.5.23 Non-Maskable Interrupt (NMI)

The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.

1.5.24 Boot Assist Module (BAM)

The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode is selected via boot configuration pins. The BAM provides the following features:

• Enables booting via serial mode (CAN or LIN/UART)
• Supports programmable 64-bit password protection for serial boot mode
• Supports serial bootloading of either classic PowerPC Book E code (default) or Freescale VLE code
• Automatic switch to serial boot mode if internal flash memory is blank or invalid

1.5.25 System Status and Configuration Module (SSCM)

The SSCM on this device features the following:

• System configuration and status
• Debug port status and debug port enable
• Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half Word
• Sets up the MMU to allow user boot code to execute as e ither classic PowerPC Book E code (default) or as Freescale VLE code out of flash memory
• Triggering of device self-tests during reset phase of device boot

1.5.26 Controller Area Network Module (CAN)

The CAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. Although the CAN interface was designed to be used primarily as a vehicle networking bus, it is widely used in industrial and other transport applications due to its robust operation, time determinism, cost effectiveness, and optional redundant physical layer implementation. The CAN module provides the following features:

• Full implementation of the CAN protocol specification, version 2.0B — Standard data and remote frames — Extended data and remote frames — 0 to 8 bytes data length — Programmable bit rate as fast as 1Mbit/s
• 32 message buffers of 0 to 8 bytes data length
• Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages
• Programmable loop-back mode supporting self-test operation
• 3 programmable mask registers
• Programmable transmit-first scheme: lo west ID or lowest buffer number
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• High immunity to EMI

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor16

• Short latency time due to an arbitr ation scheme for high-priority messages
• Transmit features — Supports configuration of multiple mailboxes to form message queues of scalable depth — Arbitration scheme according to me ssage ID or message buffer number — Internal arbitration to guarantee no inner or outer priority inversion — Transmit abort procedure and notification
• Receive features — Individual programmable filters for each mailbox — 8 mailboxes configurable as a 6-entry receive FIFO — 8 programmable acceptance filters for receive FIFO
• Programmable clock source — System clock — Direct oscillator cloc k to avoid FMPLL jitter

1.5.27 FlexRay

The FlexRay module provides the following features:

• Full implementation of FlexRay Protocol Specification 2.1 Rev. A
• 64 configurable message buffers can be handled
• Dual channel or single channe l mode of operation, each as fast as 10 Mbit/s data rate
• Message buffers configurab le as transmit or receive
• Message buffer size configurable
• Message filtering for all message buffers ba sed on Frame ID, cycle count, and message ID
• Programmable acceptance filters for receive FIFO
• Message buffer header, status, and payloa d data stored in system memory (SRAM)
• Internal FlexRay memories have error detection and correction

1.5.28 Serial Communicatio n Interface Module (UART)

The UART module with DMA support on this device features the following:

• UART features: — Full-duplex operation — Standard non return-to-ze ro (NRZ) mark/space format — Data buffers with 4-byte receive, 4-byte transmit — Configurable word length (8-bit or 9-bit words) — Error detection and flagging – Parity, noise and framing errors — Interrupt driven operation with 4 interrupts sources — Separate transmitter and r eceiver CPU interrupt sources — 16-bit programmable baud-rate m odulus counter and 16-bit fractional — 2 receiver wake-up methods
• LIN features: — Autonomous LIN frame handling — Message buffer to store identif ier and up to eight data bytes — Supports message length of up to 64 bytes — Detection and flagging of LIN errors

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 17 — Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors — Classic or extended checksum calculation — Configurable Break duration of up to 36-bit times — Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional) — Diagnostic features – Loop back –S e l f T e s t – LIN bus stuck dominant detection — Interrupt driven operation with 16 interrupt sources — LIN slave mode features – Autonomous LIN header handling – Autonomous LIN response handling – Discarding of irrelevant LIN resp onses using up to 16 ID filters

1.5.29 Serial Peripheral Interface (SPI)

The SPI modules provide a synchronous serial interface for communication between the PXS20 and external devices. A SPI module provides these features:

• Full duplex, synchronous transfers
• Master or slave operation
• Programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Programmable transfer baud rate
• Programmable data frames from 4 to 16 bits
• As many as 8 chip select lines availabl e, depending on package and pin multiplexing
• 4 clock and transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for de-glitching
• FIFOs for buffering as many as 5 tran sfers on the transmit and receive side
• Queueing operation possible through use of the eDMA
• General purpose I/O functionality on pins when not used for SPI

1.5.30 Pulse Width Modulator (PWM)

The PWM module contains four PWM channels, each of which is configured to control a single half-bridge power stage. Two modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is present. Additionally, four fault input channels are provided per PWM module. This PWM is capable of controlling most motor types, including:

• AC induction motors (ACIM)
• Permanent Magnet AC motors (PMAC)
• Brushless (BLDC) and brush DC motors (BDC)
• Switched (SRM) and variable reluctance motors (VRM)
• Stepper motors A PWM module implements the following features:
• 16 bits of resolution for center, ed ge aligned, and asymmetrical PWMs

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor18

• Maximum operating frequency as high as 120 MHz — Clock source not modulated and independent from system clock (generated via secondary FMPLL)
• Fine granularity control for enhanced resolution of the PWM period
• PWM outputs can operate as complementary pairs or independent channels
• Ability to accept signed nu mbers for PWM generation
• Independent control of both edges of each PWM output
• Synchronization to external hardware or other PWM supported
• Double buffered PWM registers — Integral reload rates from 1 to 16 — Half cycle reload capability
• Multiple ADC trigger events can be generated per PWM cycle via hardware
• Fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Independent top and bottom deadtime insertion
• Each complementary pair can operate with its own PWM frequency and deadtime values
• Individual software control for each PWM output
• All outputs can be forced to a value simultaneously
• PWMX pin can optionally output a third signal from each channel
• Channels not used for PWM generation can be used for buffered output compare functions
• Channels not used for PWM generation can be used for input capture functions
• Enhanced dual edge capture functionality
• Option to supply the source for each complementar y PWM signal pair from any of the following: — External digital pin — Internal timer channel — External ADC input, taking into account values set in ADC high- and low-limit registers
• DMA support 1.5.31 eTimer Module The PXS20 provides three eTimer modules on the 257 MAPBGA device, and two eTimer modules on the 144 LQFP package. Six 16-bit general purpose up/down timer/counters per module are implemented with the following features:
• Maximum clock frequency of 120 MHz
• Individual channel capability — Input capture trigger — Output compare — Double buffer (to capture rising edge and falling edge) — Separate prescaler for each counter — Selectable clock source — 0–100% pulse measurement — Rotation direction flag (Quad decoder mode)
• Maximum count rate — Equals peripheral clock divided by 2 for external event counting — Equals peripheral clock for internal clock counting
• Cascadeable counters
• Programmable count modulo

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 19

• Quadrature decode capabilities
• Counters can share available input pins
• Count once or repeatedly
• Preloadable counters
• Pins available as GPIO when timer functionality not in use
• DMA support

1.5.32 Sine Wave Generator (SWG)

A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).

• Frequency range from 1 kHz to 50 kHz
• Sine wave amplitude from 0.47 V to 2.26 V

1.5.33 Analog-to-Digital Converter Module (ADC)

The ADC module features include: Analog part:

• 2 on-chip ADCs — 12-bit resolution SAR architecture — A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels) — One channel dedicated to each T-sensor to en able temperature reading during application — Separated reference for each ADC — Shared analog supply voltage for both ADCs — One sample and hold unit per ADC — Adjustable sampling and conversion time Digital part:
• 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in the appropriate ADC result location
• 2 modes of operation: Motor Control Mode or Regular Mode
• Regular mode features — Register based interface with the CP U: one result register per channel — ADC state machine managing three request flows: regul ar command, hardware injected command, software injected command — Selectable priority between softwa re and hardware injected commands — 4 analog watchdogs comparing ADC results ag ainst predefined levels (low, high, range) — DMA compatible interface
• Motor control mode features — Triggered mode only — 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries) — Result alignment circuitry (left justified; right justified) — 32-bit read mode allows to have channel ID on one of the 16-bit parts — DMA compatible interfaces
• Built-in self-test features triggered by software

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor20

1.5.34 Junction Temperature Sensor

The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device junction temperature. The key parameters of the junction temperature sensor include:

• Nominal temperature ra nge from –40 to 150 °C
• Software temperature alarm via analog ADC comparator possible

1.5.35 Cross Triggering Unit (CTU)

The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU load during the PWM period and with minimized CPU load for dynamic configuration. The CTU implements the following features:

• Cross triggering between ADC, PWM, eTimer, and external pins
• Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers
• Maximum operating frequency less than or equal to 120 MHz
• Trigger generation unit configurable in sequential mode or in triggered mode
• Trigger delay unit to compensate the delay of external low pass filter
• Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
• Double buffered ADC command list pointers to minimize ADC-trigger unit update
• Double buffered ADC conversion command li st with as many as 24 ADC commands
• Each trigger capable of generating consecutive commands
• ADC conversion command allows control of ADC chan nel from each ADC, single or synchronous sampling, independent result queue selection
• DMA support with safety features

1.5.36 Cyclic Redundancy Checker (CRC) Unit

The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register. The CRC unit has the following features:

• 3 sets of registers to allow 3 concur rent contexts with possibly different CRC computations, each with a selectable polynomial and seed
• Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register. The following standard CRC polynomials are implemented: — x16 + x12 + x5 + 1 [16-bit CRC-CCITT] — x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x +1 [32-bit CRC-ethernet(32)]
• Key engine to be coupled with comm unication periphery where CRC application is added to allow implementation of safe communication protocol
• Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic procedures
• CRC unit connected as peripheral bus on internal peripheral bus
• DMA support

1.5.37 Redundancy Control and Checker Unit (RCCU)

The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 21

• Duplicated module to guarantee highest poss ible diagnostic coverage (check of checker)
• Multiple times replicated IPs are used as checkers on the SoR outputs

1.5.38 Voltage Regulator / Power Management Unit (PMU)

The on-chip voltage regulator module provides the following features:

• Single external rail required
• Single high supply required: nominal 3.3 V for packaged option — Packaged option requires extern al ballast transistor due to reduced dissipation capacity at high temperature but can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation)
• All I/Os are at same voltage as external supply (3.3 V nominal)
• Duplicated Low-V oltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing feature)

1.5.39 Built-In Self-Test (BIST) Capability

This device includes the following protection against latent faults:

• Boot-time Memory Built-In Self-Test (MBIST)
• Boot-time scan-based Logic Built-In Self-Test (LBIST)
• Run-time ADC Built-In Self-Test (BIST)
• Run-time Built-In Self Test of LVDs 1.5.40 IEEE 1149.1 JTAG Controller (JTAGC) The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE standard. The JTAG controller provides the following features:
• IEEE Test Access Port (TAP) interface with 5 pins: —T D I —T M S —T C K —T D O —J C O M P
• Selectable modes of operation include JT AGC/debug or normal system operation
• 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: —B Y P A S S — IDCODE —E X T E S T —S A M P L E — SAMPLE/PRELOAD
• 3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths.
• TAP controller state machine that cont rols the operation of the data registers, instruction register and associated circuitry

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor22

1.5.41 Nexus Port Controller (NPC)

The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO 5001-2008 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO 5001-2008 Class 3+, including selected features from Class 4 standard. The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the MCUs internal memory map and access to the Power Architecture® internal registers during halt. The Nexus interface also supports a JTAG only mode using only the JTAG pins. The following features are implemented:

• Full and reduced port modes
• MCKO (message clock out) pin
• 4 or 12 MDO (message data out) pins 1
• 2 M S E O (message start/end out) pins
• E V T O (event out) pin — Auxiliary input port
• E V T I (event in) pin
• 5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) — Supports JTAG mode
• Host processor (e200) deve lopment support features — Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool to trace reads or writes, or both, to selected internal memory resources. — Ownership trace via ownership trace me ssaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An ownership trace message is transmitted when a new process/task is activated, allowing development tools to trace ownership flow. — Program trace via branch trace messagi ng (BTM). Branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. — Watchpoint messaging (WPM ) via the auxiliary port — Watchpoint trigger enable of pr ogram and/or data trace messaging — Data tracing of instructi on fetches via private opcodes 1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.

2 Package pinouts and signal descriptions

2.1 Package pinouts

Figure 3 shows the PXS20 in the 144 LQFP package. Figure 3. PXS20 144 LQFP pinout (top view) Figure 4 shows the PXS20 in the 257 MAPBGA package.

144 LQFP package

Figure 4. PXS20 257 MAPBGA pinout (top view) signals multiplexed to each pin.

1 NC = Not connected (the pin is physically not connected to anything on the device)

2 Pin K3 is NC on cut1 and RDY on cut2/3.

Table 3. 144 LQFP pin function summary

2 A[6] SIUL GPIO[6] GPIO[6]

3 D[1] SIUL GPIO[49] GPIO[49]

4 F[4] SIUL GPIO[84] GPIO[84]

5 F[5] SIUL GPIO[85] GPIO[85]

8 F[6] SIUL GPIO[86] GPIO[86]

10 A[7] SIUL GPIO[7] GPIO[7]

11 C[4] SIUL GPIO[36] GPIO[36]

12 A[8] SIUL GPIO[8] GPIO[8]

13 C[5] SIUL GPIO[37] GPIO[37]

14 A[5] SIUL GPIO[5] GPIO[5]

15 C[7] SIUL GPIO[39] GPIO[39]

16 V DD_HV_REG_0 —

17 V SS_LV_COR —

18 V DD_LV_COR —

19 F[7] SIUL GPIO[87] GPIO[87]

20 F[8] SIUL GPIO[88] GPIO[88]

21 V DD_HV_IO —

22 V SS_HV_IO —

23 F[9] SIUL GPIO[89] GPIO[89]

24 F[10] SIUL GPIO[90] GPIO[90]

25 F[11] SIUL GPIO[91] GPIO[91]

26 D[9] SIUL GPIO[57] GPIO[57]

27 V DD_HV_OSC —

28 V SS_HV_OSC —

29 XTALIN —

30 XTALOUT —

31 RESET

Table 3. 144 LQFP pin function summary (continued)

32 D[8] SIUL GPIO[56] GPIO[56]

33 D[5] SIUL GPIO[53] GPIO[53]

34 D[6] SIUL GPIO[54] GPIO[54]

35 V SS_LV_PLL0_PLL1 —

36 V DD_LV_PLL0_PLL1 —

37 D[7] SIUL GPIO[55] GPIO[55]

38 FCCU_F[0] FCCU F[0] F[0]

39 V DD_LV_COR —

40 V SS_LV_COR —

41 C[1] SIUL — GPIO[33]

42 E[4] SIUL — GPIO[68]

43 B[7] SIUL — GPIO[23]

44 E[5] SIUL — GPIO[69]

45 C[2] SIUL — GPIO[34]

46 E[6] SIUL — GPIO[70]

47 B[8] SIUL — GPIO[24]

48 E[7] SIUL — GPIO[71]

49 E[2] SIUL — GPIO[66]

50 V DD_HV_ADR0 —

51 V SS_HV_ADR0 —

52 B[9] SIUL — GPIO[25]

53 B[10] SIUL — GPIO[26]

54 B[11] SIUL — GPIO[27]

55 B[12] SIUL — GPIO[28]

56 V DD_HV_ADR1 —

57 V SS_HV_ADR1 —

58 V DD_HV_ADV —

59 V SS_HV_ADV —

60 B[13] SIUL — GPIO[29]

61 E[9] SIUL — GPIO[73]

62 B[15] SIUL — GPIO[31]

63 E[10] SIUL — GPIO[74]

64 B[14] SIUL — GPIO[30]

65 E[11] SIUL — GPIO[75]

66 C[0] SIUL — GPIO[32]

67 E[12] SIUL — GPIO[76]

68 E[0] SIUL — GPIO[64]

69 BCTRL —

70 V DD_LV_COR —

71 V SS_LV_COR —

72 V DD_HV_PMU —

73 A[0] SIUL GPIO[0] GPIO[0]

74 A[1] SIUL GPIO[1] GPIO[1]

75 G[11] SIUL GPIO[107] GPIO[107]

76 D[10] SIUL GPIO[58] GPIO[58]

77 G[10] SIUL GPIO[106] GPIO[106]

78 D[11] SIUL GPIO[59] GPIO[59]

79 G[9] SIUL GPIO[105] GPIO[105]

80 C[11] SIUL GPIO[43] GPIO[43]

81 G[8] SIUL GPIO[104] GPIO[104]

82 C[12] SIUL GPIO[44] GPIO[44]

83 G[7] SIUL GPIO[103] GPIO[103]

84 A[2] SIUL GPIO[2] GPIO[2]

85 G[5] SIUL GPIO[101] GPIO[101]

86 B[5] SIUL GPIO[21] GPIO[21]

87 TMS —

88 TCK —

89 B[4] SIUL GPIO[20] GPIO[20]

90 V SS_HV_IO —

91 V DD_HV_IO —

92 A[3] SIUL GPIO[3] GPIO[3]

93 V DD_LV_COR —

94 V SS_LV_COR —

95 V DD_HV_REG_1 —

96 V SS_HV_FLA —

97 V DD_HV_FLA —

98 G[6] SIUL GPIO[102] GPIO[102]

99 D[12] SIUL GPIO[60] GPIO[60]

100 G[4] SIUL GPIO[100] GPIO[100]

101 C[13] SIUL GPIO[45] GPIO[45]

102 G[2] SIUL GPIO[98] GPIO[98]

103 C[14] SIUL GPIO[46] GPIO[46]

104 G[3] SIUL GPIO[99] GPIO[99]

105 D[14] SIUL GPIO[62] GPIO[62]

106 F[12] SIUL GPIO[92] GPIO[92]

107 V PP_TEST

108 A[4] SIUL GPIO[4] GPIO[4]

109 B[0] SIUL GPIO[16] GPIO[16]

110 B[1] SIUL GPIO[17] GPIO[17]

111 C[10] SIUL GPIO[42] GPIO[42]

112 F[13] SIUL GPIO[93] GPIO[93]

113 F[15] SIUL GPIO[95] GPIO[95]

114 B[2] SIUL GPIO[18] GPIO[18]

115 F[14] SIUL GPIO[94] GPIO[94]

116 B[3] SIUL GPIO[19] GPIO[19]

117 E[13] SIUL GPIO[77] GPIO[77]

118 A[10] SIUL GPIO[10] GPIO[10]

119 E[14] SIUL GPIO[78] GPIO[78]

120 A[11] SIUL GPIO[11] GPIO[11]

121 E[15] SIUL GPIO[79] GPIO[79]

122 A[12] SIUL GPIO[12] GPIO[12]

123 JCOMP — — JCOMP

124 C[15] SIUL GPIO[47] GPIO[47]

125 D[0] SIUL GPIO[48] GPIO[48]

127 V SS_HV_IO —

128 D[3] SIUL GPIO[51] GPIO[51]

129 D[4] SIUL GPIO[52] GPIO[52]

130 V DD_HV_REG_2 —

131 V DD_LV_COR —

132 V SS_LV_COR —

133 F[0] SIUL GPIO[80] GPIO[80]

134 A[9] SIUL GPIO[9] GPIO[9]

135 V DD_LV_COR —

136 A[13] SIUL GPIO[13] GPIO[13]

137 V SS_LV_COR —

138 B[6] SIUL GPIO[22] GPIO[22]

139 F[3] SIUL GPIO[83] GPIO[83]

140 D[2] SIUL GPIO[50] GPIO[50]

141 FCCU_F[1] FCCU F[1] F[1]

142 C[6] SIUL GPIO[38] GPIO[38]

143 A[14] SIUL GPIO[14] GPIO[14]

144 A[15] SIUL GPIO[15] GPIO[15]

1 VPP_TEST should always be tied to ground (VSS) for normal operations. Table 4. 257 MAPBGA pin function summary

Table 4. 257 MAPBGA pin function summary (continued)

1 VPP_TEST should always be tied to ground (VSS) for normal operations.

2.2 Supply pins

Table 5. Supply pins between these pins and the nearest VDD_LV_COR pin.

17 VSS_HV 2

between these pins and the nearest VSS_LV_COR pin.

18 VDD_LV 1

39 VDD_LV 1

40 VSS_LV 2

70 VDD_LV 1

71 VSS_LV 2

93 VDD_LV 1

94 VSS_LV 2

131 VDD_LV 1

132 VSS_LV 2

135 VDD_LV 1

137 VSS_LV 2

1 VDD_LV balls are tied together on the 257 MAPBGA substrate. 2 VSS_LV balls are tied together on the 257 MAPBGA substrate. 3 VDD_HV balls are tied together on the 257 MAPBGA substrate. 4 VSS_HV balls are tied together on the 257 MAPBGA substrate. Table 5. Supply pins (continued)

2.3 System pins

2.4 Pin muxing

Table 7 defines the pin list and muxing for this device. assigned to each pin after reset is indicated by ALT0. voltage may cause unpredictable device behavior or damage. Table 6. System pins 1 This pad is configured for Fast (F) pad speed. 2 This pad contains a weak pull-up. 3 This pad contains a weak pull-down. RESET Bidirectional reset with Schmitt-Trigger characteristics and noise filter. This pin has medium drive strength.

107 D15

Table 7. Pin muxing

Table 7. Pin muxing (continued)

2 The default function of this pin out of reset is ALT1 (TDO).

3 Analog

Electrical characteristics

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 73

3 Electrical characteristics

3.1 Introduction

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for this device. This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “CC”, “P”,

• “SR” identifies system requirements—conditions that mu st be provided to ensure normal device operation. An example is the input voltage of a voltage regulator.
• “CC” identifies controller characteris tics—indicating the characteristics and timing of the signals that the chip provides.
• “P”, “C”, “T”, or “D” apply only to controller characteristics—sp ecifications that define normal device operation. They specify how each characteristic is guaranteed. — P: parameter is guaranteed by produc tion testing of each individual device. — C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process variations. — T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category. — D: parameters are derived mainly from simulations.

3.2 Absolute maximum ratings

Table 8. Absolute maximum ratings1

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.3 Recommended operating conditions

VSS_HV_ADV SR 3.3 V ADC supply ground — –0.1 0.1 V TVDD SR Slope characteristics on all V DD during power up — 0.5 3.0 × 10 6 (3.0 V/sec) V/µs VIN SR Voltage on any pin with respect to ground (VSS_HV_IOx) — –0.3 6.0 V Relative to VDD –0.3 V DD +0 . 36 IINJPAD SR Injected input current on any pin during overload condition — –10 10 mA during overload condition — –50 50 mA TSTG SR Storage temperature — –55 150 °C 1 Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining. 4 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by the same voltage source. 6 Only when VDD < 5.2 V. Table 9. Recommended operating conditions (3.3 V)

3 SR Internal supply voltage — — — V

Table 8. Absolute maximum ratings1 (continued)

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 75

3.4 Thermal characteristics

VSS_LV_REGCOR SR Internal reference voltage — 0 0 V VDD_LV_CORx SR Internal supply voltage — — — V VSS_LV_CORx SR Internal reference voltage — 0 0 V VDD_LV_PLL SR Internal supply voltage — — — V VSS_LV_PLL SR Internal reference voltage — 0 0 V TA SR Ambient temperature under bias fCPU 120 MHz –40 125 °C TJ SR Junction temperature under bias — –40 150 °C 1 Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. 2 VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage source. 3 Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an on-chip voltage regulator. 4 For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used. Table 10. Thermal characteristics for 144 LQFP package1 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. meets JEDEC specification for this package. specification for the specified package. temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. parameter is written as Psi-JT. Table 9. Recommended operating conditions (3.3 V) (continued)

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.4.1 General notes for specification s at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from Equation 1: TJ =T A +( RJA ×P D) Eqn. 1 where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA =R JC + RCA Eqn. 2 where: RJA = junction to ambient thermal resistance (°C/W) RJC = junction to case thermal resistance (°C/W) RCA = case to ambient thermal resistance (°C/W) Table 11. Thermal characteristics for 257 MAPBGA package1 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. meets JEDEC specification for this package. specification for the specified package. temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. parameter is written as Psi-JT.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 77 RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: TJ =T T +( JT ×P D) Eqn. 3 where: TT = thermocouple temperature on top of the package (°C) JT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

3.4.1.1 References

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134 USA (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. 2. G . Kromann, S. Shidore, and S. Addison, “Thermal Mo deling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. 3. B. Joiner and V . Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

3.5 Electromagnetic Interference (EMI) characteristics (cut1)

The characteristics in Table 13 were measured using:

• Device configuration, tet conditions, and EM testing per standard IEC61967-2
• Supply voltage of 3.3 V DC
• Ambient temperature of 25 C The configuration information referenced in Table 13 is explained in Table 12.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.6 Electrostatic discharge (ESD) characteristics

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Table 12. EMI configuration summary Table 13. EMI emission testing specifications

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 79

3.7 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is appl ied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard.

3.8 Voltage regulator electrical characteristics

The voltage regulator is composed of the following blocks:

• High power regulator HPREG1 (internal ballast to support core current)
• High power regulator HPREG2 (external NPN to support core current)
• Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (V DDIO)
• Low voltage detector (LVD_MAIN_2) for 3.3 V supply (V DDREG)
• Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (V DDFLASH)
• Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPV DD)
• Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
• High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPV DD)
• High voltage detector (HVD_DIG_BKUP ) for the self-test of HVD_DIG_MAIN.
• P o w e r o n R e s e t ( P O R ) HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on board to supply core current. The PXS20 always powers up using HPREG1 if an external NPN transistor is present. Then the PXS20 makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the controller part of HPREG1 is switched off. The following bipolar transistors are supported:
• BCP68 from ON Semiconductor

Table 14. ESD ratings1, 2 3 Data based on characterization results, not tested in production. Table 15. Latch-up results

1 LU SR Static latch-up class T A = 125 °C conforming to JESD 78 II level A

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

• BCX68 from Infineon

Table 16. Voltage regulator electrical specifications

1.2 V pins

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 81 Figure 5. BCP68 board schematic example Table 16. Voltage regulator electrical specifications (continued)

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.9 DC electrical characteristics

Table 17 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx <3 . 6V ) . Table 17. DC electrical characteristics1 1 These specifications are design targets and subject to change per device characterization. 2 “SR” parameter values must not exceed the absolute maximum ratings shown in Table 8.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 83

3.10 Supply current characteristics (cut2)

Current consumption data is given in Table 18. These specifications are design targets and are subject to change per device characterization. Table 18. Current consumption characteristics

1.2 V supplies

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.11 Temperature sensor electrical characteristics

3.12 Main oscillator electrical characteristics

The device provides an oscillator/resonator driver. Figure 6 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. IDD_HV_ADC 2,3 T Operating current T J = 150 C

120 MHz

VDD_HV_ADC =3 . 6V —— 1 0 m A IDD_HV_AREF

3 T Operating current T J = 150 C

V DD_HV_REF =3 . 6V —— 3 m A TJ = 150 C VDD_HV_REF =5 . 5V —— 5 IDD_HV_OSC T Operating current T J = 150 C

3.3 V supplies

— — 900 A IDD_HV_FLASH

4 T Operating current T J = 150 C

—— 4 m A 1 Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1, PIT, CRC, PLL0/1, I/O supply current excluded 2 Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications. 3 This value is the total current for both ADCs. 4 VFLASH is only available in the calibration package. Table 19. Temperature sensor electrical characteristics Table 18. Current consumption characteristics (continued)

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.13 FMPLL electrical characteristics

Table 20. Main oscillator electrical characteristics 1 VDD = 3.3 V ±10%, TJ = –40 to +150 °C, unless otherwise specified.

2 The recommended configuration for maximizing the oscillator margin are:

Table 21. FMPLL electrical characteristics

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 87 tlpll D FMPLL lock time 6, 7 — — — 200 s tdc D Duty cycle of reference —4 0 — 6 0 % CJITTER T CLKOUT period jitter 8,9,10,11 Long-term jitter (avg. over 2 ms interval), fSYS maximum –6 — 6 ns tPKJIT T Single period jitter (peak to peak) PHI @ 120 MHz, Input clock @ 4 MHz — — 175 ps PHI @ 100 MHz, Input clock @ 4 MHz — — 185 ps PHI @ 80 MHz, Input clock @ 4 MHz — — 200 ps tLTJIT T Long term jitter PHI @ 16 MHz, Input clock @ 4 MHz ——± 6 n s fLCK D Frequency LOCK range — –6 — 6 % fsys fUL D Frequency un-LOCK range — –18 — 18 % fsys fCS fDS D Modulation Depth Center spread ±0.25 — ±2.0 12 % fsysDown Spread –0.5 — -8.0 fMOD D Modulation frequency 13 — — — 100 kHz 1 Considering operation with FMPLL not bypassed.

2 With FM; the value does not include a possible +2% modulation

3 “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked mode. 4 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the fLOR window. 5 fVCO is the frequency at the output of the VCO; its range is 256–512 MHz. fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz. fSYS =f VCOODF 6 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this FMPLL, load capacitors should not exceed these limits. 7 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 8 This value is determined by the crystal manufacturer and board design. 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 10 Proper PC board layout procedures must be followed to achieve specifications. 11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 12 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz). 13 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz. Table 21. FMPLL electrical characteristics (continued)

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 3.14 16 MHz RC oscillator electrical characteristics

3.15 ADC electrical characteristics

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter. Figure 8. ADC characteristics and error definitions

3.15.1 Input Impedance and ADC Accuracy

during the sampling phase, when the analog signal source is a high-impedance source. Table 22. RC oscillator electrical characteristics

1 LSB (ideal)

1 LSB ideal =(VrefH-VrefL)/ 4096 =

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 89 be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ =1 / ( fC CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS +R F +R L +R SW +R AD, the external circuit must be designed to respect the Equation 4: Eqn. 4 Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 9. Input Equivalent Circuit installed when the sampling phase is started (A/D switch close).

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Figure 10. Transient Behavior during Sampling Phase

• A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is Eqn. 5 Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Eqn. 6 The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 7: Eqn. 7
• A second charge transfer involves also C F (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Eqn. 8 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 9 VA VA1 VA2 tTS VCS Voltage Transient on C S V <0.5 LSB 1 2 1 < (RSW + RAD) CS << TS 2 = RL (CS + CP1 + CP2) 1 RSW RAD+= CP CS VA1 CS CP1 CP2++ VA CP1 CP2+=

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 91 Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 10 The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Figure 11. Spectral representation of input signal

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Table 23. ADC conversion characteristics 1 VDD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF. 2 AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

6 D ADC input pin capacitance 1 — — — 5 (7) pF

6 D Internal resistance of analog source — — — 825 

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 93

3.16 Flash memory electrical characteristics

4 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. 5 This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. 6 See Figure 9. 7 For the 144-pin package. 8 No missing codes. Table 24. Flash memory program and erase electrical specifications characterized, but not tested. operation at TJ =2 5 °C. These values are characterized, but not tested. program/erase cycles, nominal supply values and operation at TJ =2 5 °C. These values are verified at production test. values are characterized, but not tested. 5 See Notes for individual specifications, as shown in column headings. 6 Actual hardware programming times. These do not include software overhead. Table 25. Flash memory timing

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.17 SWG electrical characteristics

3.18 AC specifications

3.18.1 Pad AC specifications

Table 26. Flash memory module life

1 P/E C Number of program/erase cycles per block for 16 KB, 48 KB,

Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.

2 P/E C Number of program/erase cycles per block for 128 KB and

256 KB blocks over the operating temperature range1

3 Retention C Minimum data retention at 85 °C average ambient temperature3

3 Ambient temperature averaged over duration of application, not to exceed product operating temperature range. Table 27. SWG electrical characteristics Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 )1

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 95 Figure 12. Pad output delay

3.19 Reset sequence

conditions and the end indication for the reset sequences.

3 Fast T 1 — 6 — — 4 — — 72 3 — 40 25

5 Pull Up/Down

1 Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition. 2 Slope at rising/falling edge. 3 Data based on characterization results, not tested in production. Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 )1 (continued)

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

3.19.1 Reset sequence duration

Table 29 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in Section 3.19.2, Reset sequence description.

3.19.2 Reset sequence description

The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the figures indicate the starting point and the end point for which the duration is specified in Table 29. The start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3, Reset sequence trigger mapping. With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and the internal reset sequence is finished. The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the signal pin RESET. NOTE RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an external reset generator or by the chip internal reset circuitry. A high level on this pin can only be generated by an external pull up resistor which is strong enough to overdrive the weak internal pull down resistor. The rising edge on RESET in the following figures indicates the time when the device stops driving it low. The reset sequence durations given in table Table 29 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET asserted low beyond the last PHASE3. Table 29. RESET sequences by an external reset generator.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Figure 16. Functional Reset Sequence Long Figure 17. Functional Reset Sequence Short drive RESET low for the duration of the internal reset sequence1.

3.19.3 Reset sequence trigger mapping

conditions as well as the reset sequence end indications that are the basis for the timing data provided in Table 29. 1.See RGM_FBRE register for more details.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 99 Table 30. Reset sequence trigger — reset sequence 1 Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM. RESET is released externally. 3 The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.

6 If RESET is configured for short reset

the functional reset source which triggered the reset sequence.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor100

3.19.4 Reset sequence — start condition

The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration.

3.19.4.1 Destructive reset

Figure 18 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled. Figure 18. Reset sequence start for Destructive Resets

3.19.4.2 External reset via RESET

Table 31. Voltage Thresholds

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 101 Figure 19. Reset sequence start via RESET assertion

3.19.5 External watchdog window

the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigger window. Figure 20. Reset sequence - External watchdog trigger window position

3.20 AC timing characteristics

• TJ = –40 to 150 C
• Supply voltages as specified in Table 9 TReset, max starts here TReset, min starts here RESET_B 0.65 * VDD_HV_IO t V 0.35 * VDD_HV_IO RESET External Watchdog Window Closed Earliest Application Start Latest Application Start Internal Reset Sequence Start condition (signal or voltage rail) External Watchdog Window Open TReset, min TReset, max TWDStart, min TWDStart, max External Watchdog Window Closed External Watchdog Window Open Basic Application Init Basic Application Init Application time required to prepare watchdog trigger Watchdog needs to be triggered within this window Watchdog trigger Application Running Application Running

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor102

• Input conditions: All Inputs: tr, tf = 1 ns
• Output Loading: All Outputs: 50 pF

3.20.1 RESET pin characteristics

The PXS20 implements a dedicated bidirectional RESET pin. Figure 21. Start-up reset requirements Figure 22. Noise filtering on reset signal

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 103

3.20.2 WKUP/NMI timing

3.20.3 IEEE 1149.1 JTAG interface timing Table 32. RESET electrical characteristics 2 CL includes device and package capacitance (CPKG <5p F ) . Table 33. WKUP/NMI glitch filter Table 34. JTAG pin AC electrical characteristics

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 105 Figure 25. JTAG boundary scan timing

3.20.4 Nexus timing

Table 35. Nexus debug port timing1 measured from 50% of MCKO and 50% of the respective signal. 2 For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 107 Figure 28. Nexus TDI, TMS, TDO timing

3.20.5 External interrupt timing (IRQ pin)

Table 36. External interrupt timing 1 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor108 Figure 29. External interrupt timing

3.20.6 DSPI timing

Table 37. DSPI timing

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 109 Figure 30. DSPI classic SPI timing — master, CPHA = 0 on SIN, but no valid data is transmitted on SOUT. Table 37. DSPI timing (continued) Note: The numbers shown are referenced in Table 37.

Figure 37. DSPI modified transfer format timing — slave, CPHA = 1 Figure 38. DSPI PCS strobe (PCSS) timing

4 Package characteristics

4.1 Package mechanical data

Note: The numbers shown are referenced in Table 37. Note: The numbers shown are referenced in Table 37.

Figure 39. 144 LQFP package mechanical drawing (1 of 2)

Figure 40. 144 LQFP package mechanical drawing (2 of 2)

Figure 41. 257 MAPBGA package mechanical drawing (1 of 2)

Figure 42. 257 MAPBGA package mechanical drawing (2 of 2)

PXS20 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice

Ordering information

Freescale Semiconductor118

5 Ordering information

Figure 43. PXS20 orderable part number description

6 Document revision history

Table 39 summarizes revisions to this document. Table 38. PXS20 orderable part number summary Table 39. Revision history 1 30 Sep 2011 Initial release. Note: Not all options are available on all devices. See Table 38 for more information.

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