MPXN1005VLQ120R

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Data Sheet: Technical Data Document Number: PXD10 Rev. 1, 09/2011 PXD10

416 TEPBGA

176 LQFP

208 LQFP

© Freescale Semiconductor, Inc., 2011. All rights reserved. The PXD10 family represents a new generation of 32-bit microcontrollers based on the Power Architecture®. These devices provide a cost-effective, single chip display solution for the industrial market. An integrated TFT driver with digital video input ability from an external video source, significant on-chip memory, and low power design methodologies provide flexibility and reliability in meeting display demands in rugged environments. The advanced processor core offers high performance processing optimized for low power consumption, operating at speeds as high as 64 MHz. The family itself is fully scalable from 512 KB to 1 MB internal flash memory. The memory capacity can be further expanded via the on-chip QuadSPI serial flash controller module. The PXD10 family platform has a single level of memory hierarchy supporting on-chip SRAM and flash memories. The 1 MB flash version features

160 KB of on-chip graphics SRAM to buffer cost

effective color TFT displays driven via the on-chip Display Control Unit (DCU). See Table 1 for specific memory size and feature sets of the product family members. The PXD10 family benefits from the extensive development infrastructure for Power Architecture devices, which is already well established. This includes full support from available software drivers, operating systems, and configuration code to assist with users’ implementations. See Section 3, Developer support, for more information. PXD10 Microcontroller Data Sheet 3.6 Electromagnetic compatibility (EMC) characteristics . . 65

3.10 RESET

3.11 Fast external crystal oscillator (4–16 MHz) electrical characteristics87

3.12 Slow external crystal oscillator (32 KHz) electrical characteristics89

3.14 Fast internal RC oscillator (16 MHz) electrical characteristics 92

3.15 Slow internal RC oscillator (128 kHz) electrical characteristics92

1 Overview

1.1 Document overview

characteristics. For functional characteristics, see the PXD10 Microcontroller Reference Manual.

1.2 Description

directly using an on-chip color TFT display controller. with 1 MB of flash memory (PXD1010) features 160 KB of on-chip graphics SRAM. See Table 1 for specific memory and feature sets of the product family members.

1.3 Device comparison

Table 1. PXD10 family feature set

Table 1. PXD10 family feature set (continued)

1.4 PXD10 series blocks

1.4.1 Block diagram

Figure 1 shows a high-level block diagram of the PXD10 series. Figure 1. PXD10 series block diagram

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 5

1.5 PXD10 features

1.5.1 Summary

• Single issue, 32-bit Power Architecture t echnology compliant CPU core complex (e200z0h) — Compatible with Power Architecture instruction set — Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional Book E compliant code
• On-chip ECC flash memory with flash controller — As much as 1 MB primary flas h—two 512 KB modules with pref etch buffer and 128-bit data access port — 64 KB data flash—separate 4 16 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port
• As much as 48 KB on-chip ECC SRAM with SRAM controller
• As much as 160 KB on-chip non-ECC gr aphics SRAM with SRAM controller
• Memory Protection Unit (MPU) with as many as 12 region descriptors and 32-byte region granularity to provide basic memory access permission
• Interrupt Controller (INTC) wi th as many as 127 peripheral interrupt sources and eight software interrupts
• Two Frequency-Modulated Ph ase-Locked Loops (FMPLLs) — Primary FMPLL provides a 64 MHz system clock — Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation
• Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus masters (AMBA 2.0 v6 AHB)
• 16-channel Enhanced Direct Memory Access cont roller (eDMA) with multiple transfer request sources using a DMA channel multiplexer
• Boot Assist Module (BAM) supports internal fl ash programming via a serial link (FlexCAN or LINFlex)
• Display Control Unit to drive TFT LCD displays — Includes processing of as many as four planes that can be blended together — Offers a direct unbuffered hardwa re bit-blitter of as many as 16 software-configurable dynamic layers in order to drastically minimize graphic memory requirements and provide fast animations — Programmable display resoluti ons are available up to WVGA
• Parallel Data Interface (P DI) for digital video input
• LCD segment driver module with two software programmable configurations: — As many as 40 frontplane driver s and four backplane drivers

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor6 — As many as 38 frontplane drivers and six backplane drivers

• Stepper Motor Controller (SMC) module with high-current drivers for as many as six stepper motors driven in full dual H-Bridge configuration including full diagnostics for short circuit detection
• Stepper motor return-to-zero and stall detection module
• Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound
• 24 eMIOS channels providing as many as 16 PWM and 24 input capture / output compare channels
• 10-bit Analog-to-Digital Converter (ADC) — Maximum conversion time of 1 µs — As many as 16 internal channels, expa ndable to 23 via external multiplexing
• As many as two Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with external devices (extendable to include up to 8 multiplexed external channels)
• QuadSPI serial flash memory controller suppor ting single, dual and quad modes of operation to interface to external serial flash memory. QuadSPI can be configured to function as another DSPI module.
• Two Local Interconnect Network Flexible (LIN Flex) controller modules capable of autonomous message handling (master), autonomous header handling (slave mode), and UART support. Compliant with LIN protocol rev 2.1
• Two full CAN 2.0B controllers with 64 configurable buffers each; bit rate programmable as fast as

1 Mbit/s

• As many as four inter- integrated circuit (I2C) internal bus controllers with master/slave bus interface
• As many as 133 configurable general purpose pins supporting input and output operations
• Real Time Counter (RTC) w ith multiple clock sources: — 128 kHz slow internal RC os cillator or 16 MHz fast internal RC oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds — 32 KHz slow external crysta l oscillator, supporting wakeup with 1 s resolution and maximum timeout of one hour — 4–16 MHz fast external crystal oscillator
• System timers: — Four-channel 32-bit System Timer Module (STM)—included in processor platform — Four-channel 32-bit Periodic Interrupt Timer (PIT) module — Software Watchdog Timer (SWT)
• System Integration Unit (SIU) module to manage re sets, external interrupts, GPIO and pad control
• System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot mode, or debug status and provides an entry point for the censorship password mechanism

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 7

• Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface, enabling access to all clock sources
• Clock Monitor Unit (CMU) to monitor the integrit y of the main crystal oscillator and the PLL and act as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock
• Mode Entry Module (MC_ME) to control the de vice power mode, i.e., RUN, HALT, STOP, or STANDBY , control mode transition sequences, and manage the power control, voltage regulator, clock generation and clock management modules
• Reset Generation Module (MC_RGM) to manage rese t assertion and release to the device at initial power-up
• Nexus development interf ace (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
• Device/board boundary-sca n testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
• On-chip voltage regulator contro ller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires external ballast transistor)
• The PXD10 microcontrollers are of fered in the following packages:1 — 144 LQFP, 0.5 mm pitch, 20 mm  20 mm outline — 176 LQFP, 0.5 mm pitch, 24 mm  24 mm outline

1.6 Details

1.6.1 Low-power operation

PXD10 devices are designed for optimized low-power operation and dynamic power management of the core processor and peripherals. Power management features include software-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. There are two static low-power modes, STANDBY and STOP, and two dynamic power modes—RUN and HALT. Both low power modes use clock gating to halt the clock for all or part of the device. The STANDBY mode also uses power gating to automatically turn off the power supply to parts of the device to minimize leakage. STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode. The contents of the cores, on-chip peripheral registers and potentially some of the volatile memory are lost. STANDBY mode is configurable to make certain features available with the disadvantage that these consume additional current:

• It is possible to retain the contents of the full RAM or only 8 KB.
• It is possible to enable the internal 16 MHz or 128 kHz RC oscillator, the external 4–16 MHz oscillator, or the external 32 KHz oscillator.
• It is possible to keep the LCD module active. 1. See the device comparison table or orderable parts summary for package offerings for each device in the family.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor8 The device can be awakened from STANDBY mode via from any of as many as 19 I/O pins, a reset or from a periodic wake-up using a low power oscillator. STOP mode maintains power to the entire device allowing the retention of all on-chip registers and memory, and providing a faster recovery low power mode than the lowest STANDBY mode. There is no need to reconfigure the device before executing code. The clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or PLL at the expense of a slower start-up time. STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by the internal periodic wake-up, if enabled. RUN modes are the main operating mode where the entire device can be powered and clocked and from which most processing activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The ability to configure and select different RUN modes enables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. The necessary peripherals, clock sources, clock speed and system clock prescalers can be independently configured for each of the four RUN modes of the device. HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing activity. In this mode the core system clocks are stopped but user-selected peripheral tasks can continue to run. It can be configured to provide more efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency. The system returns to RUN mode as soon as an event or interrupt is pending.

Table 1 summarizes the operating modes of PXD10 devices. Table 1. Operating mode summary1

1 Table Key:

at wake up. Other delays will be necessary to consider including, but not limited to the external supply start-up time. IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG.

16 MHz IRC

32 KHz X OSC

3 The LCD can optionally be kept running while the device is in STANDBY mode. 4 All of the RAM contents is retained, but not accessible in STANDBY mode. 5 8 KB of the RAM contents is retained, but not accessible in STANDBY mode.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor10 Additional notes on low power operation:

• Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low power modes
• The 16 MHz internal RC oscillat or supports low speed code execution and clocking of peripherals when it is selected as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external oscillator delay
• PXD10 devices include an intern al voltage regulator that includes the following features: — Regulates input to genera te all internal supplies — Manages power gating — Low power regulators support operation when in STOP and STANDBY modes to minimize power consumption — Startup on-chip regulators in <50 µs for rapid exit of STOP and STANDBY modes — Low voltage detection on main supply and 1.2 V regulated supplies 1.6.2 e200z0h core processor The e200z0h processor is similar to other processors in the e200zx series but supports only the VLE instruction set and does not include the signal processing extension for DSP applications or a floating point unit. The e200z0h has all the features of the e200z0 plus:
• Branch acceleration using Br anch Target Buffer (BTB)
• Supports independent instruction and data accesse s to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data BIUs The e200z0h processor uses a four stage in-order pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), an 8 × 32 Hardware Multiplier array, result feed-forward hardware, and a hardware divider. Most arithmetic and logical operations are executed in a single cycle with the exception of the divide and multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Branch target prefetching from the BTB is performed to accelerate certain taken branches. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding four instructions. Conditional branches not taken execute in a single clock. Branches with successful target prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an execution time of two clocks.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 11 Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported. Hardware vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This allows the classic PowerPC instruction set to be represented by a modified instruction set made up from a mixture of 16-bit and 32-bit instructions. This results in a significantly smaller code size footprint without affecting performance noticeably. The CPU core is enhanced by an additional interrupt source—Non Mask able Interrupt. This interrupt source is routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing the Interrupt Controller completely. Once the edge detection logic is programmed, it can not be disabled, except by reset. The Non Maskable Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of the respective interrupt service routine. The Non maskable interrupt is not guaranteed to be recoverable. The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt. Additional features include:

• Load/store unit — 1-cycle load latency — Misaligned access support — No load-to-use pipeline bubbles
• Thirty-two 32-bit genera l purpose registers (GPRs)
• Separate instruction bus and load/store bus Harvard architecture
• Reservation instructions for implem enting read-modify-write constructs
• Multi-cycle divide (divw) and load multipl e (lmw) store multiple (smw) multiple class instructions, can be interrupted to prevent increases in interrupt latency
• Extensive system developmen t support through Nexus debug port

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor12

1.6.3 Display Control Unit (DCU)

The DCU is a display controller designed to drive TFT LCD displays capable of driving up to WQVGA resolution screens with 16 layers and 4 planes with real time alpha-blending. The DCU generates all the necessary signals required to drive the display: up to 24-bit RGB data bus, Pixel Clock, Data Enable, Horizontal-Sync and Vertical-Sync. Internal memory resource of the PXD10 allows to easily handle complex graphics contents (pictures, icons, languages, fonts) on a color TFT panel in up to Wide Quarter Video Graphics Array (WQVGA) sizes. All the data fetches from internal and/or external memory are performed by the internal four-channel DMA of the DCU providing a high speed/low latency access to the system backbone. Control Descriptors (CDs) associated with each layer enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. A layer may be constructed from graphic content of various resolutions including 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, 24bpp and 24bpp+alpha. The ability of the DCU to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of internal memory resources of the PXD10. A special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizing graphic memory usage. A hardware cursor can be managed independently of the layers at blending level increasing the efficient use of the internal DCU resources. To secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the TFT pads. The DCU features the following:

• Display color depth: up to 24 bpp
• Generation of all RGB and control signals for TFT
• Four-plane blending
• Maximum number of Input Layers: 16 (fixed priority)
• Dynamic look-up table (c olor and gamma look-up)
• blending range: as many as 256 levels
• Transparency Mode
• Gamma Correction
• Tiled mode on all the layers
• Hardware cursor
• Critical display content integrity m onitoring for functional safety support
• Internal Direct Memory Access (D MA) module to transfer data from internal and/or external memory.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 13

1.6.4 Parallel Data Interface (PDI)

The PDI is a digital interface used to receive external digital video or graphic content into the DCU. The PDI input is directly injected into the DCU background plane FIFO. When the PDI is activated, all the DCU synchronization is extracted from the external video stream to guarantee the synchronization of the two video sources. The PDI can be used to:

• Connect a video camera output directly to the PDI
• Connect a secondary display driver as slave with a minimum of extra cost
• Connect a device gathering various Video sources
• Provide flexibility to allow the DCU to be used in slave mode (external synchronization) The PDI features the following:
• Supported color modes: — 8-bit mono — 8-bit color multiplexed — RGB565 — 16-bit/18-bit RAW color
• Supported synchronization modes: — Embedded ITU-R BT.656-4 (RGB565 mode 2) — HSYNC, VSYNC — Data Enable
• Direct interface with DCU background plane FIFO
• Synchronization generation for the DCU

1.6.5 Liquid Crystal Display (LCD) driver

The LCD driver module has two configurations allowing a maximum of 160 or 228 LCD segments:

• As many as 40 frontplane driver s and four backplane drivers
• As many as 38 frontplane drivers and six backplane drivers Each segment is controlled and can be masked by a corresponding bit in the LCD RAM. Four to six multiplex modes (1/1, 1/2, 1/3, 1/4, 1/5, 1/6 duty), and three bias (1/1, 1/2, 1/3) methods are available. All frontplane and backplane pins can be multiplexed with other port functions. The LCD driver module features the following:
• Programmable frame clock generato r from different clock sources: — System clock — Internal RC oscillator
• Programmable bias vol tage level selector
• On-chip generation of all output voltage levels

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor14 — LCD voltage reference ta ken from main 5V supply

• LCD RAM — Contains the data to be displayed on the LCD — Data can be read from or writte n to the display RAM at any time
• End of Frame interrupt — Optimizes the refresh of the data without visual artefact — Provides selectable number of frames between each interrupt
• Contrast adjustment using program mable internal voltage reference
• Remapping capability of four or six backplanes with frontplanes — Increase pin selection flexibility
• In low power modes, the LCD operation can be suspended under software control. The LCD can also operate in low power modes, clocked by the internal 128 kHz IRC or external 32 KHz crystal oscillator
• Selectable output current boost during transitions

1.6.6 Stepper Motor Controller (SMC)

The SMC module is a PWM motor controller suitable to drive loads requiring a PWM signal. The motor controller has twelve PWM channels associated with two pins each (24 pins in total). The SMC module includes the following features:

• 10/11-bit PWM counter
• 11-bit resolution with select able PWM dithering function
• Left, right, or center aligned PWM
• Output slew rate control
• Output Short Circuit Detection This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive capabilities of the module.

1.6.7 Stepper Stall Detector (SSD)

The stepper stall detector (SSD) module provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ). The SSD module features the following:

• Programmable full step state
• Programmable integration polarity
• Blanking (recirculation) state
• 16-bit integration accumulator register
• 16-bit modulus down counter with interrupt

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 15

1.6.8 Flash memory

The PXD10 microcontroller has the following flash memory features:

• As much as 1 MB of burst flash memory — Typical flash memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 64 MHz — Two 4 × 128-bit page buffers with programmable prefetch control – One set of page buffers can be allocated for c ode-only, fixed partitions of code and data, all available for any access – One set of page buffers allocated to Display Controller Unit and the eDMA — 64-bit ECC with single-bit correction, double-bit detection for data integrity — 64 KB data flash memory — separate 4 16 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port
• Small block flash memory arrangement to suppor t features such as boot block, operating system block
• Hardware managed flash memory wr ites, erase and verify sequence
• Censorship protection scheme to prev ent flash memory content visibility
• Separate dedicated 64 KB data flash memory for EEPROM emulation — Four erase sectors each c ontaining 16 KB of memory — Offers Read-While-Write functi onality from main program space — Same data retention and program erase specification as main program flash memory array

1.6.9 Static random-access memory (SRAM)

The PXD10 microcontrollers have as much as 48 KB general-purpose on-chip SRAM with the following features:

• Typical SRAM access time: 0 wait-s tate for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block
• 32-bit ECC with single-bit correction, double bit detection for data integrity
• Supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory
• User transparent ECC encoding and decoding for byte, half word, and word accesses
• Separate internal power domain applied to full SRAM block, 8 KB SRAM block during STANDBY modes to retain contents during low power mode.

1.6.10 On-chip graphics SRAM

The PXD10 microcontroller has 160 KB on-chip graphics SRAM with the following features:

• Usable as general purpose SRAM
• Typical SRAM access tim e: 0 wait-state for reads and 32-bit writes
• Supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor16

1.6.11 QuadSPI serial flash controller

The QuadSPI module enables use of external serial flash memories supporting single, dual and quad modes of operation. It features the following:

• Memory mapping of external serial flash
• Automatic serial flash read command generation by CPU, DMA or DCU read access on AHB bus
• Supports single, dual and quad serial flash read commands
• Flexible buffering scheme to maximi ze read bandwidth of serial flash
• ‘Legacy’ mode allowing QuadSPI to be used as a standard SPI (no DSI or CSI mode)

1.6.12 Analog-to-digital converter (ADC)

The ADC features the following:

• 10-bit A/D resolution
• 0 to 5 V common mode conversion range
• Supports conversions speeds of as fast as 1 µs
• 16 internal and 8 external channels support
• As many as 16 single-ended inputs channels — All channels configured to have alternat e function as general purpose input/output pins – 10-bit ±3 counts accuracy (TUE)
• External multiplexer support to in crease as many as 23 channels — Automatic 1 × 8 mu ltiplexer control — External multiplexer connected to a dedicated input channel — Shared register between the 8 external channels
• Result register available fo r every non-multiplexed channel
• Configurable left- or right-aligned result format
• Supports for one-shot, scan and injection conversion modes
• Injection mode status bit implemented on adjacent 16-bit register for each result — Supports access to result and inject ion status with single 32-bit read
• Independently enabling of function for channels: — Pre-sampling — Offset error cancellation —O f f s e t r e f r e s h
• Conversion Triggering support — Internal conversion triggering from periodic interrupt timer (PIT)
• Four configurable analog comparator channels offering range comparison with triggered alarm — Greater than —L e s s t h a n — Out of range

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 17

• All unused analog inputs can be used as general purpose input and output pins
• Power down mode
• Optional support for DMA transfer of results

1.6.13 Sound generation logic (SGL) module

The SGL module has two modes of operation:

• Amplitude modulated PWM mode for low co st buzzers using any two eMIOS channels — Monophonic signal with amplitude control — 8-bit amplitude resolution — Ability to mix any two eMIOS channels. — Requires simple external RC lowpass filter
• Digital sample mode for higher quality sound using one eMIOS channel and eDMA — Up to 10-bit audio amplitude resolution — Polyphonic sound synthesis — Playback of sample based waveforms — Text-to-speech possibility — Requires external lowpass filter

1.6.14 Serial communication interface module (UART)

The PXD10 devices include as many as two UART modules and support UART Master mode, UART Slave mode and UART mode. The modules are UART state machine compliant to the UART 1.3 and 2.0 and 2.1 Specifications and handle UART frame transmission and reception without CPU intervention. The serial communication interface module offers the following:

• UART features: — Full-duplex operation — Standard non return-to-zero (NRZ) mark/space format — Data buffers with 4-byte receive, 4-byte transmit — Configurable word length (8-bit or 9-bit words) — Error detection and flagging – Parity, noise and framing errors — Interrupt driven operation wi th four interrupts sources — Separate transmitter and r eceiver CPU interrupt sources — 16-bit programmable baud-rate modul us counter and 16-bit fractional — Two receiver wake-up methods
• LIN features: — Autonomous LIN frame handling — Message buffer to stor e identifier and as many as 8 data bytes

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor18 — Supports message length of as long as 64 bytes — Detection and flagging of LIN errors — Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors — Classic or extended checksum calculation — Configurable Break duration of up to 36-bit times — Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional) — Diagnostic features – Loop back –S e l f T e s t – LIN bus stuck dominant detection — Interrupt driven operation with 16 interrupt sources — LIN slave mode features – Autonomous LIN header handling – Autonomous LIN response handling – Discarding of irrelevant LIN responses using as many as 16 ID filters

1.6.15 Serial Peripheral Interface (SPI) module

The SPI modules provide a synchronous serial interface for communication between the PXD10 MCU and external devices. The SPI features the following:

• As many as two SPI modules
• Full duplex, synchronous transfers
• Master or slave operation
• Programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Programmable transfer baud rate
• Programmable data frames from four to 16 bits
• As many as six chip select lines available, depending on package and pin multiplexing, enable 64 external devices to be selected using external muxing from a single SPI
• Eight clock and transfer attributes registers
• Chip select strobe available as alternate functi on on one of the chip select pins for deglitching
• FIFOs for buffering as many as four tr ansfers on the transmit and receive side
• General purpose I/O functionality on pins when not used for SPI
• Queueing operation possible through use of eDMA

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 19

1.6.16 Controller Area Ne twork (CAN) module

The PXD10 contains two CAN modules that offer the following features:

• Compliant with CAN protocol specification, Version 2.0B active
• 64 mailboxes, each configurab le as transmit or receive — Mailboxes configurable while modul e remains synchronized to CAN bus
• Transmit features — Supports configuration of multiple mailboxes to form message queues of scalable depth — Arbitration scheme according to me ssage ID or message buffer number — Internal arbitration to guarantee no inner or outer priority inversion — Transmit abort proce dure and notification
• Receive features — Individual programmable filters for each mailbox — 8 mailboxes configurable as a 6-entry receive FIFO — 8 programmable acceptance filters for receive FIFO
• Programmable clock source — System clock — Direct oscillator clock to avoid PLL jitter
• Listen only mode capabilities
• C A N S a m p l e r — Can catch the first message sent on the CAN network while the PXD10 is stopped. This guarantees a clean startup of the system without missing messages on the CAN network. — The CAN sampler is connected to one of the CAN RX pins.

1.6.17 Inter-IC Communications (I 2C) module

The I2C module features the following:

• As many as four I 2C modules supported
• Two-wire bi-directional serial bus for on-board communications
• Compatibility with I 2C bus standard
• Multimaster operation
• Software-programmable for one of 256 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automati c mode switching from master to slave
• Calling address iden tification interrupt
• Start and stop signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor20

1.6.18 Real Time Counter (RTC)

The Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation

• Configurable resolution for different timeout periods — 1 s resolution for >1 hour period — 1 ms resolution for 2 second period
• Selectable clock sources from external 32 KHz crystal, external 4–16 MHz crystal, internal 128 kHz RC oscillator or divided internal 16 MHz RC oscillator

1.6.19 Enhanced Modular Input/ Output System (Timers, PWM)

PXD10 microcontrollers have two eMIOS modules—one with 16 channels and one with 8—with input/output channels supporting a range of 16-bit input capture, output compare, and Pulse Width Modulation functions. The modules are configurable and can implement 8-channel, 16-bit input capture/output compare or 16-channel, 16-bit output pulse width modulation/input compare/output compare. As many as five additional channels are configurable as modulus counters. eMIOS features include:

• Selectable clock source from main FMPLL, a uxiliary FMPLL, external 4–16 MHz oscillator or

16 MHz Internal RC oscillator

• Timed I/O channels with 16-bit counter resolution
• Buffered updates
• Support for shifted PWM outputs to mini mize occurrence of concurrent edges
• Edge aligned output pulse width modulation — Programmable pulse pe riod and duty cycle — Supports 0% and 100% duty cycle — Shared or independent time bases
• Programmable phase sh ift between channels
• Selectable combination of pairs of eMIOS outputs to support sound generation
• DMA transfer support
• Selectable clock source from the primary FMPLL, auxiliary FMPLL, external 4–16 MHz oscillator or the 16 MHz internal RC oscillator. The channel configuration options for the 16-channel eMIOS module are summarized in Table 2.

The channel configuration options for the 8-channel eMIOS module are summarized in Table 3.

1.6.20 Periodic interrupt timer (PIT) module

• Four general purpos e interrupt timers
• As many as two dedicated interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by system clock frequency
• 32-bit counter for Real Time Interrupt, clocked from main external oscillator

Table 2. 16-channel eMIOS module channel configuration

1 Modulus up and down counters to support driving local and global counter busses

Table 3. 8-Channel eMIOS module channel configuration

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor22

1.6.21 System Timer Module (STM)

The STM is a 32-bit timer that supports commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256).

• One 32-bit up counter with 8-bit prescaler
• Four 32-bit compare channels
• Independent interrupt source for each channel
• Counter can be stopped in debug mode

1.6.22 Software Watchdog Timer (SWT)

The SWT features the following:

• Watchdog supporting software acti vation or enabled out of reset
• Supports normal or windowed mode
• Watchdog timer value wr itable once after reset
• Watchdog supports optional ha lting during low power modes
• Configurable response on timeout: reset, in terrupt, or interrupt followed by reset
• Selectable clock source for main system cl ock or internal 16 MHz RC oscillator clock

1.6.23 Interrupt Controller (INTC)

The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. Multiple processors can assert interrupt requests to each other through software settable interrupt requests. These same software settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software settable interrupt request to finish the servicing in a lower priority ISR. Therefore these software settable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following features:

• Unique 9-bit vector for each of the po ssible 128 separate interrupt sources
• Eight software-triggerable interrupt sources

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 23

• 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source
• Ability to modify the ISR or task priority. — Modifying the priority can be used to implem ent the Priority Ceiling Protocol for accessing shared resources.
• External non-maskable in terrupt directly accessing the main core critical interrupt mechanism
• 32 external interrupts

1.6.24 System Integration Unit (SIU)

The SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The GPIO features the following:

• As many as four levels of internal pin mul tiplexing, allowing exceptional flexibility in the allocation of device functions for each package
• Centralized general purpose input output (GPIO) control of as many as 132 input/output pins (package dependent)
• All GPIO pins can be independently conf igured to support pull-up, pull down, or no pull
• Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
• All peripheral pins can be alte rnatively configured as both general purpose input or output pins except ADC channels which support alternative configuration as general purpose inputs
• Direct readback of the pin value supported on all digital output pins through the SIU
• Configurable digital input filter that can be applied to as many as 14 general purpose input pins for noise elimination on external interrupts
• Register configuration protected ag ainst change with soft lock for temporary guard or hard lock to prevent modification until next reset.

1.6.25 System Clocks and Clock Generation Modules

The system clock on the PXD10 can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz oscillator.

• The source system clock freque ncy can be changed via an on-chip programmable clock divider (1 to 2).
• Additional programmabl e peripheral bus clock divider ratio (1 to 16)
• The PXD10 has two on-chip FMPLLs—the primary module and an auxiliary module. — Each features the following: – Input clock frequency from 4 MHz to 16 MHz – Lock detect circuitry conti nuously monitors lock status – Loss Of Clock (LOC) detection fo r reference and feedback clocks – On-chip loop filter (for impr oved electromagnetic interference performance and reduction of number of external components required)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor24 – Support for frequency ramping from PLL — The primary FMPLL module is for use as a system clock source. The auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation.

• The main oscillator provides the following features: — Input frequency range 4–16 MHz — Square-wave input mode — Oscillator input mode 3.3 V (5.0 V) — Automatic level control — PLL reference
• PXD10 includes a 32 KHz low power external oscillator for slow execution, low power, and Real Time Clock
• Dedicated internal 128 kHz RC oscillator fo r low power mode operation and self wake-up — ±10% accuracy across vol tage and temperature (after factory trimming) — Trimming registers to suppor t improved accuracy with in-application calibration
• Dedicated 16 MHz inte rnal RC oscillator — Used as default clock source out of reset — Provides a clock for rapid st art-up from low power modes — Provides a back-up clock in the event of PLL or External Oscillator clock failure — Offers an independent clock source for the Watchdog timer — ±5% accuracy across voltage and te mperature (after factory trimming) — Trimming registers to support frequency ad justment with in-application calibration

1.6.26 Crossbar Switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width. The crossbar allows four concurrent transactions to occur from any master port to any slave port but one of those transfers must be an instruction fetch from internal flash. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters having equal priority are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features:

• Four master ports — e200z0h core instruction port — e200z0h core complex load/store data port — eDMA controller — Display control unit

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 25

• Four slave ports — One flash port dedicated to the CPU — Platform SRAM — QuadSPI serial flash controller — One slave port combining: – Flash port dedicated to the Disp lay Control Unit and eDMA module – Graphics SRAM – Peripheral bridge
• 32-bit internal address bus , 32-bit internal data bus

1.6.27 Enhanced Direct Memory Access (eDMA)

The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:

• 16 channels support independent 8-, 16- or 32-bit single value or block transfers
• Supports variable sized que ues and circular queues
• Source and destination address regi sters are independently configured to post-increment or remain constant
• Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
• Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer
• DMA transfers possible between sy stem memories, QuadSPI, SPIs, I2C, ADC, eMIOS and General Purpose I/Os (GPIOs)
• Programmable DMA Channel Mux allows assignm ent of any DMA source to any available DMA channel with a total of as many as 64 potential request sources.

1.6.28 Memory Protection Unit (MPU)

The MPU features the following:

• 12 region descriptors for per-master protection
• Start and end address defi ned with 32-byte granularity
• Overlapping regions supported
• Protection attributes can optionally include process ID
• Protection offered for 3 concurrent read ports
• Read and write attri butes for all masters
• Execute and supervisor/user mode attributes for processor masters

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor26

1.6.29 Boot Assist Module (BAM)

The BAM is a block of read-only memory that is programmed once by Freescale. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are:

• Booting from internal flash memory
• Serial boot loading (A program is downloaded into RAM via CAN or UART and then executed)
• Booting from external memory Additionally, the BAM:
• Enables and manages the transition of the MCU from reset to user code execution
• Configures device for serial bootload
• Enables multiple bootcode starting locations out of reset through implementation of search for valid Reset Configuration Halfword
• Enables or disables software watchdog timer out of reset through BAM read of the Reset Configuration Halfword option bit 1.6.30 IEEE 1149.1 JTAG Controller (JTAGC) JTAGC features the following:
• Backward compatible to standard JTAG IE EE 1149.1-2001 test access port (TAP) interface
• Support for boundary scan testing

1.6.31 Nexus Development Interface (NDI)

Nexus features the following:

• Per IEEE-ISTO 5001-2003
• Nexus 2 Plus features supported — Static debug — Watchpoint messaging — Ownership trace messaging — Program trace messaging — Real time read/write of any internally memory mapped resources through JTAG pins — Overrun control, which selects whether to stal l before Nexus overruns or keep executing and allow overwrite of information — Watchpoint triggering, watchpoint triggers program tracing
• Configured via the IEEE 1149.1 (JTAG) port
• Nexus Auxiliary port supported on the 176 LQFP package FOR DEVELOPMENT ONLY — Narrow Auxiliary Nexus port supporti ng support trace, with two MDO pins — Wide Auxiliary Nexus port supporting higher bandwidth trace, with four MDO pins

2 Pinout and signal descriptions

This section shows the pinouts for the 144-pin LQFP packages. Any pins labeled “NC” must not be connected to any external circuit. Figure 2. 144-pin LQFP pinout for PXD1010

Figure 3. 144-pin LQFP pinout for PXD1005

Pinout and signal descriptions PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor30

2.3 Pad configuration during reset phases

All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are floating with the following exceptions:

• PB[5] (FAB) is pull-down. Without external str ong pullup the device starts fetching from flash.
• RESET pad is driven low. This is re leased only after PHASE2 reset completion.
• Main oscillator pads (EXTAL, XTAL) are tristate.
• Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
• The following pads are pullup: —P B [ 6 ] —P H [ 0 ] —P H [ 1 ] —P H [ 3 ] —E V T I

2.4 Voltage supply pins

V oltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization. There is a preferred power-up sequence for devices in the PXD10 family. That sequence is described in the following paragraphs. Broadly, the supply voltages can be grouped as follows:

• VREG HV supply (V DDR)
• Generic I/O supply —V DDA —V DDE_A —V DDE_B —V DDE_C —V DDE_E —V DDMA —V DDMB —V DDMC —V DDPLL
• LV supply (V DD12) The preferred order of ramp up is as follows: 1. Generic I/O supply

1. VREG HV supply (V DDR - Should be the last HV supply to ramp up. It is also OK if all HV and

2.5 Pad types

• The port pin summary table
• The pad type descriptions

Table 2. Voltage supply pin descriptions

144 LQFP 176 LQFP

1 Decoupling capacitors must be connected between these pins and the nearest VSS12 pin.

1.2 V core supply 42, 51, 103, 118 , 133 50, 67, 123, 148, 163

2 All stepper motor supplies need to be at same level (3.3 V or 5 V). 3 This signal needs to be connected to ground during normal operation.

9 V - 12 V flash test analog write signal 26 26

• The description of the pad configuration registers in Chapter 37, System Integration Unit Lite (SIUL)
• The device data sheet

2.6 System pins

The system pins are listed in Table 3.

2.7 Debug pins

The debug pins are listed in Table 4 and Table 5. Table 3. System pin descriptions

144 LQFP 176 LQFP 208 MAPBG

oscillator amplifier circuit. oscillator amplifier circuit. 1 VREG_BYPASS should be pulled down externally. Table 4. Debug pin descriptions

208 MAPB

there are additional dedicated Nexus pins. Table 5. Debug pin descriptions

144 LQFP 176 LQFP TEPBGA2

Table 4. Debug pin descriptions (continued)

2.8 Port pin summary

The functional port pins are listed in Table 6. Table 6. Port pin summary

Table 6. Port pin summary (continued)

7 PCR[99] Option 0

7 PCR[102] Option 0

function is reported as “—”. their functionality. ADC functions are enabled using the PCR[APC] bit; other functions are enabled by enabling the respective module. of the PXD10 Microcontroller Reference Manual for details. 5 Reset configuration is given as I/O direction and pull, e.g., “Input, Pullup”. 6 This option on this pin has alternate functions that depend on whether the QuadSPI is in SPI mode or in serial flash mode (SFM). 7 Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when needed. 8 This pin can be used for LCD supply pin VLCD. Refer to the voltage supply pin descriptions in the PXD10 data sheet for details.

Pinout and signal descriptions PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor52

2.8.1 Signal details

Table 7. Pad type descriptions device reference manual for the features available for each pad type.

Description

F Fast (with GPIO and digital alternate function) J Slow pads with analog muxing (built for ADC channels) M1 Medium (with GPIO and digital alternate function) M2 Programmable medium/slow pad (programmed via the slew rate control in the PCR): Slew rate disabled: Slow driver configuration (AC/DC parameters same as for a slow pad) Slew rate enabled: Medium driver configuration (AC/DC parameters same as for a medium pad) S Slow (with GPIO and digital alternate function) SMD Stepper motor driver (with slew rate control) X Oscillator Table 8. Signal details conversion. ANS[0:15] connect to ATD channels [32:47]. multiplexed channels connect to ATD channels [64:71]. the lowest flash sector containing a valid boot signature. DCU_DE DCU Indicates that valid pixels are present.

timed input or output functions. Table 8. Signal details (continued)

(DTM). Only available in reduced port mode. RXD_1 LINFlex SCI/LIN Receive data signal . Input pad for the LIN SCI module. Connects to the internal LIN second port. device from the clock generation module.

Electrical characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 55

3 Electrical characteristics

3.1 Introduction

This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by internal pull up and pull down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column.

3.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 9 are used and the parameters are tagged accordingly in the tables where appropriate. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. Table 9. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. relevant sample size across process variations. D Those parameters are derived mainly from simulations.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor56

3.3 NVUSRO register

Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Nonvolatile User Options (NVUSRO) register. For a detailed description of the NVUSRO register, please see the chip reference manual.

3.3.1 NVUSRO[PAD3V5V] field description

Table 10 shows how NVUSRO[PAD3V5V] controls the device configuration. The DC electrical characteristics are dependent on the PAD3V5V bit value.

3.3.2 NVUSRO[OSCILLATOR_MARGIN] field description

Table 10 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. The 4–16 MHz fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 10. PAD3V5V field description1 1 See the device reference manual for more information on the NVUSRO register. 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V Table 11. OSCILLATOR_MARGIN field description1 1 See the device reference manual for more information on the NVUSRO register.

2 Default manufacturing value before Flash initialization is ‘1’

0 Low consumption configuration (4 MHz/8 MHz)

1 High margin configuration (4 MHz/16 MHz)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 57

3.4 Absolute maximum ratings

Table 12. Absolute maximum ratings

1 SR C Voltage on VDDE_A (I/O supply) pin with

1 SR C Voltage on VDDE_B (I/O supply) pin with

1 SR C Voltage on VDDE_C (I/O supply) pin with

1 SR C Voltage on VDDE_E (I/O supply) pin with

1 SR C Voltage on VDDMA (stepper motor supply) pin

2 SR C I/O supply ground — 0 0 V

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor58 NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN >V DD or VIN <V SS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. IINJPAD SR C Injected input current on any pin during overload condition — 10 10 mA during overload condition — 50 50 TSTORAGE SR C Storage temperature — 55 150 °C NOTES: 1 Throughout the remainder of this document VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC, unless otherwise noted. 2 Throughout the remainder of this document VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC, unless otherwise noted. 3 As long as the current injection specification is adhered to, then a higher potential is allowed. Table 12. Absolute maximum ratings (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 59

3.4.1 Recommended operating conditions

Maximum slew time for the supplies to ramp up should be 1 second, which is slowest ramp-up time. CAUTION VDDE_C and VDDA must be the same voltage. VDDMB and VDDMC must be the same voltage. Table 13. Recommended operating conditions (3.3 V)

1 SR C Voltage on VDDA pin (ADC reference) with

2 SR C Voltage on VDDR pin (regulator supply) with

6 SR C I/O supply ground — 0 0 V

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor60 VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin with respect to VSS —0 0 V VLCD SR C Voltage on VLCD (LCD supply) pin with respect to VSS —0 V DDE_A + 0.3 V TVDD SR C V DD slope to ensure correct power up — 5 10–6 0.25 V/µs TA SR C Ambient temperature under bias — 40 105 °C TJ SR C Junction temperature under bias 40 150 NOTES: 1 100 nF capacitance needs to be provided between VDDA/VSSA pair. 2 At least 10 µF capacitance must be connected between VDDR and VSS. This is required because of sharp surge due to external ballast. 3 VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC. 4 100 nF capacitance needs to be provided between each VDD/VSS pair 5 Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/O’s DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL device is reset. 6 VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC) unless otherwise noted. Table 14. Recommended operating conditions (5.0 V)

3 SR C Voltage on VDDR pin (regulator supply) with

Table 13. Recommended operating conditions (3.3 V) (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 61 NOTE RAM data retention is guaranteed with VDD12 not below 1.08 V . VSS VDDE_A SR C Voltage on VDDE_A (I/O supply) pin with respect to ground (VSSE_A) —4 . 5 5 . 5 V VDDE_B SR C Voltage on VDDE_B (I/O supply) pin with respect to ground (VSSE_B) —4 . 5 5 . 5 V VDDE_C

7 SR C Voltage on VDDE_C (I/O supply) pin with

respect to ground (VSSE_C) —4 . 5 5 . 5 V VDDE_E SR C Voltage on VDDE_E (I/O supply) pin with respect to ground (VSSE_E) —4 . 5 5 . 5 V VDDMA SR C Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) —4 . 5 5 . 5 V VDDMB SR C Voltage on VDDMB (stepper motor supply) pin with respect to ground (VSSMB) —4 . 5 5 . 5 V VDDMC SR C Voltage on VDDMC (stepper motor supply) pin with respect to ground (VSSMC) —4 . 5 5 . 5 V VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin with respect to VSS —0 0 V VLCD SR C Voltage on VLCD (LCD supply) pin with respect to VSS —0 V DDE_A +0 . 3 V TVDD SR C V DD slope to ensure correct power up — 3 10–6 0.25 V/µs TA SR C Ambient temperature under bias — 40 105 °C TJ SR C Junction temperature under bias — 40 150 °C NOTES: 1 100 nF capacitance needs to be provided between VDDA/VSSA pair. 2 Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical characteristics may not be guaranteed below 4.5 V during the voltage drop sequence. 3 10 µF capacitance must be connected between VDDR and VSS12. This is required because of sharp surge due to external ballast. 4 VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC. 5 100 nF capacitance needs to be provided between each VDD/VSS pair 6 VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC) unless otherwise noted. 7 VDDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = V DDA 100 mV. Table 14. Recommended operating conditions (5.0 V) (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor62

3.4.2 Connecting power supply pins: What to do and what not to do

• D o : — Have all power/ground supplies co nnected on the board from a strong supply source rather than weak voltage divider sources unless there is “NO IO activity” in the section — Meet the supply specifications for max / ty pical operating conditions to guarantee correct operation — Place the decoupling near the supply/gr ound pin pair for EMI emissions reduction — Route high-noise supply/ground away from sensitive signals (for example, ADC channels must be away from SMD supply/motor pads) — Use star routing for the ballast supply from the VDDR supply to avoid ballast startup noise injected to VDDR supply of the device — Use LC inductive filtering for ADC, OSC, and PLL supplies if these are generated from common board regulators
• Do not: — Violate injection current limit per IO/All IO pins as per specifications — Connect sensitive supplies/ground on noisy su pplies/ground (that is, ADC, PLL, and OSC) — Use SMD supply for generation of noise free supply as these are most noisy lines in the system — Connect different VDD pins (connected together inside the device) to different potentials.

3.5 Thermal characteristics

Table 15. LQFP thermal characteristics meets JEDEC specification for this package. specification for the specified package.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 63

3.5.1 General notes for specification s at maximum junction temperature

An estimate of the chip junction temperature, TJ, can be obtained from Equation 1: TJ = TA + (RJA  PD) Eqn. 1 where: TA = ambient temperature for the package (°C) RJA = junction to ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:

• Construction of the applicati on board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and elec trical connections to the planes
• Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm 2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. 3 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor64 At a known board temperature, the junction temperature is estimated using Equation 2: TJ = TB + (RJB  PD) Eqn. 2 where: TB = board temperature for the package perimeter (°C) RJB = junction-to-board thermal resistance (°C/W) per JESD51-8S PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA Eqn. 3 where: RJA = junction to ambient thermal resistance (°C/W) RJC = junction to case thermal resistance (°C/W) RCA= case to ambient thermal resistance (°C/W) RJC s device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using Equation 4: TJ = TT + (JT x PD) Eqn. 4 where: TT = thermocouple temperature on top of the package (°C) JT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 65 The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 USA (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org.

3.6 Electromagnetic compatib ility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

3.6.1 EMC requirements on board

The following practices help minimize noise in applications.

• Place a 100 nF capacitor between each of the VDD12/VSS12 supply pairs and also between the VDDPLL/VSSPLL pair. The voltage regulator also requires stability capacitors for these supply pairs.
• Place a 10 F capacitor on VDDR.
• Isolate VDDR with ballast emitter to a void voltage droop during STANDBY mode exit.
• Enable pad slew rate only as necessary to eliminate I/O noise: — Enabling slew rate for SMD pa ds will reduce noise on motors. — Disabling slew rate for non-SMD pa ds will reduce noise on non-SMD IOs.
• Enable PLL modulation (± 2%) for system clock.
• Place decoupling capacitors for all HV supplies close to the pins.

3.6.2 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

• Software recommendations The software flowchart must include the management of runaway conditions such as:

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor66 — Corrupted program counter — Unexpected reset — Critical data corrupti on (control registers...)

• Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.

3.6.3 Electromagnetic interference (EMI)

3.6.4 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

3.6.4.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Table 16. EMI testing specifications1 1 EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03.

30 MHz – 1 GHz: RBW 120 kHz, step size 80 kHz

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 67

3.6.4.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is appl ied to each power supply pin.
• A current injection is applied to eac h input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard.

3.7 Power management electrical characteristics

3.7.1 Voltage regulator electrical characteristics

The internal high power or main regulator (HPREG) requires an external NPN ballast transistor (see Table 19 and Table 20) to be connected as shown in Figure 5 as well as an external capacitance (CREG) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 15 nH. For the PXD10 microcontroller, 100 nF should be placed between each of the VDD12/VSS12 supply pairs and also between the VDDPLL/VSSPLL pair. These decoupling capacitors are in addition to the required stability capacitance. Additionally, 10 F should be placed between the VDDR pin and the adjacent VSS pin. Table 17. ESD absolute maximum ratings1 2 Table 18. Latch-up results

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor68 Figure 5. External NPN ballast connections conditions. X7R type materials are recommended for all capacitors, based on ESR characteristics. values. They should be located close to the device pin. Table 19. Allowed ballast components Table 20. Ballast component parameters

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 69 Table 21. Voltage regulator electrical characteristics 1 Time after the input supply to the voltage regulator has ramped up (VDDR). Table 22. Low-power voltage regulator electrical characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor70 SR C External decoupling/stability capacitor 4 capacitances of 10 µF each 10 4—1 0 4µ F C ESR of external cap 0.1 — 0.6 ohm C 1 bond wire R + 1 pad R 0.2 — 1 ohm LBOND CC D Bonding Inductance for Bipolar Base Control pad — 0— 1 5 n H CC D Power supply rejection @ DC @ no load C L =1 0µ F 4— — 5 5 d B D any frequency @ no load 32 D @ DC @ max load 24 D any frequency @ max load CC D Load current transient C L =1 0µ F 4 — — 10% to 90% of IL in 10 s tSU CC C Start-up time after input supply stabilizes 2 CL =1 0µ F 4 — — 700 µs NOTES: 1 On this device, the ultra-low-power regulator is always enabled when the low-power regulator is enabled. Therefore, the total low-power current capacity is the sum of IL values for the two regulators. 2 Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted the Power OK signal. Table 23. Ultra-low-power voltage regulator electrical characteristics Table 22. Low-power voltage regulator electrical characteristics (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 71

3.7.2 Voltage monitor electrical characteristics

The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD12 voltage while device is supplied:

• POR monitors V DD during the power-up phase to ensure device is maintained in a safe reset state
• LVDHV3 monitors V DD to ensure device reset below minimum functional supply
• LVDHV5 monitors V DD when application uses device in the 5.0 V ± 10% range
• LVDLVCOR monitors power domain No. 1
• LVDLVBKP monitors power domain No. 0

3.7.3 Low voltage domain power consumption

Table 25 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. CC D Power supply rejection @ DC @ no load — — 25 dB D any frequency @ no load 7 D @ DC @ max load 25 D any frequency @ max load CC D Load current transient — — 10 to 90 A in 70 s Table 24. Low voltage monitor electrical characteristics Table 23. Ultra-low-power voltage regulator electrical characteristics (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor72 Table 25. DC electrical characteristics peripherals, operating frequency, etc.

16 MHz fast internal RC oscillator

Table 26. IDDSTDBY specification1 1 All current values are typical values.

8 KB RAM on

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 73

3.7.4 Recommended power-up and power-down order

Figure 6 shows the recommended order for powering up the power supplies on this device. The 1.2 V regulator output starts after the device’s internal POR (VDDREG HV) is deasserted at approximately 2.7 V on VDDREG . Figure 6. Recommended order for powering up the power supplies Figure 7 shows the recommended order for powering down the power supplies on this device. 2 Values provided for reference only. The permitted temperature range of the chip is specified separately.

1.2 V regulator output

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor74 Figure 7. Recommended order for powering down the power supplies down before the 3.3 V regulator shuts down.

3.7.5 Power-up inrush current profile

condition (fastest PVT and fastest power ramp time). Figure 8. Power-up inrush current profile

1.2 V supply

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 75 The HPREG has a “soft startup” profile which increases the supply in steps of approximately 50 mV in a series of approximately 25 steps. Therefore, the peak current is within 750 mA of the maximum current during startup. This eliminates any noise on the VDDR supply during startup and charging of NPN emitter stability capacitance of 40 F (minimum). Soft startup also occurs when waking up from standby mode to limit noise on the VDDR supply. In case VDDR is shared between the device and the ballast, it must be star routed on the board or isolated as much as possible to avoid any noise injected by the ballast. Soft startup will help to limit this noise but a VDDR capacitor close to the ballast pin is critical here. A minimum capacitance of 10 F is needed. Table 27 shows the typical and maximum startup currents.

3.7.6 HPREG load regulation characteristics

The HPREG exhibits a very strong load-regulation behavior (the transition from low- to high-current state is regulated quickly). This is illustrated in Figure 10, which shows a 10–150 mA jump over 10 ns. Under any case of load transition, the HPREG responds within 100 ns and stabilizes within 5 s. This helps improve the stability of the 1.2 V supply and settling time. Figure 9. HPREG load regulation

3.8 I/O pad electrical characteristics

3.8.1 I/O pad types

Table 27. Startup current

3 V input supply

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor76

• Slow pads — These are the mo st common pads, providing a good compromise between transition time and low electromagnetic emission.
• Medium pads — These are provided in two types (M1 and M2) and provide transitions fast enough for the serial communication channels. M2 pads include slew rate control.
• Fast pads — These provide maximum speed. There are used for improved NEXUS debugging capability.
• SMD pads — These provide a dditional current capability to drive stepper motor loads.
• Digital I/O with analog (J) pad — These provide input and output digital features and analog input for ADC. M2 and Fast pads can disable slew rate to reduce electromagnetic emission, at the cost of reducing AC performance.

3.8.2 I/O input DC characteristics

Table 28 provides input DC electrical characteristics as described in Figure 10. Figure 10. I/O input DC electrical characteristics definition Table 28. I/O input DC electrical characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 77

3.8.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:

• Table 29 provides weak pull figures. Both pull-up and pull-down resistances are supported.
• Table 30 provides output driver characteristics for I/O pads when in SLOW configuration.
• Table 31 provides output driver characteristics for I/O pads when in MEDIUM configuration (applies to both M1 and M2 type pads).
• Table 32 provides output driver characteristics for I/O pads when in FAST configuration.
• Table 33 provides SMD pad characteristics. ILKG CC P Input leakage current — –1 — 1 A TA = -40°C — 2 — nA TA = 25°C — 2 — nA CT A = 105°C — 12 500 nA PT J = 150°C — 70 1000 nA RON CC D Resistance of the analog switch inside the J pad type2 Supply range 3.3–5 V —— 1 k  NOTES: 1 VDD = 3.3 V  10% / 5.0 V  10%, TA = 40 to 105 °C. 2 Applies to the J pad type only.

Table 29. I/O pull-up/pull-down DC electrical characteristics 1 1 The pull currents are dependent on the HVE settings. RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 28. I/O input DC electrical characteristics (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor78 Table 30. SLOW configuration output buffer electrical characteristics configured in input or in high impedance state. 3 CL calculation should include device and package capacitances (CPKG < 5 pF).

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 79 Table 31. MEDIUM configuration output buffer electrical characteristics configured in input or in high impedance state. 3 CL includes device and package capacitance (CPKG <5 p F ) .

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor80 Table 32. FAST configuration output buffer electrical characteristics configured in input or in high impedance state. 3 CL includes device and package capacitance (CPKG <5 p F ) .

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 81

3.8.4 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 34. Table 35 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAV G S E G maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 33. SMD pad electrical characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor82 Table 34. I/O supply segment

1 LCD pad segment containing pad supplies VDDE_A

2 Miscellaneous pad segment containing pad supplies VDDE_B

3 ADC pad segment containing pad supplies VDDE_C

4 VDDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = V DDA 100 mV.

5 Stepper Motor pad segment containing I/O supplies VDDMA, VDDMB, VDDMC

6 Miscellaneous pad segment containing pad supplies VDDE_E

144 LQFP pins 1–21

176 LQFP pins 1–21

Table 35. I/O consumption

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 83 IRMSMED CC D Root mean square I/O current for MEDIUM configuration CL = 25 pF , 2 MHz VDD = 5.0 V ±10%, PAD3V5V = 0 —— 6 . 6 m A DC L = 25 pF , 4 MHz VDD = 5.0 V ±10%, PAD3V5V = 0 —— 1 3 . 4 DC L = 100 pF , 2 MHz VDD = 5.0 V ±10%, PAD3V5V = 0 —— 1 8 . 3 DC L = 25 pF , 2 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 5 . 0 DC L = 25 pF , 4 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 8 . 5 DC L = 100 pF , 2 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 1 1 . 0 IRMSFST CC D Root mean square I/O current for FAST configuration CL = 25 pF , 2 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 —— 2 2 . 0 m A DC L = 25 pF , 4 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 —— 3 3 . 0 DC L = 100 pF , 2 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 —— 5 6 . 0 DC L = 25 pF , 2 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 1 4 . 0 DC L = 25 pF , 4 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 2 0 . 0 DC L = 100 pF , 2 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 2 5 . 0 IDYNSEG SR D Sum of all the dynamic and static I/O current within a supply seg- ment VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 110 mA DV DD = 3.3 V ± 10%, PAD3V5V = 1 — — 65 IAVGSEG SR D Sum of all the static I/O current within a supply segment VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70 mA DV DD = 3.3 V ± 10%, PAD3V5V = 1 — — 65 IDDMxAVG SR D Sum of currents of two motors assigned to segment VDDMx, VSSMx pair VDD = 5.0 V ± 10%, PAD3V5V = 0 TJ =1 3 0C ——9 0 VDD = 5.0 V ± 10%, PAD3V5V = 0 TJ =– 4 0C —— 1 2 0 NOTES: 1 VDD = 3.3 V  10% / 5.0 V  10%, TA = 40 to 105 °C, unless otherwise specified Table 35. I/O consumption (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor84

3.9 SSD specifications

3.9.1 Electrical characteristics

3.9.2 Accumulator values

Equation 5 describes the accumulator value in unipolar configuration. The voltage Vin is applied between the integrator input and VDDM. The internal generated reference voltage is not connected. The accumulator value is a function of VDDM, the number of samples (Nsample) taken and the SSD constant (SSDconst). The SSD constant and offset (SSDconst, SSDoffset) vary with temperature and process. Eqn. 5 Equation 6 describes the accumulator value in bipolar configuration. The voltage Vin is applied between the integrator input and the reference output. The accumulator value depends on the same parameters as in the unipolar case but the inaccuracy of the voltage reference (Vvref) is compensated. Eqn. 6

3.10 RESET electrical characteristics

Table 36. SSD electrical characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor86 Table 37. Reset electrical characteristics (RGM) section of the device reference manual). 3 CL includes device and package capacitance (CPKG <5 p F ) .

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 87

3.11 Fast external crystal o scillator (4–16 MHz) electrical

The device provides an oscillator/resonator driver. Figure 13 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Figure 13. Crystal oscillator and resonator connection scheme XTAL/EXTAL must not be directly used to drive external circuits. Table 38. Crystal description

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor88 Figure 14. Fast external crystal oscillator (4–16 MHz) electrical characteristics includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. Table 39. Resonator description

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 89

3.12 Slow external crystal oscillator (32 KHz) electrical characteristics

The device provides a low power oscillator/resonator driver. Table 40. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 91

3.13 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 41. Slow external crystal oscillator (32 KHz) electrical characteristics 2 The quoted figure is based on a board that is properly laid out and has no stray capacitances. Table 42. FMPLL electrical characteristics 1 VDDPLL = 1.2 V ± 10%, TA = 40 to 105 °C, unless otherwise specified. functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 3 fCPU 64 MHz can be achieved only at temperatures up to TA = 105 °C with a maximum FM depth of 2%.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor92

3.14 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.

3.15 Slow internal RC oscillator (128 kHz) electrical characteristics

The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module. Table 43. Fast internal RC oscillator (16 MHz) electrical characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 93

3.16 Flash memory electrical characteristics

Table 44. Slow internal RC oscillator (128 kHz) electrical characteristics Table 45. Program and erase specifications 1 Typical program and erase times assume nominal supply values and operation at 25 °C. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor94

3.17 ADC electrical characteristics

The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter. Table 46. Flash module life Table 47. Flash memory read access timing

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 95 Figure 17. ADC Characteristics and Error Definitions

3.17.1 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is considered. when the analog signal source is a high-impedance source.

1 LSB (ideal)

1 LSB ideal = VDDA / 1024

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor96 or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 7: Eqn. 7 Equation 7 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 18. Input equivalent circuit (precise channels)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor98 (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is Eqn. 8 Equation 8 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Eqn. 9 The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 10: Eqn. 10

• A second charge transfer involves also C F (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Eqn. 11 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 12 Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 13 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 13 The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal 1 RSW RAD+= CP CS VA1 CS CP1 CP2++ VA CP1 CP2+= VA2 CS CP1 CP2 CF+++ VA CF VA1+C P1 CP2+C S+=

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 99 source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Figure 21. Spectral representation of input signal the time in which the sampling switch is closed.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor100

3.17.2 ADC conversion characteristics

For input leakage current specification, see Table 28. Table 48. ADC conversion characteristics

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 101

3.18 LCD driver electrical characteristics

OFS CC T Offset error After offset cancellation — 0.5 — LSB GNE CC T Gain error — 0.6 — LSB TUEx CC P Total unadjusted error for extended channel Without current injection –3 — 3 LSB T With current injection –4 — 4 NOTES: 1 VDDA = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 105 °C, unless otherwise specified. 2 Analog and digital VSS must be common (to be tied together externally). 3 VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF 4 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming.

5 The maximum sample rate is 1 million samples per second, provided the source impedance and current

limiter(>1 k) are calculated adequately. - Filter capacitor at analog source output must meet the criteria Cf (filter capacitor) > 2048*Cs (sampling capacitor which is 3 pF) 6 This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result’s register with the conversion result. Table 49. LCD driver specifications 2 Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.

3 With PWR=10, BSTEN=0, and BSTAO=0

Table 48. ADC conversion characteristics (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor102

3.19 Pad AC specifications

Table 50. Pad AC specifications (5.0 V, PAD3V5V = 0)1

1 Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition

2 Slope at rising/falling edge

3 F a s t 1—6 1—4— — 1 0 0 1 8 — 5 5 2 5

4 Pull Up/Down

Table 51. Pad AC specifications (3.3 V, PAD3V5V = 1)1

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 103 Figure 22. Pad output delay

3 F a s t 1 — 6 1 — 4 ——7 2 3 —4 0 2 5

Table 51. Pad AC specifications (3.3 V, PAD3V5V = 1)1 (continued)

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor104

3.20 AC timing

3.20.1 IEEE 1149.1 interface timing Table 52. SMD pad delays Table 53. JTAG interface timing1

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor106 Figure 25. JTAG boundary scan timing

3.20.2 Nexus debug interface

Table 54. Nexus debug port timing1

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor108 Figure 28. Nexus TDI, TMS, TDO timing

3.20.3 Interface to TFT LCD panels

1. DCU_CLK latches data into the pa nel on its positive edge (when positive polarity is selected). In

active mode, DCU_CLK runs continuously.

1. DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
2. DCU_VSYNC causes the panel to start a new fram e. It always encompasses at least one HSYNC
3. DCU_DE acts like an output enable signal to th e LCD panel. This output enables the data to be

shifted onto the display. When disabled, the data is invalid and the trace is off.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 109 Figure 29. TFT LCD interface timing overview1

3.20.3.1 Interface to TFT LCD panels—pixel level timings

or active-low. The default is active-high. The DCU_DE signal is always active-high. programmed via the DCU Clock Confide Register (DCCR) in the system clock module. parameters are programmed via the VSYN_PARA register.

1. In Figure 29, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and

Table 55. LCD interface timing parameters—horizontal and vertical

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor110 Figure 30. Horizontal sync timing Figure 31. Vertical sync pulse

3.20.3.2 Interface to TFT LCD panels

Table 55. LCD interface timing parameters—horizontal and vertical (continued)

123 D E L T A _ XInvalid Data Invalid Data

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 111 Figure 32. TFT LCD interface timing parameters

3.20.4 External Interrupt (IRQ) and No n-Maskable Interrupt (NMI) timing

Table 56. TFT LCD interface timing parameters 1,2,3,4

2 Intra bit skew is less than 2 ns

3 Load CL = 50 pF for panel frequency up to 20 MHz

4 Load CL = 25 pF for panel frequency from 20 to 32 MHz

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor112 Figure 33. IRQ and NMI timing Table 57. IRQ and NMI timing 1 Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both. Table 58. eMIOS timing1 delays. Refer to the pad specification section for the details.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 113

3.20.6 FlexCAN timing

The CAN functions are available as TX pins at normal IO pads and as RX pins at the always on domain. There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.

3.20.7 Deserial Serial Peripheral Interface (DSPI)

Table 59. FlexCAN timing1 and CL = 50 pF with SRC = 0b00. Table 60. DSPI timing1

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor114 Figure 34. DSPI classic SPI timing — master, CPHA = 0 1 DSPI timing specified at VDDE_x = 3.0 V to 5.5 V, TA = 40 to 105 °C, and CL = 50 pF with SRC = 0b11. 2 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. 3 The actual minimum SCK Cycle Time is limited by pad performance.

4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK = 2

5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]

6 This delay value is corresponding to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. Table 60. DSPI timing1 (continued) Note: Numbers in circles refer to values in Table 60.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor118 Figure 41. DSPI modified transfer format timing — slave, CPHA = 1

3.20.8 I 2C timing

Table 61. I2C Input Timing Specifications — SCL and SDA

1 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device

Note: Numbers in circles refer to values in Table 60.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 119 Figure 42. I2C input/output timing

3.20.9 QuadSPI timing

• All data are based on a negative edge data launch from PXD10 and a positive edge data capture as shown in the timing diagrams.
• Typical values are pr ovided from center-split material at 25C and 3.3 V . Minimum and maximum values are from a temperature variation of –45 C to 105 C and the following supply conditions: — IO voltage: 3.2 V , core supply: 1.2 V

Table 62. I2C Output Timing Specifications — SCL and SDA listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR.

2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device

or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor120 — IO voltage: 3.6 V , core supply: 1.2 V

• All measurements are taken at 70% of VDDE levels for clock pin and 50% of VDDE level for data pins.
• Timings correspond to QSPI_SMPR = 0x0000_000x. See the PXD10 Microcontroller Reference Manual for details.
• A negative value of hold is an indication of pa d delay on the clock pad (delay between the edge capturing data inside the device and the edge appearing at the pin).
• Values are with a load of 15pF on the output pins.

Figure 43. QuadSPI output timing diagram Table 63. QuadSPI timing

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor122

4 Package mechanical data

4.1 144 LQFP

Figure 46. LQFP144 mechanical drawing (Part 1 of 3)

Figure 47. LQFP144 mechanical drawing (Part 2 of 3)

Figure 48. LQFP144 mechanical drawing (Part 3 of 3)

Figure 49. LQFP176 mechanical drawing (Part 1 of 3)

Figure 50. LQFP176 mechanical drawing (Part 2 of 3)

Figure 51. LQFP176 mechanical drawing (Part 3 of 3)

Ordering information

PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 129

5 Ordering information

Figure 52. PXD10 orderable part number description Table 64. PXD10 orderable part number summary Note: Not all options are available on all devices. See Table 64 for more information.

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Freescale Semiconductor Japan Ltd. Freescale Semiconductor China Ltd. circuits or integrated circuits based on the information in this document. Semiconductor was negligent regarding the design or manufacture of the part. Freescale sales representative. http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2011. All rights reserved.

6 Revision history

Table 65. Document revision history 1 30 Sep 2011 Initial release.