MPXD2010VLT120R

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Data Sheet: Advance Information Document Number: PXD20 Rev. 2, 04/2012 This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. PXD20

416 TEPBGA

176 LQFP

208 LQFP

© Freescale Semiconductor, Inc., 2011–2012. All rights reserved. Preliminary—Subject to Change Without Notice The PXD20 represents a new generation of 32-bit microcontrollers targeting single-chip industrial HMI applications. PXD20 devices are part of the PX family of Power Architecture ®-based devices. This family has been designed with an emphasis on providing cost-effective and high quality graphics capabilities. PXD20 devices contain 2 MB internal flash memory. Serial flash memory and DRAM interfaces are provided to allow even greater system flexibility. The PXD20:

• Includes 2 MB internal flash memory, 1 MB internal graphics SRAM, and 64 KB system SRAM
• Offers high processing performance operating at speeds up to 125 MHz
• Is optimized for low power consumption The PXD20 is designed to reduce development and production costs of TFT-based displays by providing a single-chip solution with the processing and storage capacity to host and execute real-time application software and drive TFT displays directly. The PXD20 features a 2D OpenVG 1.1 graphics accelerator, Video Input Unit (VIU2) and two on-chip display control units (DCU3 and DCULite) designed to drive two color TFT displays simultaneously. The PXD20 includes a enhanced QuadSPI serial flash controller and an optional DRAM controller allowing graphics RAM expansion externally. The PXD20 is compatible with the existing development infrastructure of current Power Architecture devices and are supported with software drivers, operating systems and configuration code to assist with application development. PXD20 Microcontroller Data Sheet 4.6 EMI (electromagnetic interference) characteristics . . . 70

4.9 RESET

4.10 Fast external crystal osci llator (4–16 MHz) electrical

4.11 Slow external crystal osci llator (32 KHz) electrical

4.13 Fast internal RC oscill ator (16 MHz) electrical

4.14 Slow internal RC oscill ator (128 kHz) electrical

1 Overview

1.1 Device comparison

Table 1. PXD20 Family Feature Set

4 KB Instruction-Cache

Table 1. PXD20 Family Feature Set (continued)

1.2 Block diagram

Figure 1. PXD20 block diagram

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 5

1.3 Feature list

• Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d) — Memory Management Unit (MMU) — 4 KB, 2/4-way instruction cache
• 2 MB on-chip ECC flash memory with: — Flash memory controller — Prefetch buffers
• 64 KB on-chip ECC SRAM
• 1 MB on-chip non-ECC graphics SRAM wi th two-port graphics SRAM controller
• Memory Protection Unit (MPU) with up to 16 region descriptors and 32-byte region granularity to provide basic memory access permission and ensure separation between different codes and data
• Interrupt Controller (INTC) with 181 peripheral interrupt sources and eight software interrupts
• Two Frequency-Modulated Phase-Locked Loops (FMPLLs) — Primary FMPLL (FMPLL0) provides a system clock up to 125 MHz — Auxiliary FMPLL (FMPLL1) is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules, QuadSPI and as alternate clock to the DCU and DCU-Lite for pixel clock generation
• Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus masters
• 16-channel Enhanced Direct Memory Access controller (eDM A) with multiple transfer request sources using a DMA channel multiplexer
• Boot Assist Module (BAM) with 8 KB dedicated ROM for embedded boot code supports boot options including download of boot code via a serial link (CAN or SCI)
• Two Display Control Units (DCU3 and DCULite) for direct drive of up to two TFT LCD displays up to XGA resolution
• Timing Controller (TCON) and RS DS interface for the DCU3 module
• 2D OpenVG 1.1 and raster gr aphics accelerator (GFX2D)
• Video Input Unit (VIU2) supporting 8/10-bit ITU656 video input, YUV to RGB conversion, video down-scaling, de-interlacing, contrast adjustment and brightness adjustment.
• DRAM controller supporting DDR1, DDR2, LPDDR1 and SDR DRAMs
• Stepper Motor Controller (SMC) — High-current drivers for as many as six stepper motors driven in full dual H-bridge configuration — Stepper motor return-to-zero and stall detection module — Stepper motor short circuit detection
• Sound Generator Module (SGM) — 4-channel mixer — Supports PCM wave playback and synthesized tones — Optional PWM or I 2S outputs
• Two 16-channel Enhanced Modular Input Output System (eMIOS) modules — Support a range of 16-bit Input Capture, Output Co mpare, Pulse Width Modulation and Quadrature Decode functions
• 10-bit Analog-to-Digital Converter (ADC) with a maximum conversion time of 1 s — Up to 20 internal channels — Up to 8 external channels
• Three Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with external devices
• QuadSPI serial flash memory controller — Supports single, dual and quad IO serial flash memory

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor6 — Interfaces to external, memory -mapped serial flash memories — Supports simultaneous addressing of 2 external se rial flashes to achieve up 80 MB/s read bandwidth

• RLE decoder supporting memory to memory decoding of RLE data in conjunction with eDMA
• Four local interconnect network (LINFlex) controller modules — Capable of autonomous message handling (master), autonomous header handling (slave mode), and UART support — Compliant with LIN protocol rev 2.1
• Three controller-area network (FlexCAN) modules — Compliant with the CAN protocol version 2.0 C — 64 configurable buffers — Programmable bit rate of up to 1 Mb/s
• Four Inter-Integrated Circuit (I 2C) internal bus controllers with master/slave bus interface
• Low-power loop controlled pierce crystal oscillat or supporting 4–16MHz external crystal or resonator
• Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous wake-up with 1 ms resolution with maximum timeout of 2 seconds — Support for real time counter (RTC) with clock source from external 32 KHz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour — RTC optionally clocked by fast 4–16 MHz external oscillator
• System timers: — Four-channel 32-bit System Timer Module (STM) — Eight-channel 32-bit Periodic Interrupt Timer (PIT) module (including ADC trigger) — Software Watchdog Timer (SWT)
• System Integration Unit Lite (SIUL) module to manage external interrupts, GPIO and pad control
• System Status and Configuration Module (SSCM) — Provides information for identification of the device, last boot mode, or debug status — Provides an entry point for the censorship password mechanism
• Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface, enabling access to all clock sources
• Clock Monitor Unit (CMU) — Monitors the integrity of the fast (4–16 MHz) exte rnal crystal oscillator and the primary FMPLL (FMPLL0) — Acts as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock
• Mode Entry Module (MC_ME) — Controls the device power mode, i.e., RUN, HALT, STOP, or STANDBY — Controls mode transition sequences — Manages the power control, voltage regulator, clock generation and clock management modules
• Power Control Unit (MC_PCU) to implement standby mode entry/exit and control connections to power domains
• Reset Generation Module (MC_RGM) to manage reset as sertion and release to the device at initial power-up
• Nexus Development Interface (NDI) per IEEE-ISTO 5001-2008 Class 3 standard with additional Class 4 features: — Watchpoint Triggering — Processor Overrun Control
• Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
• On-chip voltage regulator controller for regulating the 3.3–5 V supply voltage down to 1.2 V for core logic (requires external ballast transistor)
• Package: — 176 LQFP, 0.5 mm pitch, 24 mm  24 mm outline 1. See the device comparison table for package offerings for each device in the family.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 7 — 208 LQFP, 0.5 mm pitch, 28 mm  28 mm outline — 416 TEPBGA, 1mm ball pitch, 27 mm  27 mm outline

1.4 Feature details

1.4.1 Low-power operation

The PXD20 is designed for optimized low-power operation and dynamic power management of the CPU and peripherals. Power management features include software-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. There are three low-power modes:

• STANDBY
• S T O P
• HALT and five dynamic power modes — RUN[0..3] and DRUN. All low-power modes use clock gating to halt the clock for all or part of the device. STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode. The device can be awakened from STANDBY mode via from any of up to 23 I/O pins, a reset or from a periodic wake-up using a low power oscillator. If required, it is possible to enable the internal 16 MHz oscillator, the external 4–16 MHz oscillator and the external 32 KHz oscillator. In STANDBY mode the contents of the CPU, on-chip peripheral registers and potentially some of the volatile memory are lost. The two possible configurations in STANDBY mode are:
• The device retains 64 KB of the on-chip SRAM, bu t the content of the graphics SRAM is lost.
• The device retains 8 KB of the on-chip SRAM, but the content of the graphics SRAM is lost. STOP mode maintains power to the entire device allowing the retention of all on-chip registers and memory, and providing a faster recovery low power mode than the lowest-power STANDBY mode. There is no need to reconfigure the device before executing code. The clocks to the CPU and peripherals are halted and can be optionally stopped to the oscillator or PLL at the expense of a slower start-up time. STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by the internal periodic wake-up, if enabled. RUN modes are the main operating modes where the entire device can be powered and clocked and from which most processing activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The ability to configure and select different RUN modes enables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. The necessary peripherals, clock sources, clock speed and system clock prescalers can be independently configured for each of the four RUN modes of the device. HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing activity. In this mode the CPU system clocks are stopped but user-selected peripheral tasks can continue to run. It can be configured to provide more efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency. The system returns to RUN mode as soon as an event or interrupt is pending. Table 2 summarizes the operating modes of the PXD20.

• Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low power modes
• The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals when it is selected as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external oscillator delay
• The device includes an internal voltage regul ator that includes the following features:

Table 2. Operating mode summary1

1 Table Key:

external supply start-up time. IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG. All other wake-up times must be added to determine the total start-up time.

16 MHz IRC

32 KHz X OSC

3 Either 64 KB or 8 KB available. 4 64 KB of the RAM contents is retained, but not accessible in STANDBY mode. 5 8 KB of the RAM contents is retained, but not accessible in STANDBY mode. 6 Dependent on boot option after reset.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 9 — Regulates input to generate all internal supplies — Manages power gating — External ballast transistor for high power regulator — Low-Power and Ultra-Low-Power regulators support operation when in STOP and STANDBY modes, respectively, to minimize power consumption — Startup on-chip regulators in <350 µs for rapid exit of STOP and STANDBY modes — Low voltage detection on main supply and 1.2 V regulated supplies. 1.4.2 e200z4d core The e200z4d Power Architecture core provides the following features:

• Dual issue, 32-bit Power Architecture Book E compliant CPU
• Implements the VLE APU for reduced code footprint
• In-order execution and retirement
• Precise exception handling
• Branch processing unit — Dedicated branch address calculation adder — Branch target prefetching using 8-entry BTB
• Supports independent in struction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data BIUs.
• Load/store unit — 2 cycle load latency — Fully pipelined — Big and Little endian support — Misaligned access support
• 64-bit General Purpose Register file
• Dual AHB 2.v6 64-bit System buses
• Memory Management Unit (MMU) with 16-entry fully-associative TLB and multiple page size support
• 4 KB, 2/4-Way Set Associative Instruction Cache
• Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose Register file.
• Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations, using the 64-bit General Purpose Register file.
• Nexus Class 3 real-time Development Unit
• Dynamic power management of execution units, cache and MMU

1.4.3 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between seven master ports and eight slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows concurrent transactions to occur from any master port to any slave port but one of those transfers must be an instruction fetch from internal flash. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters having equal priority are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features:

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor10

• Seven master ports: — e200z4d core instruction port — e200z4d core complex load/store data port — eDMA controller —D C U — DCU-Lite —V I U — 2D Graphics Accelerator (GFX2D)
• Seven slave ports: — Platform Flash Controller (2 Ports) — Platform SRAM Controller — Graphics SRAM Controller (2 Ports) — QuadSPI serial flash Co ntroller and RLE Decoder — Peripheral Bridge
• 32-bit internal address bus, 64-bit internal data bus
• Programmable Arbitration Priority — Requesting masters can be treated with equal priority and will be granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access or a priority order can be assigned by software at application run time
• Temporary dynamic priori ty elevation of masters

1.4.4 Enhanced Direct Memory Access (eDMA)

The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:

• 16 channels support independent 8-, 16- or 32-bit single value or block transfers
• Supports variable sized qu eues and circular queues
• Source and destination addre ss registers are independently configured to post-increment or remain constant
• Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
• Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer
• DMA transfers possible between system memories, QuadSPI, RLE Decoder, SPIs, I2C, ADC, eMIOS and General Purpose I/Os (GPIOs)
• Programmable DMA Channel Mux allows assignment of a ny DMA source to any available DMA channel with up to a total of 64 potential request sources.

1.4.5 Interrupt Controller (INTC)

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 11 lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. Multiple processors can assert interrupt requests to each other through software settable interrupt requests. These same software settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software settable interrupt request to finish the servicing in a lower priority ISR. Therefore these software settable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following features:

• Unique 9-bit vector for each of the po ssible 128 separate interrupt sources
• Eight software triggerable interrupt sources
• 16 priority levels with fixed ha rdware arbitration within priority levels for each interrupt source
• Ability to modify the ISR or task priority. — Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources.
• External non maskable interrup t directly accessing the main CPU critical interrupt mechanism
• 32 external interrupts

1.4.6 QuadSPI serial flash memory controller

The QuadSPI module enables use of external serial flash memories supporting single, dual and quad modes of operation. It features the following:

• Maximum serial clock frequency 80 MHz
• Memory mapped read access for AHB crossbar switch masters
• Automatic serial flash read comm and generation by CPU, eDMA, DCU, or DCU-Lite read access on AHB bus
• Supports single, dual and quad serial flash read commands
• Simultaneous mode: — Supports concurrent read of two external serial flashes — The quad data streams from the two flashes can be reco mbined in the QuadSPI to achieve up to 80 MB/s read bandwidth with 80 MHz serial flash
• 1 6 64-bit buffer with speculative fetch and buffer flush mechanisms to maximize read bandwidth of serial flash
• DMA support
• All Serial Flash program, eras e, read and configuration commands available via IP bus interface.

1.4.7 System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The GPIO features the following:

• Up to four levels of internal pin multiplexing, allowing ex ceptional flexibility in the allocation of device functions for each package
• Centralized general purpose input output (GPIO) control
• All GPIO pins can be independently configured to support pull-up, pull down, or no pull
• Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
• All peripheral pins can be alternatively configured as bot h general purpose input or output pins except ADC channels which support alternative configuration as general purpose inputs

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor12

• Direct readback of the pin value supporte d on all digital output pins through the SIU
• Configurable digital input filter that can be applied to up to 24 general purpose input pins for noise elimination on external interrupts
• Register configuration protect ed against change with soft lock for temporary guard or hard lock to prevent modification until next reset.

1.4.8 On-chip flash memory with ECC

The PXD20 microcontroller has the following flash memory features:

• 2 MB of flash memory — Typical flash memory access time: 0 wa it-state for buffer hits, 3 wait-states for page buffer miss at 125 MHz — Two 4 × 128-bit page buffers with programmable prefetch control – One set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any access – One set of page buffers allocated to Display Co ntroller Units, Graphics Accelerator and the eDMA — 64-bit ECC with single-bit correction, double-bit detection for data integrity
• Small block flash arrangement to sup port features such as boot block, EEPROM Emulation, operating system block. —8 16 KB —2 64 KB —2 128 KB —6 256 KB
• Hardware managed Flash writes, erase and verify sequence
• Censorship protection scheme to prevent Flash content visibility

1.4.9 Static random-access memory (SRAM)

The PXD20 microcontroller has 64 KB general-purpose on-chip SRAM with the following features:

• Typical SRAM access time: 1 wait-st ate for reads and 32-bit writes
• 32-bit ECC with single-bit correction, double bit detection for data integrity
• Supports byte (8-bit), half word (16-bit), word (32-bit) a nd double-word (64-bit) writes for optimal use of memory
• User transparent ECC encoding and decodi ng for byte, half word, and word accesses
• Separate internal power domains applied to 56 KB and 8 KB SRAM blocks during STANDBY modes to retain contents during low power mode.

1.4.10 On-chip graphics SRAM

The PXD20 microcontroller has 1 MB on-chip graphics SRAM with the following features:

• Two crossbar slave ports: — One dedicated to the 2D Grap hics Accelerator (GFX2D) access — One dedicated to all other crossbar masters
• Usable as general purpose SRAM
• Supports byte (8-bit), half word (16-bit), word (32-bit) a nd double-word (64-bit) writes for optimal use of memory
• RAM controller with hardware RAM fill function su pporting all-zeroes or all-ones SRAM initialization
• Independent data buffers (one per AHB port) for maximum system performance — Optimized for burst tr ansfers (read + write) — Programmable read pr efetch capabilities

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 13

1.4.11 Memory Protection Unit (MPU)

The MPU features the following:

• Sixteen region descriptors for per master protection
• Start and end address defined with 32-byte granularity
• Overlapping regions supported
• Protection attributes can optionally include process ID
• Protection offered for 4 concurrent read ports
• Read and write attributes for all masters
• Execute and supervisor/user mode attributes for processor masters 1.4.12 2D graphics accelerator (GFX2D)
• Native vector graphics rendering — Compatible with OpenVG1.1 — Complete hardware OpenVG 1.1 rendering pipeline — Both geometry and pixel processing — Adaptive processing of B ezier curves and strokes
• 16-sample edge anti-aliasing — High image quality, font scalability, etc. —4  Rotated Grid Supersampling (RGSS) AA for Flash
• 3D perspective texturing, reflections, and shadowing
• Shading (linear or radial gradient)
• Separate 2D engine for BitB lt, fill and ROP operations
• Significant performance improvement when compared to software or 3D GPU-based OpenVG implementations

1.4.13 Display Control Unit (DCU3)

The DCU3 is a display controller designed to drive TFT LCD displays up to WVGA resolution using direct blit graphics and video. The DCU3 generates all the necessary signals required to drive the TFT LCD displays: up to 24-bit RGB data bus, Pixel Clock, Data Enable, Horizontal-Sync and Vertical-Sync. The flexible architecture of the DCU3 enables the display of OpenVG-rendered frame buffer content and direct blit rendered graphics simultaneously. An optional Timing Controller (TCON) and RSDS interface is available to directly drive the row and column drivers of a display panel. Internal memory resource of the device allows to easily handle complex graphics contents (pictures, icons, languages, fonts). The DCU3 supports 4-plane blending and 16 graphics layers. Control Descriptors (CDs) associated with each of the 16 layers enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. A layer may be constructed from graphic content of various resolutions including indexed colors of 1, 2, 4 and 8 bpp, direct colors of 16, 24 and 32 bpp, and a YUV 4:2:2 color space. The ability of the DCU3 to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of internal memory resources of the PXD20. A special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizing graphic memory usage. A hardware cursor can be managed independently of the layers at blending level increasing the efficient use of the internal DCU3 resources.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor14 To secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the TFT pads. The DCU3 features the following:

• Display color depth: up to 24 bpp
• Generation of all RGB an d control signals for TFT
• Four-plane blending
• Maximum number of Input Layers: 16 (fixed priority)
• Dynamic Look-Up-Table (Color and Gamma Look-Up)
• blending range: up to 256 levels
• Transparency Mode
• Gamma Correction
• Tiled mode on all the layers
• Hardware Cursor
• Supports YCrCb 4:2:2 input data format
• RLE decode inline supporting direct read of RLE compressed images from system memory
• Critical display content integrity monitoring for Functional Safety support
• Internal Direct Memory Access (DMA) module to transf er data from internal and / or external memory. The DCU3 also features a Parallel Data Interface (PDI) to receive external digital video or graphic content into the DCU3. The PDI input is directly injected into the DCU3 background plane FIFO. When the PDI is activated, all the DCU3 synchronization is extracted from the external video stream to guarantee the synchronization of the two video sources. The PDI can be used to:
• Connect a video camera output directly to the PDI
• Connect a secondary display driver as slave with a minimum of extra cost
• Connect a device gathering various Video sources
• Provide flexibility to allow the DCU to be us ed in slave mode (external synchronization) The PDI features the following:
• Supported color modes: — 8-bit mono — 8-bit color multiplexed — RGB565 — 16-bit/18-bit RAW color
• Supported synchronization modes: — embedded ITU-R BT.656-4 (RGB565 mode 2) — HSYNC, VSYNC — Data Enable
• Direct interface with DCU3 background plane FIFO
• Synchronization generation for the DCU3

1.4.14 Display Control Unit Lite (DCULite)

The DCULite is a display controller designed to enable the PXD20 to drive a second TFT LCD display up to XGA resolution using direct blit graphics and video. The DCULite includes all features of the DCU3, including the PDI with the following exceptions:

• Reduced from 4-plan e to 2-plane blending
• Reduced from 16 layers to 4 layers
• Reduced CLUT size

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 15

1.4.15 Timing controller (TCON) and RSDS interface

The TCON enables direct drive of the row and column drivers of display panels enabling emulation of TCON ICs used in display panels.

• Programmable Timing Generation unit featuring 12 waveform generators allowing high degree of flexibility in panel waveform generation
• Reduced Swing Differential Signaling (RSD S) interface for RGB data and pixel clock
• Conforms to “RSDS ‘Intra Panel’ Interface Spec ification” Rev. 1.0 (National Semiconductor)

1.4.16 RLE decoder

The RLE decoder is a crossbar slave sharing a slave port with the QuadSPI module. The platform eDMA is used to stream compressed image data into and extract decompressed data out of the RLE Decoder.

• Lossless decompression
• Pixel formats supported: 8bpp, 16bpp, 24bpp and 32bpp
• AHB mapped read and write registers in RLE_DEC to achieve higher throughput
• Programmable fill levels of read and wr ite buffers for initiating burst transfers
• Crop feature: Support for selectively reading out a part of decompressed image data taking complete compressed data for the full image as input.

1.4.17 DRAM controller

The DRAM controller is a multi-port DRAM controller supporting SDR, LPDDR1, DDR-1, and DDR-2 memories. The DRAM controller listens to the incoming requests to the seven buses in parallel and then sends commands to the DRAM from the highest priority bus at the current time The seven incoming 64-bit buses are:

• D C U 3
• D C U L i t e
• e200z4d core - instruction bus
• e200z4d core - data bus
• V I U 2
• G F X 2 D
• e D M A The DRAM controller features the following:
• Supports CAS latency of 2, 3, and 4 clock cycles.
• Master buses — 7 incoming master buses — Supports 16-byte and 32-byte bursts — Supports byte enables — Supports 4-bit priority signal for each bus
• Write buffer contains five 32-byte entries
• Supports 16-wide and 32-wide SDR, DDR1, DDR2 and LPDDR1 DRAM devices
• Controller supports one chip select, 8-bank DRAM system
• Supports dynamic on-die termination in the host device and in the DRAM.
• Supports memory sizes as small as 64Mbit

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor16

1.4.18 Video Input Unit (VIU2)

The VIU2 is a crossbar master module accepting an ITU656 compatible video input stream on a parallel interface, converting the pixel data to RGB or YUV format and transferring the video image to internal frame buffer memory or external DRAM if available.

• Supports 8-bit/10-bit ITU656 video input
• Output formats: — RGB888 — RGB565 — 8-bit monochrome — YCrCb 4:2:2
• Video downscaling
• Contrast and Brightness adjustment
• De-interlace for interlaced video image
• Internal DMA engine for data transfer to memory

1.4.19 Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once by Freescale. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are:

• Booting from internal flash memory
• Serial boot loading (A program is downloaded into RAM via CAN or LIN and then executed)
• Booting from external memory Additionally the BAM:
• Enables and manages the transition of th e MCU from reset to user code execution
• Configures device for serial bootload
• Enables multiple bootcode starting locations out of rese t through implementation of search for valid Reset Configuration Halfword
• Enables or disables software watchdog timer out of rese t through BAM read of Reset Configuration Halfword option bit

1.4.20 Enhanced Modular Inpu t/Output System (eMIOS)

This device has two eMIOS modules, each with 16 channels supporting a range of 16-bit Input Capture, Output Compare, Pulse Width Modulation, and Quadrature Decode functions.

• Selectable clock source from primary FMPLL, secondary FM PLL, external 4–16 MHz oscillator or 16 MHz Internal RC oscillator on a per module basis
• Timed I/O channels with 16-bit counter resolution
• Buffered updates
• Support for shifted PWM outputs to minimize occurrence of concurrent edges
• Edge aligned output pulse width modulation — Programmable pulse period and duty cycle — Supports 0% and 100% duty cycle — Shared or independent time bases
• Programmable phase shift between channels
• 4 channels of Quadrature Decode
• DMA transfer support

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 17

1.4.21 Analog-to-digital converter (ADC)

The ADC features the following:

• 10-bit A/D resolution
• 0–5 V or 0–3.3 V common mode conversion range
• Supports conversions speeds of up to 1 s
• 20 internal and 8 external channels support
• Up to 20 single-ended inputs channels — 10 channels configured as input only pins – 10-bit ± 2 counts accuracy (TUE) — 10 channels configured to have alternate function as general purpose input/output pins – 10-bit ± 3 counts accuracy (TUE)
• External multiplexer support to increase up to 27 channels — Automatic 1 × 8 multiplexer control — External multiplexer connected to a dedicated input channel — Shared register between the 8 external channels
• Result register available for every non-multiplexed channel
• Configurable Left or Right aligned result format
• Supports for one-shot, scan and injection conversion modes
• Injection mode status bit implemented on adjacent 16-bit register for each result — Supports Access to Result and injection status with single 32-bit read
• Independently enabling of function for channels: — Pre-sampling — Offset error cancellation —O f f s e t R e f r e s h
• Conversion Triggering support — Internal conversion triggering from periodic interrupt timer (PIT)
• Four configurable analog comparator channels offering range comparison with triggered alarm — Greater than — Less than — Out of range
• All unused analog pins available as general purpose input pins
• Selected unused analog pins available as general purpose pins
• Power Down mode
• Optional support for DMA transfer of results

1.4.22 Serial Peripheral Interface (SPI)

The SPI modules provide a synchronous serial interface for communication between the MCU and external devices. The SPI features:

• Full duplex, synchronous transfers
• Master or slave operation
• Programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Programmable transfer baud rate

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor18

• Programmable data frames from 4 to 16 bits
• Up to 3 chip select lines available, de pending on package and pin multiplexing, enable 8 external devices to be selected using external muxing from a single SPI
• Eight clock and transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for de-glitching
• FIFOs for buffering up to 4 transfer s on the transmit and receive side
• General purpose I/O functionality on pins when not used for SPI
• Queueing operation possible through use of eDMA

1.4.23 Controller Area Network (CAN) module

The PXD20 includes up to three controller area network (CAN) modules. The CAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. Each CAN module offers the following:

• Compliant with CAN protocol specification, Version 2.0B active
• 64 mailboxes, each configurable as transmit or receive — Mailboxes configurable while module remains synchronized to CAN bus
• Transmit features — Supports configuration of multiple mailboxes to form message queues of scalable depth — Arbitration scheme according to messa ge ID or message buffer number — Internal arbitration to guarantee no inner or outer priority inversion — Transmit abort procedure and notification
• Receive features — Individual programmable filters for each mailbox — 8 mailboxes configurable as a 6-entry receive FIFO — 8 programmable acceptance filters for receive FIFO
• Programmable clock source — System clock — Direct oscillator clock to avoid PLL jitter
• Listen only mode capabilities
• CAN Sampler — Can catch the 1st message sent on the CAN network while the MCU is stopped. This guarantees a clean startup of the system without missing messages on the CAN network. — The CAN sampler is connected to one of the CAN RX pins.

1.4.24 Serial communication interface module (UART)

The PXD20 devices include up to four UART modules and support for UART Master mode, UART Slave mode and UART mode. The modules are UART state machine compliant to the LIN 1.3 and 2.0 and 2.1 Specifications and handle UART frame transmission and reception without CPU intervention. The serial communication interface module offers the following:

• UART features: — Full-duplex operation — Standard non return-to-ze ro (NRZ) mark/space format

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 19 — Data buffers with 4-byte receive, 4-byte transmit — Configurable word length (8-bit or 9-bit words) — Error detection and flagging – Parity, noise and framing errors — Interrupt driven operation with 4 interrupts sources — Separate transmitter and r eceiver CPU interrupt sources — 16-bit programmable baud-rate m odulus counter and 16-bit fractional — 2 receiver wake-up methods

• LIN features: — Autonomous LIN frame handling — Message buffer to store identif ier and up to eight data bytes — Supports message length of up to 64 bytes — Detection and flagging of LIN errors — Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors — Classic or extended checksum calculation — Configurable Break duration of up to 36-bit times — Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional) — Diagnostic features – Loop back –S e l f T e s t – LIN bus stuck dominant detection — Interrupt driven operation with 16 interrupt sources — LIN slave mode features – Autonomous LIN header handling – Autonomous LIN response handling – Discarding of irrelevant LIN resp onses using up to 16 ID filters

1.4.25 Inter-Integrated Circuit (I 2C) controller modules

The PXD20 includes four I2C modules. Each module features the following:

• Two-wire bi-directional serial bus for on-board communications
• Compatibility with I 2C bus standard
• Multi-master operation
• Software-programmable for one of 256 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor20

1.4.26 System clocks and clock generation modules

The system clock on the PXD20 can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz oscillator. The source system clock frequency can be changed via an on-chip programmable clock divider ( 1 to 2). An additional programmable peripheral bus clock divider (ratios 1 to ) is also available. The PXD20 has two on-chip FMPLLs (primary and secondary). Each features the following:

• Input clock frequency from 4 MHz to 16 MHz
• Lock detect circuitry continuously monitors lock status
• Loss Of Clock (LOC) detection for reference and feedback clocks
• On-chip loop filter (for improved electromagnetic inte rference performance and reduction of number of external components required)
• Support for frequency ramping from PLL The primary FMPLL module is for use as a system clock source. The secondary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation. The main oscillator provides the following features:
• Input frequency range 4–16 MHz
• Square-wave input mode
• Oscillator input mode 3.3 V (5.0 V)
• Automatic level control
• Low power consumption
• PLL reference The PXD20 also includes the following oscillators:
• 32 KHz low power external oscillator for slow execution, low power, and RTC
• Dedicated internal 128 kHz RC oscillator for low power mode operation and self wake-up — ±10% accuracy across voltage and temp erature (after factory trimming) — Trimming registers to support improved accuracy with in-application calibration
• Dedicated 16 MHz internal RC oscillator — Used as default clock source out of reset — Provides a clock for rapid start-up from low power modes — Provides a back-up clock in the event of PLL or External Oscillator clock failure — Offers an independent clock source for the SWT — ±5% accuracy across voltage and temp erature (after factory trimming) — Trimming registers to support frequency adjustment with in-application calibration

1.4.27 Periodic interrupt timer (PIT)

The PIT features the following:

• Eight general purpose interrupt timers
• Two dedicated interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by system clock frequency

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 21

1.4.28 Real time counter (RTC)

The Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation

• Configurable resolution for different timeout periods — 1 s resolution for >1 hour period — 1 ms resolution for 2 second period
• Selectable clock sources from external 32 KHz crystal, external 4–16 MHz crystal, internal 128 kHz RC oscillator or divided internal 16 MHz RC oscillator

1.4.29 System timer module (STM)

The STM is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256).

• One 32-bit up counter with 8-bit prescaler
• Four 32-bit compare channels
• Independent interrupt source for each channel
• Counter can be stopped in debug mode

1.4.30 Software watchdog timer (SWT)

The SWT features the following:

• Watchdog supporting software activation or enabled out of Reset
• Supports normal or windowed mode
• Watchdog timer value writable once after reset
• Watchdog supports optional halting during low power modes
• Configurable response on timeout: reset, interrupt, or interrupt followed by reset
• Clock source: 128 kHz RC oscillator

1.4.31 Stepper motor controller (SMC)

The SMC module is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring a PWM signal. The motor controller has twelve PWM channels associated with two pins each (24 pins in total) driving up to 6 stepper motors. The SMC module includes the following features:

• 10/11-bit PWM counter
• 11-bit resolution with selectable PWM dithering function
• Left, right, or center aligned PWM
• Output slew rate control
• Output Short Circuit Detection This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive capabilities of the module.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor22

1.4.32 Stepper stall de tect (SSD) module

The SSD module provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ). The SSD module features the following:

• Programmable fu ll step state
• Programmable integration polarity
• Blanking (recirculation) state
• 16-bit integration accumulator register
• 16-bit modulus down counter with interrupt

1.4.33 Sound generator module (SGM)

The SGM features the following:

• 4-channel audio mixer
• Each channel capable of independent Tone generation or Wave playback
• Individual channel volume control (8-bit resolution)
• Tone Mode: — Programmable Tone frequency — Programmable amplitude envel ope: attack, duration and decay — Programmable number of tone pulses and inter-tone duration
• Wave Mode: — One FIFO per channel workin g in conjunction with eDMA — Supports standard audio sampling rates (4 kHz, 8 kHz , 11.025 kHz, 16 kHz, 22.050 kHz, 32 kHz, 44.100 kHz, 48 kHz) — Same sample rate applies to all channels — 8-bit, 12-bit, 16-bit input data formats — Programmable wave duration and inter-wave duration — Repeat mode with programmab le number of wave playbacks
• SGM Output: — 16-bit PWM channel — Integrated I 2S master interface for connection to external audio DAC 1.4.34 IEEE 1149.1 JTAG controller (JTAGC) JTAGC features the following:
• Backward compatible to standard JTAG IE EE 1149.1-2001 test access port (TAP) interface
• Support for boundary scan testing

1.4.35 Nexus Development Interface (NDI)

The Nexus 3 module is compliant with Class 3 of the IEEE-ISTO 5001-2008 standard, with additional Class 4 features available. The following features are implemented:

• Program Trace via Branch Trace Messagi ng (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus static code may be traced.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 23

• Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides the capability for the development tool to trace reads and/or writes to selected internal memory resources.
• Ownership Trace via Ownership Trace Messa ging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An Ownership Trace Message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow.
• Run-time access to embedded processor memory map via the JTAG port. This allows for enhanced download/upload capabilities.
• Watchpoint Messaging via the auxiliary pins
• Watchpoint Trigger enable of Pr ogram and/or Data Trace Messaging
• Data Acquisition Messaging (DQM) allows code to be instrumented to export customized information to the Nexus Auxiliary Output Port.
• Address Translation Messaging via program correlation messages displays updates to the TLB for use by the debugger in correlating virtual and physical address information
• Auxiliary interface for hi gher data input/output
• Registers for Program Trace, Data Trace, Ownership Trace and Watchpoint Trigger.
• All features controllable and c onfigurable via the JTAG port

2 Pinout and signal descriptions

Figure 2 shows the pinout for the 176-pin LQFP package. Figure 2. 176-pin LQFP pinout available only on this package.

Figure 3 shows the pinout for the 208-pin LQFP package. Figure 3. 208-pin LQFP pinout

2.4 Signal description

The following sections provide signal descriptions and related information about the signals’ functionality and configuration.

2.4.1 Pad configuratio n during reset phases

All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate.

• PB[5] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash memory.
• RESET pad is driven low. This is released only after PHASE2 reset completion.
• F a s t ( 4-16 MHz) external oscillator pads (EXTAL, XTAL) are tristate.
• The following pads are pull-up: —P B [ 6 ] —P H [ 0 ] —P H [ 1 ] —P H [ 3 ]

2.4.2 Voltage supply pins

V oltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization. Table 3. Voltage supply pin descriptions

176 LQFP 208 LQFP 416 TEPBGA

Table 3. Voltage supply pin descriptions (continued)

2.4.3 Pad types

• The port pin summary in Table 1;
• The pad type descriptions in Table 3-6; (PCR185–PCR281);
• The device data sheet.

2.4.4 System pins

The system pins are listed in Table 4. 1 Decoupling capacitors must be connected between these pins and the nearest VSS pin. 2 VDDA must be at the same voltage as VDDE_A. 3 This signal needs to be connected to ground during normal operation. Table 4. System pin descriptions oscillator amplifier circuit. oscillator amplifier circuit. oscillator amplifier circuit.

2.4.5 Nexus pins

On the 416 TEPBGA package option all Nexus pins are dedicated to Nexus only. 1 Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”). 2 Although this signal is not a supply for RSDS pads, it needs to be terminated in an external capacitor with a value of 47 pF . 3 VREG_BYPASS should be pulled down externally. Table 5. Nexus pins

2.4.6 DRAM interface

The DRAM interface pins are listed in Table 6. package, there are additional dedicated Nexus pins. Table 6. DRAM interface pin summary Table 5. Nexus pins (continued)

Table 6. DRAM interface pin summary (continued)

2.4.7 VIU muxing

streams to VIU2 and DCU3 (operating in narrow mode). Figure 5 explains the pin sharing arrangement. Figure 5. VIU2, DCU3, and DCULite pin sharing VIU input data selection is done based on select bit (bit 0) of Miscellaneous control register (0xC3FE0340).

• VIU pix data: VIU[9:0]
• Select bit 1’b0: PDI[7:0],HSYNC,VSYNC
• Select bit 1’b1: PDI[17:8] DDR_CLKB DRAM Clock bar Output DDR NA Output, None DDR_CK DRAM Clock Enable Output DDR PCR[222] Output, Pull Down DDR_CS DRAM Chip Select Output DDR PCR[223] Output, None MVREF DDR Reference Voltage Input — NA — J4 MVTT DRAM Termination Voltage Input — NA — F2,J2,M2,R2 1 These port pins are disabled and unpowered on packages where the DRAM interface is not bonded out. 2 Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).

Pinout and signal descriptions PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 35

2.4.8 SGM muxing

The SGM shares pins between the PWM output signals and the I2S bus signals as shown in the “Port pin summary” table. When the PWM function is enabled in the SGM (SGMCTL[PWME]) the PWM (PWMO, PWMOA) signals are available. When the PWM function is disabled the I2S bus signals (I2S_DO, I2S_SCK) are available.

2.4.9 RSDS special function muxing

Ports PA[0:15], PG[0:7], PG[11] and PM[2] have the RSDS signalling option as a special function. The SIUL allocates pad control registers to these functions (PCR[270:282]), but because these pads share a common pin with the normal GPIO pins they do not operate in the same way as the normal GPIO ports. PG[11] in particular has a special configuration separate from the other pads. The special-function pads are output-only, and the associated PCR[OBE] bit is controlled by the TCON_CTRL1 register (TCON_BYPASS and RSDS_MODE bits). However, the alternate function selection is taken from the associated normal GPIO pad. This allows selection of the DCU3 function as the alternate function of the pad and then the TCON module to select if the output style is TCON/RSDS or digital RGB format. Therefore, when the TCON bypass is active (bypass disabled with or without RSDS active), it is important not to configure the normal GPIO ports for output operation with a non-DCU3 alternate function on ports PA[0:15] and PG[0:7]. For PG[11], the PCR[282] OBE bit is fully controlled by the TCON module and will become an output whenever the DCU3 alternate option is selected. Therefore, only select the DCU3 function on this pin when ready to configure it as a clock for a TFT panel.

2.4.10 Functional ports

• S — Slow (pad_ssr, pad_ssr_hv)
• M — Medium (pad_msr, pad_msr_hv)
• F — Fast (pad_fc)
• J — Input/output with analog f eatures (pad_tgate, pad_tgate_hv)
• Analog — Input only with analog features (pad_ae, pad_ae_hv)
• SMD — Stepper Motor Detector
• DDR — DDR pads
• RSDS — RSDS pads

Table 7. Port pin summary

Table 7. Port pin summary (continued)

11 T 4

22 T 2

33 T 1

6 PCR[100] Option 0

6 PCR[102] Option 0

44 U 4

55 U 3

88 U 2

99 U 1

1 Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIUL module. the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”. their functionality. ADC functions are enabled using the PCR[APC] bit; other functions are enabled by enabling the respective module. of the PXD20 Microcontroller Reference Manual for details. 4 See the “Pad types” section for an explanation of the letters in this column. 5 Reset configuration is given as I/O direction and pull, e.g., “Input, pullup”. 6 Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when needed.

3 System design information

3.1 Power-up sequencing

1. Generic IO supplies or noise-free supplies, consisting of:

Figure 6. Power-up sequencing

Figure 7. Power-down sequencing

1. All 3.3V supplies (VDDE_B and VDD33_DR) should be ramped up first, and then the rest of the I/O supplies should

be ramped up (VDDA, VDDE_A, VDDM, and VDD_DR).

1. VDDR, the regulator input supply, should be the last supply to ramp up; all supplies can be ramped up together as long

the same level, they can be ramped up together as well.

1. LV supply (VDD12). If Vreg is in bypass mode and the core supply (1.2 V) is supplied externally, then this should be

For DDR, the 3.3 V supply (VDD33_DR) should come before VDD_DR.

Electrical characteristics

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor62

4 Electrical characteristics

4.1 Introduction

This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by internal pull up and pull down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column.

4.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 8 are used and the parameters are tagged accordingly in the tables where appropriate. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. Table 8. Parameter classifications P Those parameters are guaranteed during production testing on each individual device. relevant sample size across process variations. D Those parameters are derived mainly from simulations.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 63

4.3 Absolute maximum ratings

Table 9. Absolute maximum ratings

1 SR D Voltage on VDDE_B (I/O supply) pin with

1 SR D Voltage on VDDM (stepper motor supply) pin

VSSM, unless otherwise noted.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor64 NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V IN >V DD or VIN <V SS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values.

4.4 Recommended operating conditions

Table 10. Recommended operating conditions (3.3 V)

1 SR P Voltage on VDDA pin (ADC reference) with re-

2 SR P Voltage on VDDR pin (regulator supply) with

5 VDDmax

9 SR P Voltage on VDDE_A (I/O supply) pin with

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 65 1 100 nF capacitance needs to be provided between VDDA/VSSA pair. 2 10 F capacitance must be connected between VDDR and VSS12 because of a sharp surge due to external ballast. 3 VDD12 cannot be used to drive any external component. 4 Each VDD12/VSS12 supply pair should have a 10F capacitor. Absolute combined maximum capacitance is 40F . Preferably, all the VDD12 supply pads should be shorted and then connected to a 4  10 F capacitance. This is to ensure the ESR of external capacitance does not exceed 0.2 . A 100 nF capacitor must be placed close to the pin. 5 VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDD_DR, and VDDM. 6 100 nF capacitance needs to be provided between each VDD/VSS pair. VDDmin value for is 3 V for VDDE_A & VDDM as well as for VDDE_B, while it is 1.62 V for VDD_DR. VDD max value is 3.6 V for VDDE_A & VDDM as well as for VDDE_B & VDD_DR. 7 Full electrical specification cannot be guaranteed when voltage drops below 3.0V. In particular, ADC electrical characteristics and I/O’s DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL device is reset. 8 VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSS, and VSSM unless otherwise noted. 9 VDDE_A should not be less than VDDA. 10 Guaranteed by device validation. Table 11. Recommended operating conditions (5.0 V)

3 SR P Voltage on VDDR pin (regulator supply) with

6 VDDmax

10 SR P Voltage on VDDE_B (I/O supply) pin with

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor66

4.5 Thermal characteristics

VDDM SR P Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) +4.5 +5.5 V D2.30 VDD_DR 11 P Voltage on V DD_DR with respect to VSS +1.62 +3.6 V D2.31 VSS_DR D Voltage on V SSRSDS with respect to VSS +1.62 +3.6 V D2.32 VRSDS P Voltage on V DD_DR with respect to VSS +3.0 +3.6 V D2.33 TVDD SR D V DD slope to ensure correct power up12 12 V/ms D2.34 TA SR P Ambient temperature under bias –40 105 °C D2.35 –40 105 TJ SR D Junction temperature under bias –40 140 D2.36 1 100 nF capacitance needs to be provided between VDDA/VSSA pair. 2 Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical characteristics may not be guaranteed below 4.5 V during the voltage drop sequence. 3 10 F capacitance must be connected between VDDR and VSS12. It is recommended that this cap should be placed, as close as possible to the DUT pin on board. 4 VDD12 cannot be used to drive any external component. 5 Each VDD12/VSS12 supply pair should have a 10F capacitor. Absolute combined maximum capacitance is 40 F . Preferably, all the VDD12 supply pads should be shorted and then connected to a 410 F capacitance. This is to ensure the ESR of external capacitance does not exceed 0.2 . A 100 nF capacitor must be placed close to the pin. 6 VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_DR, VDDMA, VDDMB and VDDMC. VDDmin value for is 4.5 V for VDDE_A & VDDM, 3 V VDDE_B, while it is 1.62 V for VDD_DR. VDD max value is 5.5 V for VDDE_A & VDDM and 3.6 V for VDDE_B & VDD_DR. 7 100 nF capacitance needs to be provided between each VDD/VSS pair. 8 VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_A, VSSE_E, VSSMA, VSSMB and VSSMC) unless otherwise noted. 9 VDDE_A should not be less than VDDA. 10 VDDE_B cannot go beyond 3.6V under any operating condition. 11 VDD_DR can be 1.8, 2.5 and 3.3V (typical) based on type of SDR memory.

12 Guaranteed by device validation

Table 12. Thermal characteristics for 176-pin LQFP1 Table 11. Recommended operating conditions (5.0 V) (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 67 JT CC D Junction to Package Top Natural Convec- tion5 2° C / W D 3 . 7 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 13. Thermal characteristics for 208-pin LQFP1 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. specification for this package. for the case temperature. Reported value includes the thermal resistance of the interface layer. Table 14. Thermal characteristics for 416-pin TEPBGA1 Table 12. Thermal characteristics for 176-pin LQFP1 (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor68

4.5.1 General notes for specification s at maximum junction temperature

An estimate of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA * PD) Eqn. 1 where: TA= ambient temperature for the package (oC) RJA= junction to ambient thermal resistance (oC/W) PD= power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:

• Construction of the application board (number of planes)
• Effective size of the boar d which cools the component
• Quality of the thermal and elect rical connections to the planes
• Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. JT CC D Junction to Package Top Natural Convec- tion5 — 2 °C/W D3.21 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 14. Thermal characteristics for 416-pin TEPBGA1 (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 69 At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB * PD) Eqn. 2 where: TB= board temperature for the package perimeter (oC) RJB= junction-to-board thermal resistance (oC/W) per JESD51-8S PD= power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA Eqn. 3 where: RJA = junction to ambient thermal resistance (oC/W) RJC= junction to case thermal resistance (oC/W) RCA= case to ambient thermal resistance (oC/W) RJC s device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) Eqn. 4 where: TT= thermocouple temperature on top of the package (oC) JT= thermal characterization parameter (oC/W) PD= power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References:

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor70 Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org.

4.6 EMI (electromagnetic interference) characteristics

4.7 Power management

4.7.1 Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN (BCP68 or NJD2873) ballast to be connected as shown in Figure 8 s well as an external capacitance (CREG) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 15 nH. Table 15. EMI testing specifications12 1 The reported emission level is the value of the maximum emission, rounded up to the next whole number. 2 IEC Level Maximum:, L is less than or equal to 24 dBµV, K is less than or equal to 30 dBµV.

50 MHz

50 MHz –

150 MHz

150 MHz –

500 MHz

500 MHz –

1000 MHz

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 71 For the PXD20 microcontroller, 100 nF should be placed between each VDD12/VSS12 supply pair and also between the VDDPLL/VSSPLL pair. Additionally, 10 F should be placed between the VDDR pin and the adjacent VSS pin. Figure 8. External NPN ballast connections Table 16. Voltage regulator electrical characteristics

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor72

4.7.2 Voltage monitor electrical characteristics

The device implements a Power On Reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the VDD and the VDD12 voltage while device is supplied:

• POR monitors V DD during the power-up phase to ensure device is maintained in a safe reset state
• LVDHV3 monitors V DD to ensure device reset below minimum functional supply
• LVDHV5 monitors V DD when application uses device in the 5.0V ±10% range
• LVDLVCOR monitors power domain No. 1
• LVDLVBKP monitors power domain No. 0 1 Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted the Power OK signal.

Table 17. Low-power voltage regulator electrical characteristics Table 18. Ultra low-power voltage regulator electrical characteristics

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 73

4.7.3 Low voltage domain power consumption

Table 20 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Table 19. Low voltage monitor electrical characteristics 2 All values need to be confirmed during device validation. Table 20. DC electrical characteristics

2 CC D RUN mode maximum

4 CC P RUN mode typical

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor74 IDDSTDBY2 CC D STANDBY2 mode current8 (64K SRAM on) SXOSC (32 KHz9) ON and RTC running TA = –40oC— 4 7 0 — A DT A = 0oC— 4 8 0 — PT A = 25oC — 481 490 DT A = 55oC— 5 2 5— DT A = 85oC— 6 5 0— PT A = 105oC — 870 910 CC D SXOSC (32 KHz) and RTC OFF T A = –40oC6 3 — A DT A = 0oC8 5 — PT A = 25oC 93 100 DT A = 55oC9 5 — DT A = 85oC1 9 0 — PT A = 105oC 390 430 IDDSTDBY1 CC D STANDBY1 mode current (8K SRAM on)10 SXOSC (32KHz) ON and RTC running TA = –40oC— 4 1 5 — A DT A = 0oC— 4 2 2 — PT A = 25oC — 426 430 DT A = 55oC— 5 7 5— DT A = 85oC— 6 8 0— PT A = 105oC — 810 915 CC D SXOSC (32 KHz) and RTC OFF T A = –40oC2 0 — A DT A = 0oC2 2 — PT A = 25oC2 9 4 5 DT A = 55oC4 7 — DT A = 85oC1 1 8 — PT A = 105oC 236 310 1 VDD = 3.0 V to 5.5 V, TA = –40 to 105 °C, unless otherwise specified. 2 IDDMAX is composed of the current consumption on all supplies (VDD12, VDDE_A, VDDE_B, VDDA, VDDR, VDDM, VDDPLL, and VDD_DR). It does not include current consumption linked to I/Os toggling which is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application; switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 3 HIgher current may be sinked by device during power-up and standby exit. Please refer to inrush current in Table 21. 4 RUN current measured with typical application and accesses on both flash and RAM. 5 Data and Code Flash in Normal Power. Code fetched from RAM: DCUs running with 20MHz pixel clock, QuadSPI fetching data at 80MHz, GPU accessing internal SRAM and external DRAM, DMA, RLE, and VIU active, Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/ADC/SMD/SSD/SGM) and running at max frequency, periodic SW/WDG timer reset enabled. Table 20. DC electrical characteristics (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 75

4.8 DC electrical specifications

4.8.1 DC specification for CMOS 090LP2 library @ VDDE = 3.3 V NOTE These pad specifications are applicable for pads in the Digital segment Only. See the “GPIO power bank supplies and functionality” table in the “V oltage Regulators and Power Supplies” chapter of the reference manual for details. 6 Flash in Low Power. RCOSC 128 kHz and RCOSC 16 MHz ON. 10 MHz XTAL clock. FlexCAN: instances: 0, 1ON (clocked but no reception or transmission), LINFLEX: instances 0, 1, 2 ON (clocked but no reception or transmission). eMIOS: instance: 0, 1 ON - 16 channels on with PWM20K Hz. DSPI: instance: 0 (clocked but no communication). DCUs, TCON, VIU, GPU clock gated, RTC/API ON.PIT ON. STM ON. ADC ON but not converting. 7 No clock, RC 16MHz off, RCI 128 kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 8 ULPreg ON, HP/LPVreg off, 64 KB RAM on, device configured for minimum consumption, all possible modules switched off. 9 32 KHz oscillator operates at 32,768 Hz. 10 ULPreg ON, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off. Table 21. DC electrical specifications

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor76 Vol SR P Output low voltage — — 0.2 Vdde V D9.13 Voh_pci SR P PCI output high voltage — 0.9 Vdde — V D9.14 Vol_pci SR P PCI output low voltage — — 0.1 Vdde V D9.15 Vol_fod_h SR P Fast open-drain output low voltage Iol_fod_h = 10 mA — 0.2 Vdd33 D9.16 Table 22. Drive current, VDDE=3.3 V (±10%) 1 Ioh is defined as the current sourced by the pad to drive the output to Voh. 2 Iol is defined as the current sunk by the pad to drive the output to Vol. Table 23. Supply leakage Table 21. DC electrical specifications (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 77 4.8.2 DC specification for CMOS 090LP2fg library @ VDDE = 5.0 V NOTE These pad specifications are applicable for pads in the Analog segment Only. See the “GPIO power bank supplies and functionality” table in the “V oltage Regulators and Power Supplies” chapter of the reference manual for details. Table 24. DC electrical specifications

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor78 Rtgate SR D Pad_tgate_hv input resistance — 250 800  D9.39 pupd_rm SR D pad_pupd_hv resistance mismatch —— 5 % D 9 . 4 0 pupd_leak SR D pad_pupd_hv leakage current — 0.1 75000 pA D9.41 pupd200k SR D pad_pupd_hv 200 k  resistance — 130 280 k  D9.42 pupd100k SR D pad_pupd_hv 100 k  resistance — 65 140 k  D9.43 pupd5k SR D pad_pupd_hv 5 k  resistance —1 . 4 5 . 2 k  D9.44 Table 25. DC electrical specifications Table 24. DC electrical specifications (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 79 Ioh_msr SR pad_msr_hv Ioh — 5.4 21 mA D9.59 Iol_msr SR pad_msr_hv Iol — 8.1 38.6 mA D9.60 Ioh_ssr SR pad_ssr_hv Ioh — 2.8 11.2 mA D9.61 Iol_ssr SR pad_ssr_hv Iol — 4.2 20.6 mA D9.62 Ioh_multv_h s SR pad_multv_hv Ioh High swing mode — TBD mA D9.63 Iol_multv SR pad_multv_hv Iol High/low swing mode — TBD mA D9.64 Rtgate SR Pad_tgate_hv input resistance — 325 1250  D9.65 pupd_rm SR pad_pupd_hv resistance mismatch —— 5 % D 9 . 6 6 pupd_leak SR pad_pupd_hv leakage current — 0.1 75000 pA D9.67 pupd200k SR pad_pupd_hv 200 k  resistance —1 3 0 2 8 0 k  D9.68 pupd100k SR pad_pupd_hv 100 k  resistance —6 5 1 4 0 k  D9.69 pupd5k SR pad_pupd_hv 5 k  resistance —1 . 7 7 . 7 k  D9.70 Table 26. Supply leakage Table 25. DC electrical specifications (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor80 pad_vdde_hv 0 0 — — 0 0 pad_vddint3v_hv 0 0 — — 0 0 Table 27. AVG IDDE specifications 1 All loads are lumped loads. 2 Average current is for pad configured as output only. Use pad_i current for input. Table 26. Supply leakage (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 81 4.8.3 DC specification for CMOS 090_ddr library @ VDDE = 3.3 V 4.8.4 DC specification for CMOS 090_ddr library @ VDDE = 2.5 V Table 28. DC electrical specifications at 3.3 V VDDE Table 29. Output drive current @ VDDE = 3.3 V (±10%) Table 30. DC electrical specifications at 2.5 V VDDE

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor82 4.8.5 DC specification for CMOS 090_ddr library @ VDDE = 1.8 V Vih SR P Input high voltage Vref + 0.15 — V D9.85 Vil SR P Input low voltage — Vref – 0.15 V D9.86 Voh SR P Output high voltage Vtt + 0.81 — V D9.87 Vol SR P Output low voltage — Vtt – 0.81 V D9.88 Table 31. Output drive current @ VDDE = 2.5 V (±200mV) Table 32. DC electrical specifications for 1.8 V VDDE Table 33. Output drive current @ VDDE = 1.8 V (±100mV) Table 30. DC electrical specifications at 2.5 V VDDE (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 83 pad_st_dq P 000 –3.57 3.57 6MDDR 001 –7.84 7.84 010 –5.36 5.36 110 –13.4 13.4 pad_st_clk P 000 –3.57 3.57 6MDDR 001 –7.84 7.84 010 –5.36 5.36 110 –13.4 13.4 Table 34. ODT DC electrical characteristics Table 35. core_v_det_odt and core_v_det33_odt specifications Table 33. Output drive current @ VDDE = 1.8 V (±100mV) (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor84

4.9 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin. Figure 9. Start-up reset requirements Figure 10. Noise filtering on reset signal

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 85 Table 36. Reset electrical characteristics 2 All values need to be confirmed during device validation.

3 Data based on characterization results, not tested in production

4 Guaranteed by design simulation. 6 CL calculation should include device and package capacitance (CPKG < 5pF).

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor86

4.10 Fast external crystal o scillator (4–16 MHz) electrical

This device implements the fast external oscillator (FXOSC) using a low power Loop Controlled Pierce Oscillator (LCP) configuration. Table 37. Fast external crystal oscillator electrical characteristics

2 Maximum value is for extreme cases using high Q, low frequency crystals

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 87

4.11 Slow external crystal oscillator (32 KHz) electrical characteristics

The device provides a slow external oscillator/resonator driver (SXOSC). The 32 KHz oscillator operates at 32,768 Hz. Figure 11. Crystal oscillator and resonator connection scheme PC[14]/PC[15] must not be directly used to drive external circuits. Figure 12. Slow external crystal oscillator electrical characteristics

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor88

4.12 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the fast external oscillator driver. Table 38. Slow external crystal oscillator electrical characteristics 2 All values need to be confirmed during device validation.

3 Granted by device validation

Table 39. FMPLL electrical characteristics 1 VDDPLL = 1.2 V ±10%, TA = –40 to 105 °C, unless otherwise specified. 2 All values need to be confirmed during device validation. mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.

15.625 MHz @ 10 MHz resonator

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 89

4.13 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a fast internal RC oscillator (FIRC). This is used as the default clock at the power-up of the device.

4.14 Slow internal RC oscillator (128 kHz) electrical characteristics

The device provides a slow internal RC oscillator (SIRC). This can be used as the reference clock for the RTC module. 4 Data based on device simulation. 5 2x sys clock required for generation of DDR timing. 6 fCPU of 125 MHz can be achieved only at temperatures up to 105 °C with a maximum FM depth of 2%.

7 Data based on characterization results, not tested in production

Table 40. Fast internal oscillator electrical characteristics 2 All values need to be confirmed during device validation.

3 Guaranteed by device simulation, not tested in production

4 Guaranteed by device characterization, not tested in production

Table 41. Slow internal RC oscillator electrical characteristics 2 All values need to be confirmed during device validation.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor90

4.15 Flash memory electrical characteristics

Table 42. Program and erase specifications pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. Table 43. Flash module life

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 91

4.16 ADC parameters

The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter. Figure 13. ADC characteristics and error definitions

4.16.1 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is considered. charge during the sampling phase, when the analog signal source is a high-impedance source.

1 LSB (ideal)

1 LSB ideal = VDDA / 1024

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor92 A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc × CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 5: Eqn. 5 Equation 5 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 14. Input equivalent circuit (precise channels)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor94 Eqn. 7 The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 8: Eqn. 8

• A second charge transfer involves also C F (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Eqn. 9 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 10 Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 11 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 11 The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.

Figure 17. Spectral representation of input signal

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 95 Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 12 between the ideal and real sampled voltage on CS: Eqn. 12 From this formula, in the worst case (when VA is maximum, that is for instance 5V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 13

4.16.2 ADC electrical characteristics

Table 44. ADC electrical characteristics

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor96 CS CC5 D ADC input sampling capacitance —— — 3 pF D15.8 CP1 CC5 D ADC input pin capacitance 1 —— — 3 pF D15.9 CP2 CC5 D ADC input pin capacitance 2 —— — 1 pF D15.10 CP3 CC5 D ADC input pin capacitance 3 —— — 1 pF D15.11 RSW1 CC5 D Internal resistance of analog source —— — 3 k D15.12 RSW2 CC5 D Internal resistance of analog source —— — 2 k D15.13 RAD CC5 D Internal resistance of analog source —— — 0.1 k D15.14 IINJ SR T Input current Injection Current injection on one ADC input, different from the converted one –10 — 10 mA D15.15 INL CC5 P Integral Non Linearity No overload –1.5 — 1.5 LSB D15.16 DNL CC5 P Differential Non Linearity No overload –1.0 — 1.0 LSB D15.17 OFS CC5 T Offset error After offset cancellation — 0.5 — LSB D15.18 GNE CC5 T Gain error — — 0.6 — LSB D15.19 TUEX CC T Total Unadjusted Error for extended channel No overload –3 — 3 LSB D15.21 TUEP CC5 T Total Unadjusted Error for precise channels, input only pins No overload –2 — 2 LSB D15.22 overload conditions on adjacent channel LSB TUEX CC5 T Total Unadjusted Error for extended channel, No overload –3 — 3 LSB D15.23 overload conditions on adjacent channel —— — LSB 1 VDDA = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to +105 °C, unless otherwise specified. 2 All values need to be confirmed during device validation. 3 Analog and digital VSS must be common (to be tied together externally). 4 VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF

5 Guaranteed by design

6 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. 7 This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result’s register with the conversion result. Table 44. ADC electrical characteristics (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 97

4.17 AC specifications

4.17.1 AC specification for CMOS090LP2 library @ VDDE = 3.3 V Table 45. Functional pad type AC specifications 1 L>H signifies low-to-high propagation delay and H>L signifies high-to-low propagation delay. 2 Can be used on the tester.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor98 4.17.2 AC specification for CMOS090LP2fg library @ VDDE = 5.0 V 4.17.3 AC specification for CMOS090LP2fg library @ VDDE = 3.3 V Table 46. Functional pad type AC specifications 1 L>H signifies low-to-high propagation delay and H>L signifies high-to-low propagation delay. 2 For input buffer timing, look at pad_i_hv. 3 Can be used on the tester. 4 This drive select value is not supported. If selected, it will be approximately equal to 11. Table 47. Functional pad AC type specifications

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 99 4.17.4 Pad AC specifications (3.3 V, PAD3V5V = 1) pad_ssr_hv 9.2 / 6.9 27 / 28 5.5 / 4.1 15 / 17 50 11 30 / 23 81 / 87 21 / 16 57 / 63 200 N/A 10 31 / 31 80 / 90 15.4 / 15.4 38 / 42 50 01 58 / 52 144 / 155 32 / 26 82 / 85 200 162 / 168 415 / 415 80 / 82 190 / 190 50 00 216 / 205 533 / 540 106 / 95 250 / 250 200 Table 48. Pad AC specifications (3.3 V, PAD3V5V = 1)1

1 Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition

2 Slope at rising/falling edge

3 F a s t 1 — 6 1 — 4 ——7 2 3 —4 0 2 5

Table 47. Functional pad AC type specifications (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor100 4.17.5 AC specification for CMOS 090_ddr library @ VDDE = 3.3 V 4.17.6 AC specification for CMOS 090_ddr library @ VDDE = 2.5 V Table 49. AC specifications at 3.3 V VDDE Table 50. AC specifications at 2.5 V VDDE

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 101 4.17.7 AC specification for CMOS 090_ddr library @ VDDE = 1.8 V Table 51. AC electrical specifications at 1.8 V VDD

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor102

4.18 AC timing

4.18.1 IEEE 1149.1 interface timing Figure 18. JTAG test clock input timing Table 52. JTAG interface timing1 and CL = 50 pF with SRC = 0b01. 2 Parameter values guaranteed by design.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 103 Figure 19. JTAG test access port timing

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor104 Figure 20. JTAG boundary scan timing

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 105

4.18.2 Nexus debug interface

Figure 21. Nexus output timing Table 53. Nexus debug port timing1 CL = 50 pF (Cl = 30 pF on MCKO), with SRC = 0b10 for MCKO and 0b11 for others. 2 Parameter values guaranteed by design. 3 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 4 The system clock frequency needs to be three times faster that the TCK frequency. for #2, 3, and 4 above, are 0.3 of tMCYC for shared Nexus ports.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor106 Figure 22. Nexus TCK timing Figure 23. Nexus TDI, TMS, TDO timing

4.18.3 Interface to TFT LCD panels (DCU3 and DCULite)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 107

• PCLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, PCLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
• DE acts like an output enable signal to the LCD pa nel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.

Figure 24. TFT LCD interface timing overview1

4.18.3.1 Interface to TFT LCD panels—pixel level timings

VSYNC signals via the SYN_POL register, whether active-high or active-low. The default is active-high. The DE signal is always active-high. programmed via the DCU Clock Confide Register (DCCR) in the system clock module. parameters are programmed via the VSYN_PARA register.

1. In Figure 24, the “LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7].

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor108 Figure 25. Horizontal sync timing Table 54. LCD interface timing parameters—horizontal and vertical 1 Parameter values guaranteed by design.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 109 Figure 26. Vertical sync pulse

4.18.3.2 Interface to TFT LCD panels—access level

Table 55. LCD interfac e timing parameters 1,2,3,4—Access Level 2 Intrabit skew is less than 2 ns. 3 Load CL = 50 pf for frequency up to 20 MHz. 4 Load CL = 25 pf for display freq from 20 to 32 MHz. Num Symbol C Characteristic Min. 5 Parameter values guaranteed by design.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor110 Figure 27. LCD Interface timing parameters—access level

4.18.4 RSDS interface to TFT LCD panels

Table 56. RSDS electrical characteristics 1 VDDA = 3.3 V ± 10% TA = –40 to 105 °C, unless otherwise specified. 2 All values need to be confirmed during device validation.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 111 Figure 28. TCON/RSDS timing diagram

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor112

4.18.5 DRAM interface

DDR Interface specification from ‘MCD — 32 Bit Automotiv e MCU — CMOS090LP2’ I/O Pad Specification Revision 1.5 — May14th 2008. This device supports SDR, DDR1, DDR2 half and full strengths, as well as LPDDR half and full speeds. Table 57 shows the SRE settings for the different modes. NOTE: The specifications given in Table 58 are preliminary. Table 57. Pad mode configurations

100 Not supported

101 Not supported

111 SDR

Table 58. LPDDR, DDR, and DDR2 (DDR2-250) SDRAM timing specifications1 2 3 1 At recommended operating conditions with VDDE_DR of ±5%. 2 VDDE_DR value is 1.8 for DDR2 mode, 2.5 V for DDR1 mode, and 1.8 V for LPDDR mode.

1 F CC Frequency of Operation (Clock Period) N/A 125 MHz

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 113 4.18.5.1 2.5V DDR1 The SSTL_2 differential input switch point is at Vref = 0.50 × Vddet. Note that the JEDEC SSTL_2 specifications (JESD8-9B) for an SSTL interface for class II operation supersedes any specification in this document. The SSTL_2 Class II output with ipp_sre[2:0] set to enabling SSTL_2 2.5V DDR1 mode, at the destination, have a rise/fall time (10–90%) between 1 ns and 2 ns over process, voltage, and temperature driving a 70 ohm transmission line with 0.167 ns td terminated at the destination with 70 ohms to Vtt (0.5 × vddet) with 4.0 pf, representing the DDR input capacitance. 4 Measured with clock pin loaded with differential 100 ohm termination resistor. 5 All transitions measured at mid-supply (VDDE_DR/2). 6 Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDDE_DR/2. 7 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 8 Window position is given for tDQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly. Table 59. SSTL_2 Class II 2.5V DDR DC specifications

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor114 Figure 29. SSTL_2 Class II test load The SSTL_18 differential input switch point is at Vref = 0.50 × Vddet. specification in this document. Table 60. SSTL_18 Class II 1.8V DDR2 DC specifications

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor116

4.18.6 Video Input Unit timing

Figure 31. VIU2 timing diagram

4.18.7 External Interrupt (IRQ) and No n-Maskable Interrupt (NMI) Timing

Figure 32. IRQ and NMI timing Table 62. VIU2 timing parameters Table 63. IRQ and NMI timing Num Symbol C Characteristic Min. 1 Parameter values guaranteed by design. 2 Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 117 4.18.8 eMIOS timing

4.18.9 FlexCAN timing

The CAN functions are available as TX pins at normal I/O pads and as RX pins at the always on domain. There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.

4.18.10 Deserial Serial Peripheral Interface (DSPI)

Table 64. eMIOS timing1 Num Symbol C Characteristic Min. 2 There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad delays. Refer to the pad specification section for the details. 3 Parameter values guaranteed by design. Table 65. FlexCAN timing1 Num Symbol C Characteristic Min. value Max. 2 Parameter values guaranteed by design. Table 66. DSPI timing1

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor118 7t SUI CC2 D Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) ns ns ns ns A11.7 8t HI CC2 D Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) ns ns ns ns A11.8 SUO CC2 D Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA=0) Master (MTFE = 1, CPHA=1) ns ns ns ns A11.9 10 t HO CC2 D Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) –15 5.5 –15 ns ns ns ns A11.10 1 DSPI timing specified at VDDE_x = 3.0 V to 3.6 V, TA = –40 to 105 °C, and CL = 50 pF with SRC = 0b10. 2 Parameter values guaranteed by design. 3 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. 4 The actual minimum SCK Cycle Time is limited by pad performance. 5 Maximum clock possible is System clock/2. 6 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 & CSSCK = 2

7 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]

8 This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register. Table 66. DSPI timing1 (continued)

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 123

4.18.11 I 2C timing

Table 67. I2C input timing specifications—SCL and SDA 1 Parameter values guaranteed by design.

2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device

Table 68. I2C Output timing specifications—SCL and SDA affected by the prescale and division values programmed in IFDR. 2 Parameter values guaranteed by design.

3 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device

takes to reach a high level depends on external signal capacitance and pullup resistor values.

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor124 Figure 41. I2C input/output timing

4.18.12 QuadSPI timing

• All data is based on a negative edge data launch from PX D20 and a positive edge data capture, as shown in the timing diagrams in this section.
• The supply conditions, over a temperature range of –45 C to 125 C/150 C, are as follows: — I/O voltage: 3.0 V , Core supply: 1.2 V — I/O voltage: 3.3 V , Core supply: 1.2 V — I/O voltage: 3.6 V , Core supply: 1.2 V
• The actual frequency at which the device can work will be a combination of this data and the clock pad profile.
• All measurements are considering 70 % of VDDE levels for clock pin and 50% of VDDE level for data pins.
• Timings assume a setting of 0x0000_000x for QSPI_SMP R register (see the reference manual for details).
• A negative value of hold is an indication of pad delay on the clock pad (delay b/w actual edge capturing data in the device vs. edge appearing at the pin).
• Measurements are with a load of 50 pF on output pins
• The clock profile is measured at 30% to 70% levels of VDDE. The numbers in Figure 42 and Figure 43 correspond to events as described in Table 70.

Table 69. QuadSPI timing specifications, maximum temperature 125 C

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 125 Figure 42. QuadSPI output timing Figure 43. QuadSPI input timing Table 70. QuadSPI timing events

1 Last address out

2 Address captured at flash memory

3 Data out from flash memory

4 Ideal data capture edge

5 Delayed data capture edg e with QSPI_SMPR=0x0000_000X

6 Delayed data capture edg e with QSPI_SMPR=0x0000_002X

7 Delayed data capture edg e with QSPI_SMPR=0x0000_004X

8 Delayed data capture edg e with QSPI_SMPR=0x0000_006X

1. Address captured at flash
2. Delayed data capture edge with QSPI_SMPR=0x0000_000x
3. Delayed data capture edge with QSPI_SMPR=0x0000_002x
4. Delayed data capture edge with QSPI_SMPR=0x0000_004x
5. Delayed data capture edge with QSPI_SMPR=0x0000_006x

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor126 Figure 44. QuadSPI clock profile

4.18.13 TCON/RSDS timing

• Measurement condition: Vdde/Vdd33 = 3.3 V ± 10%, Vdd = 1.2 V ± 10%, Vss/Vsse = 0 V , T = –40 to 105°C
• Termination: 100  ± 5%
• VREFH_RSDS terminations of 47 F

Table 71. TCON/RSDS timing 1 There are eight programmable bits to provide 256 different skew numbers with various combinations of these bits. 2 Default value of all the eight skew options are all “1”. 3 All “0” combination of eight bits is not valid.

5 Package mechanical data

6 Ordering information

Figure 48. PXD20 orderable part number description Table 72. PXD20 orderable part number summary Note: Not all options are available on all devices. See Table 72 for more information.

Revision history

PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 129

7 Revision history

Table 73. Revision history 1 30 Sep 2011 Initial release. 2 27 Apr 2012 Editorial updates and impr ovements throughout the document. In Figure 4 (416 TEPBGA pinout), corrected pin P25 to VSS. Figure 7 (Power-down sequencing). — Changed maximum Tj from 150 oC to 140 oC. maximum value from 1.280 V to 1.29 V. low-power voltage regulator electrical characteristics). Single Display Drive from 306 to 240 mA. — Updated typical I DDHALT current at 25 oC from 12.67 mA to 17.5 mA. — Updated typical I DDHALT current at 105 oC from 33.1 mA to 35 mA. — Updated maximum I DDHALT current at 25 oC from 18.26 mA to 21.5 mA. — Updated maximum I DDHALT current at 105 oC from 36.41 mA to 43.5 mA. — In I DDHALT specification, changed TB = 105 oC to TA =1 0 5oC.

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