MPX5100 NXP | Alldatasheet

Document overview

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Technical content

Features

  • 2.5% maximum error over 0 to 85 °C
  • Ideally suited for microproce ssor or microcontroller-based systems
  • Patented silicon shea r stress strain gauge
  • Available in absolute, differe ntial and gauge configuration
  • Durable epoxy unibody element
  • Easy-to-use chip carrier option Typical applications
  • Patient monitoring
  • Process control
  • Pump/motor control
  • Pressure switching
  • White goods

Ordering information

Device name Shipping Package # of Ports Pressure type Device markingNone Single Dual Gauge Differential Absolute Unibody Package (MPX5100 Series) MPX5100AP Tray 98ASB42796B • • MPX5100AP MPX5100DP Tray 98ASB42797B • • MPX5100DP MPX5100GP Tray 98ASB42796B • • MPX5100GP Small Outline Package (MPXV5100 Series) MPXV5100DP Tray 98ASA99255D • • MPXV5100DP MPXV5100GC6U Rail 98ASB17757C • • MPXV5100G MPXV5100GC7U Rail 98ASB17759C • • MPXV5100G MPXV5100GP Tray 98ASA99303D • • MPXV5100GP MPX5100DP 98ASA42797B MPXV5100DP 98ASA99255D MPXV5100GP 98ASA99303D MPXV5100GC6U 98ASB17757C MPXV5100GC7U 98ASB17759C MPX5100 Unibody packages Small outline packages MPX5100AP/GP 98ASB42796B

2 NXP Semiconductors, B.V. Related Documentation The MPX5100 device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the NX P homepage at: http://www.nxp.com/ 2. In the Keyword search box at th e top of the page, enter the device number MPX5100. 3. In the Refine Your Result pane on the left, click on the Docu mentation link.

Contents

1 General Description

1.1 MPX5100AP/DP/GP Block diagram

Figure 1 shows a block diagram of the internal circuitry integrated on a pressure sensor chip in a unibody package. Figure 1. Integrated pressure sensor block diagram

1.2 MPX5100AP/DP/GP Pinout (Unibody)

Figure 2. Device pinout (top view) Table 1. Pin functions

2 GND Ground

4 DNC Do not connect to exter nal circuitry or ground. 5 DNC Do not connect to exter nal circuitry or ground. 6 DNC Do not connect to exter nal circuitry or ground. Pins 4, 5, and 6 are internal device connections. Do not connect to external circuitry or ground.

1.3 MPXV5100DP/GC6U/GC7U/GP block diagram

Figure 1 shows a block diagram of the internal circuitry integrated on a pressure sensor chip in a small outline package. Figure 3. Integrated pressure sensor block diagram

1.4 MPXV5100DP/GC6U/GC7U/GP pi nout (small outline package)

Figure 4. Device pinout (top view) Table 2. Pin functions 1 DNC Do not connect to exter nal circuitry or ground.

3 GND Ground

5 DNC Do not connect to exter nal circuitry or ground. 6 DNC Do not connect to exter nal circuitry or ground. 7 DNC Do not connect to exter nal circuitry or ground. 8 DNC Do not connect to exter nal circuitry or ground. Pins 1, 5, 6, 7, and 8 are internal device connections. Do not connect to external circuitry or ground.

2 Mechanical and Electrical Specifications

2.1 Maximum ratings

2.2 Operating characteristics

Table 3. Maximum ratings(1)

  1. Exposure beyond the specified limits may cause permanent damage or degradation to the device.

Table 4. Operating characteristics (VS = 5 Vdc, TA = 25 °C.)

  1. 1.0 kPa (kiloPascal) equals 0.145 psi.
  2. Device is ratiometric within this specified excitation range.
  3. Offset (VOFF) is defined as the output voltage at the minimum rated pressure.
  4. Full-scale output (VFSO) is defined as the output voltage at the maximum or full-rated pressure.
  5. Full-scale span (VFSS) is defined as the algebraic difference between the output voltage at full-rated pressure and the output voltage at the
  6. Accuracy (error budget) consists of the following:

Linearity: Output deviation from a straight line relationship with pressure over the specified pressure range. from the minimum or maximum operating temperature points, with zero differential pressure applied. maximum rated pressure at 25 °C. TcSpan: Output deviation over the temperature range of 0 to 85 °C , relative to 25 °C. TcOffset: Output deviation with minimum pressure applied over th e temperature range of 0 to 85 °C, relative to 25 °C. Variation from nominal: The vari ation from nominal values, for offset or full-scale span, as a percent of VFSS at 25 °C.

  1. Response time is defined as the time for the incremental changed in the output to go from 10% to 90% of its final value when subjected to a

specified step change in pressure.

  1. Warm-up time is defined as the time required for the product to meet the specified output voltage after the pressure has been stabilized.
  2. Offset stability is the product’s output deviation when subjected to 1000 hours of pulsed pressure, temperature cycling with bias test.

3 On-chip Temperature Compensation and Calibration

of the specified pressure range. reliability. Contact the factory for information regarding media compatibility in your application. Figure 5. Output versus pressure differential Figure 6. Cross-sectional diagrams (not-to-scale) microprocessor or microcontroller. Proper decoupling of the power supply is recommended. Figure 7. Recommended power supply decoupling and output filtering

4 Package Information

4.1 Pressure (P1)/Gauge (P2) side identification table

operate with positive differential pressure applied, P1 > P2. The Pressure (P1) side may be identified by using the table below.

4.2 Minimum recommended footprint for surface mounted applications

Figure 14. Small outline package footprint

4.3 Package dimensions

This drawing is located at http://cache.NXP .com/files/shared/doc/package_info/98ASB17757C.pdf.

10 NXP Semiconductors, B.V. Case 98ASB17757C, 8-lead small outline package DIM MIN MAX MIN MAX MILLIMETERSINCHES A 10.540.4250.415 10.79 B 10.540.4250.415 10.79 C 12.700.5200.500 13.21 D 0.960.0420.038 1.07 G 0.100 BSC 2.54 BSC H 0.002 0.010 0.05 0.25 J 0.009 0.011 0.23 0.28 K 0.061 0.071 1.55 1.80 M 0 7 0 7 N 0.444 0.448 11.28 11.38 S 0.709 0.725 18.01 18.41 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006). 5. ALL VERTICAL SURFACES 5 /C0095 TYPICAL DRAFT. /C0095/C0095 /C0095/C0095 S D G 8 PL SBM0.25 (0.010) A ST –A– –B– C M J K PIN 1 IDENTIFIER H SEATING PLANE –T– N V W V 0.245 0.255 6.22 6.48 W 0.115 0.125 2.92 3.17

NXP Semiconductors, B.V. 11 This drawing is located at http://cache.NXP .com/files/shared/doc/package_info/98ASB17759C.pdf. Case 98ASB17759C, 8-lead small outline package D FREESCALE

12 NXP Semiconductors, B.V. This drawing is located at http://cache.NXP .com/files/shared/doc/package_info/98ASB42796B.pdf. Case 98ASB42796B, 6-lead unibody package

NXP Semiconductors, B.V. 13 Case 98ASB42796B, 6-lead unibody package

14 NXP Semiconductors, B.V. This drawing is located at http://cache.NXP .com/files/shared/doc/package_info/98ASB42797B.pdf. Case 98ASB42797B, 6-lead unibody package

NXP Semiconductors, B.V. 15 This drawing is located at http://cache.NXP .com/files/shared/doc/package_info/98ASA99255D.pdf. Case 98ASA99255D, 8-lead, dual port, small outline package

16 NXP Semiconductors, B.V. Case 98ASA99255D, 8-lead, dual port, small outline package

NXP Semiconductors, B.V. 17 This drawing is located at http://cache.NXP .com/files/shared/doc/package_info/98ASA99303D.pdf. Case 98ASA99303D, 8-lead, side port, small outline package PAGE 1 OF 2

18 NXP Semiconductors, B.V. Case 98ASA99303D, 8-lead, side port, small outline package

5 Revision History

Table 5. Revision history

  • Deleted obsolete part numbers MPX5100A and MPX5100D.
  • Changed format to new corporate format.
  • Added pinout for MPX5100AP/DP/GP in Figure 2.
  • Added pin functions for MPX5100AP/DP/GP as Table 1.
  • Added pinout for MPXV5100DP/GC6U/GC7U/GP as Figure 4.
  • Added pin functions for MPXV5100DP/GC6U/GC7U/GP as Table 2.
  • Moved section 5.1, Package dimensions to Section 4.3.
  • Deleted section 5, duplicate Package Information information section.
  • Added revision history as Table 5.

Document Number: MPX5100 Rev. 14 Information in this document is provided solely to enable system and software implementers to use NXP products.There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: NXP.com/salestermsandconditions. NXP and the NXP logo are trademarks of NXP Semiconductors, B.V. All other product or service names are the property of their respective owners. How to Reach Us: Home Page: NXP.com Web Support: NXP.com/support