MPC601EC NXP | Alldatasheet
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(Motorola Order Number) REV 3 MPR601HSU-03 (IBM Order Number) PowerPC, PowerPC 601, and PowerPC Architecture are trademarks of International Business Machines Corp. used by Motorola under license from International Business Machines Corp. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to Motorola Inc. 1995 Instruction set and other portions International Business Machines Corp. 1991–1995
601 Hardware Specifications
change or discontinue this product without notice. Advance Information PowerPC 601 RISC Microprocessor Hardware Specifications The PowerPC 601 microprocessor is the first implementation of the PowerPC™ family of reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical characteristics of the 601 and 601v. For functional characteristics of the processor, refer to the PowerPC 601 RISC Microprocessor User’ s Manual This document contains the following topics: Topic Page Section 1.1, “PowerPC 601 Microprocessor Overview” 2 Section 1.2, “General Parameters” 3 Section 1.3, “PowerPC 601 Microprocessor Electrical Specifications” 4 Section 1.4, “PowerPC 601 Microprocessor Thermal Management Information” 14 Section 1.5, “PowerPC 601 Microprocessor Pinout Diagram” 16 Section 1.6, “PowerPC 601 Microprocessor Pinout Listing” 17 Section 1.7, “PowerPC 601 Microprocessor Package Description” 19 Appendix A, “General Handling Recommendations” 21 In this document, the terms PowerPC 601 RISC microprocessor, 601, and 601v are used to denote the first microprocessor from the PowerPC Architecture™ family. The PowerPC 601 microprocessors are available from IBM as PPC601 and from Motorola as MPC601. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006
2 601 Hardware Specifications, Rev 3 Preliminary/Subject to Change without Notice
1.1 PowerPC 601 Microprocessor Overview
The 601 is the first implementation of the PowerPC family of RISC microprocessors. The 601 implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC implementations, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. The 601 is a superscalar processor capable of issuing and retiring three instructions per clock, one to each of three execution units. Instructions can complete out of order for increased performance; however, the 601 makes execution appear sequential. The 601 integrates three execution units—an integer unit (IU), a branch processing unit (BPU), and a floating-point unit (FPU). The ability to execute three instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for 601-based systems. Most integer instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. The 601 provides an on-chip, 32-Kbyte, eight-way set-associative, physically addressed, unified instruction and data cache and an on-chip memory management unit (MMU). The MMU contains a 256-entry, two-way set-associative, unified translation lookaside buffer (UTLB) and provides support for demand-paged virtual memory address translation and variable-sized block translation. Both the UTLB and the cache use least recently used (LRU) replacement algorithms. The 601 has a 64-bit data bus and a 32-bit address bus. The 601 interface protocol allows multiple masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping logic maintains cache coherency in multiprocessor applications. The 601 supports single-beat and burst data transfers for memory accesses; it also supports both memory-mapped I/O and direct-store addressing. The 601 uses an advanced CMOS (complementary metal-oxide semiconductor) process technology and maintains full interface compatibility with TTL devices. The 601v is functionally equivalent to the 601, but operates with reduced internal voltages and with reduced power dissipation.
1.1.1 PowerPC 601 Microprocessor Features
Major features of the 601 and 601v are as follows:
- High-performance, superscalar microprocessor — As many as three instructions in execution per clock (one to each of the three execution units) — Single clock cycle execution for most instructions — Pipelined FPU for all single-precision and most double-precision operations
- Three independent execution units and two register files
- High instruction and data throughput — Zero-cycle branch capability — Programmable static branch prediction on unresolved conditional branches — Instruction unit capable of fetching eight instructions per clock from the cache — An eight-entry instruction queue that provides lookahead capability — Interlocked pipelines with feed-forwarding that control data dependencies in hardware — Unified 32-Kbyte cache—eight-way set-associative, physically addressed; LRU replacement algorithm Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006
601 Hardware Specifications, Rev 3 3
- Facilities for enhanced system performance — Bus interface can run at integer factor of operating frequency — A 64-bit split-transaction external data bus with burst transfers — Support for address pipelining and limited out-of-order bus transactions — Snooped copy-back queues for cache block (sector) copy-back operations — Bus extensions for I/O controller interface operations — Multiprocessing support features that include the following: – Hardware enforced, four-state cache coherency protocol (MESI) – Separate port into cache tags for bus snooping
1.2 General Parameters
Table 1 provides a summary of the general parameters of the 601 and 601v. Table 1. General Parameters of the PowerPC 601 Microprocessor Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.3 PowerPC 601 Microprocessor Electrical
specifications are preliminary and subject to change without notice.
1.3.1 PowerPC 601 Microprocessor DC Electrical Characteristics
Table 2 provides the maximum ratings for the 601 and 601v. be brought up and powered down simultaneously. Table 3 provides the DC electrical characteristics for the 601 and 601v. Table 2. Maximum Ratings Table 3. DC Electrical Characteristics Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
601 Hardware Specifications, Rev 3 5
- The 601v (100 MHz) requires 5.0 V Vdd
AR TR Y, and SHD, and is enabled by asserting SC_DRIVE.
- Unique 2X_PCLK input voltages only apply for a 601v (100 MHz) processor.
- Capacitance is periodically sampled rather than 100% tested.
- Typical power dissipation measured at Vdd
= 5.0 V while running SPECfp92 suite. System thermal designs should accommodate worst case power dissipation. Table 3. DC Electrical Characteristics (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.3.2 PowerPC 601 Microprocessor AC Electrical Characteristics
This section provides the AC electrical characteristics for the 601 and 601v.
1.3.2.1 Input AC Specifications
Table 4 provides the clock AC timing specifications as defined in Figure 1.
- Maximum allowable sum of cycle-to-cycle or long-term jitter
- Guaranteed by design/characterization
- PCLK_EN is measured from the 1.4 V level of the signal in question to the 1.4 V level of the input
Table 4. Clock AC Timing Specifications
50 MHz 66 MHz 80 MHz 100 MHz
3 PCLK_EN setup to falling
4 PCLK_EN hold from falling
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601 Hardware Specifications, Rev 3 7
Figure 1. PowerPC 601 Microprocessor Clock Input Timing Diagram Table 5 provides the input AC timing specifications as defined in Figure 2. Table 5. Input AC Timing Specifications
50 MHz 66 MHz 80 MHz 5 100 MHz6
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
- All input specs are measured from the TTL level of the signal in question to the 1.4 V level of the input
2X_PCLK rising edge, except for PCLK_EN.
- Input setup and hold times are measured relative to the bus transition point. An internal clock phase is
occur on the next rising edge of the 2X_PCLK.
- Test signals include: SYS_QUIESC , RESUME, SCAN_CTL, SCAN_CLK, and SCAN_SIN.
- Signals included are: TSIZ0–TSIZ2, TBST, GBL, TT0–TT3, A0–A31, AP0–AP3, DH0–DH31, DL0–DL31,
- This specification is for an 80-MHz processor with the interface running at half the processor frequency
- This specification is for a 100-MHz 601v processor with the interface running at half the processor frequency
Table 5. Input AC Timing Specifications (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
601 Hardware Specifications, Rev 3 9
diagrams for device operation.
- VM = Midpoint voltage (1.4 V)
Figure 2. PowerPC 601 Microprocessor Input Timing Diagram Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.3.2.2 Output AC Specifications
Table 6. Loading Factors for Output Signals Notes: 1. Normal mode means that SC_DRIVE is negated.
- Double drive is only available for the following signals: ABB, DBB, SHD, ARTR Y, TS, and XATS .
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601 Hardware Specifications, Rev 3 11
Table 7. Output AC Timing Specifications (Theoretical 0 pF load) Actual specifications must be derived for a minimum of 20 pF capacitive load (see Table 6).
50 MHz 66 MHz 80 MHz 8 100 MHz9
5 Width of precharge for
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
- All output specs are measured from the 1.4 V level of the 2X_PCLK input to the TTL level of the signal in
BCLK_EN , as described above. negated when there is no bus master driving.
- Because SHD and ARTR Y may be asserted by more than one device at the same time, they are negated
contention on these signals. This precharge may be disabled by setting HID0 (bit 29).
- Double drive is only available for the following signals: ABB, DBB, SHD, ARTR Y, TS, and XATS .
- If the chip is operated at a frequency less than that which is specified, the width of precharge will be
approximately one 2X_PCLK period plus 1 ns.
- ABB and DBB disable assumes continuous clock operation. If clock operations are stopped, the disable
may extend until clock operations are restarted.
- Minimum output enable and output hold times are guaranteed by design.
- This specification is for a 100-MHz 601v processor with the interface running at half the processor
Table 7. Output AC Timing Specifications (Theoretical 0 pF load) (Continued) Actual specifications must be derived for a minimum of 20 pF capacitive load (see Table 6). Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
601 Hardware Specifications, Rev 3 13
Figure 3. PowerPC 601 Microprocessor Output Timing Diagram Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.4 PowerPC 601 Microprocessor Thermal
This section provides thermal management information for the 601 and 601v.
1.4.1 Heat Sink Selection
variables. However, that type of analysis is beyond the scope of this reference. Table 8. qJH for Three Typical Heat Sink to Chip Interfaces Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
601 Hardware Specifications, Rev 3 15
Preliminary/Subject to Change without Notice
1.4.2 Thermal Management Example
The following example provides the information necessary to make a heat sink selection. For a typical desktop application which uses an 80-MHz 601 (8 W typical, 9.2 W worst case power) and has a maximum ambient air temperature of 40 oC, the allowable thermal resistance of the heat sink (qHA ) can be determined. Thermal resistance (junction to case) = qJH = 0.95 °C/Watt (junction to case) (assuming AI epoxy interface) Maximum T j (junction temperature) = 85 oC Maximum ambient air temperature Ta = 40 oC cf = 1.15 (correction factor for 7000-ft. elevation) qHA = [( (Tj – Ta) / chip power) – qJH – qconstriction] x 1/cf qHA = [((85 oC – 40 oC)/ 9.2 W) – 0.95 °C/Watt – 0.2 °C/Watt)] x 1/1.15 qHA = 3.25 °C/Watt (It is the maximum thermal resistance of the heat sink required to maintain 85 oC maximum junction temperature.)
1.4.3 Estimation of Tj
Factors such as air-ducting and preheating can significantly affect the thermal performance of the processor. As such, the processor operating temperature should be verified for each application. Since the processor junction temperature is not readily measurable, it is necessary to estimate this value. If the base temperature of the heat sink is known, the relationship to junction temperature can be easily derived as follows: Tj = TH + Power x qJH where: TH = heat sink base temperature The heat sink base temperature can be obtained by a simple thermocouple measurement. If the actual module power dissipation is available, this value should be substituted for chip power. Otherwise, an estimate of the nominal and maximum junction temperature can be made by substituting the nominal and maximum device power dissipation values from Table 3. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006
1.5 PowerPC 601 Microprocessor Pinout Diagram
Figure 4 contains the pin assignments for the 601 and 601v. Figure 4. PowerPC 601 Microprocessor Pin Assignments Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
601 Hardware Specifications, Rev 3 17
1.6 PowerPC 601 Microprocessor Pinout Listing
Table 9 provides the pinout listing for the 601 and 601v. Table 9. PowerPC 601 Microprocessor Pinout Listing Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Table 9. PowerPC 601 Microprocessor Pinout Listing (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
601 Hardware Specifications, Rev 3 19
Preliminary/Subject to Change without Notice Note: For the 50, 66, and 80 MHz versions of the 601, VddINT and VddI/O are not implemented as separate supplies on the chip, and should be powered with the same potential.
1.7 PowerPC 601 Microprocessor Package
Description
The following sections provide the package parameters and the mechanical dimensions for the 601 and 601v.
1.7.1 Package Parameters
The package parameters are as provided in the following list. The package type is 40-mm, 304-pin ceramic quad flat pack. Package outline 40 mm Interconnects 304 Pitch 0.5 mm Lead plating Ni Au Solder joint Sn/PB (10/90) Lead encapsulation HYSOL 4323 C4 encapsulation EPX 5341 Maximum module height 3.1 mm Co-planarity specification 0.08 mm Note: No solvent can be used with the C4FP. VddINT 2, 11, 16, 37, 53, 61, 76, 88, 92, 113, 128, 133, 162, 163, 171, 179, 189, 200, 205, 225, 240, 253, 257, 265, 268, 270, 280, 283, 293 High Input VddI/O 24, 29, 40, 48, 66, 79, 96, 101, 105, 116, 120, 141, 146, 154, 156, 166, 174, 176, 192, 213, 218, 234, 245, 249, 261, 272, 276, 286, 289, 296 High Input Vss 6, 12, 20, 25, 33, 38, 39, 44, 52, 57, 65, 73, 77, 87, 89, 100, 102, 109, 114, 115, 117, 124, 129, 137, 142, 150, 152, 153, 158, 160, 164, 170, 175, 177, 183, 190, 191, 193, 196, 204, 209, 217, 223, 230, 239, 242, 252, 259, 263, 266, 267, 269, 274, 278, 281, 284, 287, 294, 301 Low Input WT 214 Low Output XATS 229 Low I/O Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.7.2 PowerPC 601 Microprocessor Mechanical Dimensions
Figure 5 shows the mechanical dimensions for the 601 and 601v. Figure 5. Mechanical Dimensions of the PowerPC 601 Microprocessor Package Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
601 Hardware Specifications, Rev 3 21
Preliminary/Subject to Change without Notice Appendix A General Handling Recommendations The following list provides a few guidelines for package handling:
- Handle the electrostatic discharge sensitive (ESD) package with care before, during, and after processing.
- Do not apply any load to exceed 3 Kg after assembly.
- Components should not be hot dip tinned
- The package encapsulation is an acrylated urethane. Use adequate ventilation (local exhaust) for all elevated temperature processes. The package parameters are as follows: Heat sink adhesive AIEG-7655 IBM reference drawing 99F4869 Test socket Yamaichi IC51-3044-1543-REV C Signal 187 Power/ground 117 Total 304 A.1 Package Environmental, Operation, Shipment, and Storage Requirements The environmental, operation, shipment, and storage requirements are as follows:
- Make sure that the package is suitable for continuous operation under business office environments. — Operating environment: 10 °C to 40 °C, 8% to 80% relative humidity — Storage environment: 1 °C to 60 °C, 5% to 80% relative humidity — Shipping environment: 40 °C to 60 °C, 5% to 100% relative humidity
- This component is qualified to meet JEDEC moisture Class 2 — After expiration of shelf life, packages may be baked at 120 °C (+10/–5 °C) for 4 hours minimum and packaged. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006
22 601 Hardware Specifications, Rev 3 Preliminary/Subject to Change without Notice A.2 Card Assembly Recommendations This section provides recommendations for card assembly process. Follow these guidelines for card assembly.
- This component is supported for aqueous, IR, convection reflow, and vapor phase card assembly processes.
- The temperature of packages should not exceed 220 °C for longer than 5 minutes.
- The package entering a cleaning cycle must not be exposed to temperature greater than that occurring during solder reflow or hot air exposure.
- It is not recommended to re-attach a package that is removed after card assembly. A.2.1 Card Assembly Process During the card assembly process, no solvent can be used with the C4FP, and no more than 3 Kg of force must be applied normal to the top of the package prior to, during, or after card assembly. Other details of the card assembly process follow: Solder paste Either water soluble (for example, Alpha 1208) or no clean Solder stencil thickness0.152 mm Solder stencil aperatureWidth reduced to 0.03 mm from the board pad width Placement tool Panasonic MPA3 or equivalent Solder reflow Infrared, convection, or vapor phase Solder reflow profile Infrared and/or convection
- Average ramp-up—0.48 to 1.8 °C/second
- Time above 183 °C—45 to 145 seconds
- Minimum lead temperature—200 °C
- Maximum lead temperature—240 °C
- Maximum C4FP temperature—245 °C Vapor phase
- Preheat (board)—60 °C to 150 °C
- Time above 183 °C—60 to 145 seconds
- Minimum lead temperature—200 °C
- Maximum C4FP temperature—220 °C
- Egress temperature—below 150 °C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006
601 Hardware Specifications, Rev 3 23
Preliminary/Subject to Change without Notice Clean after reflow De-ionized (D.I.) water if water-soluble paste is used
- Cleaner requirements—conveyorized, in-line
- Minimum of four washing chambers —Pre-clean chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 70 °C minimum, dwell time of 24 seconds minimum, water is not re-used, water flow rate of 30 liters/minute. —Wash chamber #1: top and bottom sprays, minimum top-side pressure of 48 psig, minimum bottom-side pressure of 44 psig, water temperature of 62.5 °C (–2.5 °C), dwell time of 48 seconds minimum, water flow rate of 350 liters/minute. —Wash chamber #2: top and bottom sprays, minimum top-side pressure of 32 psig, minimum bottom-side pressure of 28 psig, water temperature of 72.5 °C (–2.5 °C), dwell time of 48 seconds minimum, water flow rate of 325 liters/minute. —Final rinse chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 72.5 °C minimum, dwell time of 24 seconds minimum, water flow rate of 30 liters/minute.
- No cleaning required if “no clean solder paste” is used Touch-up and repair Water soluble (for example, Kester 450) or No Clean Flux C4FP removal Hot air rework C4FP replace Hand solder Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC 601 microprocessor embodies the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. Both Motorola and IBM reserve the right to modify this manual and/or any of the products as described herein without further notice. NOTHING IN THIS MANUAL, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE . Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages, actual or otherwise. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals,” must be validated for each customer application by customer’s technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others. 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International Business Machines Corp. is an Equal Opportunity/Affirmative Action Employer. Motorola Literature Distribution Centers: USA: Motorola Literature Distribution, P.O. Box 20912, Phoenix, Arizona 85036. EUROPE: Motorola Ltd., European Literature Centre, 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd., 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd., Silicon Harbour Centre, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. Technical Information: Motorola Inc. Semiconductor Products Sector Technical Responsiveness Center; (800) 521-6274. Document Comments : FAX (512) 891-2638, Attn: RISC Applications Engineering. IBM Microelectronics: USA: IBM Microelectronics, Mail Stop A25/862-1, PowerPC Marketing, 1000 River Street, Essex Junction, VT 05452-4299; Tel.: (800) PowerPC [(800) 769-3772]; FAX (800) POWERfax [(800) 769-3732]. EUROPE: IBM Microelectronics, PowerPC Marketing, Dept. 1045, 224 Boulevard J.F. Kennedy, 91105 Corbeil-Essonnes CEDEX, France; Tel. (33) 1-60-88 5167; FAX (33) 1-60-88 4920. JAPAN: IBM Microelectronics, PowerPC Marketing, Dept., R0260, 800 Ichimiyake, Yasu-cho, Yasu-gun, Shinga-ken, Japan 520-23; Tel. (81) 775-87-4745; FAX (81) 775-87-4735. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006