MPQ9842

MPS Industries, Inc.

36V, 2A, Low IQ,Step-Down Converter AEC-Q100 Qualified Rev. 1.1 7/29/2022

Manufacturer: MPS Industries, Inc.

Document: 37 Pages / 2Mb

Request Quote Download Datasheet Read online HTML view

More from MPS Industries, Inc. Browse M parts

Online Datasheet

Read MPQ9842 online.

MPQ9842 MPSIND | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 37

Technical content

MPQ9842 36V, 2A, Low IQ, Step-Down Converter AEC-Q100 Qualified MPQ9842 Rev. 1.1 www.MonolithicPower.com 1 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

DESCRIPTION

The MPQ 9842 is a high -frequency, synchronous, rectified, step -down, switch-mode converter with built -in power MOSFETs. It offers a very compact solution that achieves 2A of continuous output current with excellent load and line regulation over a wide 3.3V to 36V input supply range. The switching frequency is programmable or can be synchronized to an external clock in the range of 350kHz to 2.5MHz. Synchronous operation and ul tra-low 14μA sleep mode quiescent current provide high efficiency o ver the output current load range, allowing the MPQ9842 to be used in a variety of step -down applications in automotive input environment s and battery -powered applications. Peak-current-mode operat ion provides fast transient response and eases loop stabilization. The excellent low dropout performance allows the MPQ9842 to be used in high duty cycle applications. Full protection features include over -current protection (OCP), short-circuit protection (SCP), and thermal shutdown. An open -drain power good (PG) signal indicates when the output is within 10% of its nominal voltage. The MPQ984 2 is available in a space-saving QFN-16 (3mmx4mm) package.

FEATURES

2μA Low Shutdown Supply Current
14μA No-Load Quiescent Current
Internal 125mΩ High-Side and 55mΩ Low- Side MOSFET
350kHz to 2.5MHz Programmable Switching Frequency
Power Good (PG) Output
External Soft Start (SS)
80ns Minimum On Time
Selectable Forced CCM and AAM
Hiccup Over-Current Protection (OCP)
AEC-Q100 Grade-1
Available in a QFN-16 (3mmx4mm) Package

APPLICATIONS

Automotive Systems
Industrial Power Systems All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VOUT SW EN VIN BST PGND MPQ9842AGND PHASE SS FREQ SYNC FB VCC PG BIAS VIN GND OFF ON VOUT SW EN VIN BST PGND MPQ9842AGND PHASE SS FREQ SYNC FB VCC PG BIAS VIN GND OFF ON Output Adjustable Version Output Fixed Version

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 2 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL Rating MPQ9842GL QFN-16 (3mmx4mm) See Below 1 MPQ9842GL-AEC1 MPQ9842GLE-AEC1* MPQ9842GLE-33-AEC1* MPQ9842GLE-5-AEC1* * For Tape & Reel, add suffix –Z (e.g. MPQ9842GL–Z) Moisture Sensitivity Level Rating *Wettable Flank TOP MARKING (MPQ9842GL & MPQ9842GL-AEC1) MP: MPS prefix Y: Year code WW Week code 9842 : First four digits of the part number LLL: Lot number TOP MARKING (MPQ9842GLE-AEC1) MP: MPS prefix Y: Year code W: Week code 9842: First four digits of the part number LLL: Lot number E: Wettable lead flank

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 3 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TOP MARKING (MPQ9842GLE-33-AEC1) MP: MPS prefix Y: Year code W: Week code 9842: First four digits of the part number LLL: Lot number E: Wettable lead flank 33: 3.3V fixed output TOP MARKING (MPQ9842GLE-5-AEC1) MP: MPS prefix Y: Year code W: Week code 9842: First four digits of the part number LLL: Lot number E: Wettable lead flank 5: 5V fixed output

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 4 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW PHASE VIN SW 4PGND 13141516 AGNDSSFBFREQ 5 6 7 8 EN SYNC PG BIAS PGND SW BST VCC QFN-16 (3mmx4mm) ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25°C) (2)(5) Electrostatic Discharge (ESD) Ratings Recommended Operating Conditions Operating junction temp. (TJ) (3)…………………. Thermal Resistance (4) θJA θJC QFN-16 (3mmx4mm) NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature , TJ(MAX), the junction -to- ambient thermal resistance , θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can produce an excessive die temperature, and the regulator may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Mission profiles requiring operation above 125 °C TJ may be supported; contact MPS for details. 4) Measured on JESD51-7, 4 -layer PCB. The values given in this table are only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51 -7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application, the value of θJC shows the thermal resistance from junction-to-case bottom. 5) Measured on an M PS EVB: 6 .35cmx6.35cm, 2oz. copper thickness, 4 -layer PCB, the value of θ JC shows the thermal resistance from junction-to-case top.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 5 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 12V, V EN = 2V, T J = -40°C to +1 25°C,unless otherwise noted. Typical values are at TJ = +25°C. Parameter Symbol Condition Min Typ Max Units VIN quiescent current IQ VFB = 0.85V, no load, no switching, TJ = +25C 14 21 µA VFB = 0.85V, no load, no switching 29 VIN shutdown current ISHDN VEN = 0V 2 6 µA VIN under-voltage lockout threshold rising INUVRISING 2.4 2.8 3.2 V VIN under-voltage lockout threshold hysteresis INUVHYS 150 mV EN rising threshold VEN_RISING 0.9 1.05 1.2 V EN threshold hysteresis VEN_HYS 120 mV Feedback reference voltage VREF 784 800 816 mV TJ = +25°C 792 800 808 mV Output voltage accuracy for the MPQ9842-33 3217 3300 3895 mV TJ 25°C 3743 3800 3857 mV 3383 mV TJ = +25°C 3250 3300 3800 3895 mV TJ 25°C 3743 3800 3857 mV 3350 mV Output voltage accuracy for the MPQ9842-5 4875 5000 5125 mV TJ = +25°C 4925 5000 5075 mV HS switch on resistance RON_HS VBST - VSW = 5V 125 165 mΩ LS switch on resistance RON_LS 55 85 mΩ Switching frequency fSW RFREQ = 180kΩ or from sync clock 400 475 550 kHz RFREQ = 82kΩ or from sync clock 850 1000 1150 kHz RFREQ = 27kΩ or from sync clock 2250 2500 2750 kHz Minimum on time (6) tON_MIN 80 ns SYNC input low voltage VSYNC_LOW 0.4 V SYNC input high voltage VSYNC_HIGH 1.8 V Current limit ILIMIT_HS Duty cycle = 40% 4.0 5.0 6.8 A ZCD current IZCD 0.1 A Reverse current limit ILIMIT_REVERSE 3 A Switch leakage current ISW_LKG 0.01 1 µA Soft-start current ISS VSS = 0.8V 5 10 15 µA VCC regulator VCC 5 V VCC load regulation ICC = 5mA 3.5 % Thermal shutdown (6) TSD 170 C Thermal shutdown hysteresis (6) TSD_HYS 20 °C

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 6 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, V EN = 2V, T J = -40°C to +1 25°C, unless otherwise noted. Typical values are at TJ = +25°C. Parameter Symbol Condition Min Typ Max Units PG rising threshold (VFB/VREF) PGRISING VFB rising 85 90 95 % VFB falling 105 110 115 PG falling threshold (VFB/VREF) PGFALLING VFB falling 79 84 89 % VFB rising 113.5 118.5 123.5 PG deglitch timer tPG_DEGLITCH PG from low to high 30 µs PG from high to low 50 µs PG output voltage low VPG_LOW ISINK = 2mA 0.2 0.4 V NOTE: 6) Not tested in production, guaranteed by design and characterization.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 7 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 8 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 9 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, V OUT = 5V, Io=2A, L = 4.7μH, fSW = 450kHz, with EMI filters, TA = +25°C, unless otherwise noted. (7) CISPR25 Class 5 Peak Conducted Emissions 150kHz -108MHz CISPR25 Class 5 Average Conducted Emissions 150kHz - 108MHz -20 -15 -10 0.1 108 PEAK CONDUCTED EMI (dBuV) Frequency (MHz)1 10 CISPR25 CLASS 5 LIMITS NOISE FLOOR -20 -15 -10 0.1 108 AVERAGE CONDUCTED EMI (dBuV) Frequency (MHz)1 10 CISPR25 CLASS 5 LIMITS NOISE FLOOR CISPR25 Class 5 Peak Radiated Emissions 150kHz-30MHz CISPR25 Class 5 Average Radiated Emissions 150kHz-30MHz -10 0.1 30 PEAK RADIATED EMI (dBuV/m) Frequency (MHz)1 10 CISPR25 CLASS 5 LIMITS NOISE FLOOR -10 0.1 30 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz)1 10 CISPR25 CLASS 5 LIMITS NOISE FLOOR CISPR25 Class 5 Peak Radiated Emissions Horizontal, 30MHz-200MHz CISPR25 Class 5 Average Radiated Emissions Horizontal, 30MHz-200MHz 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 10 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, V OUT = 5V, Io=2A, L = 4.7μH, fSW = 450kHz, with EMI filters, TA = +25°C, unless otherwise noted. (7) CISPR25 Class 5 Peak Radiated Emissions Vertical, 30MHz-200MHz CISPR25 Class 5 Average Radiated Emissions Vertical, 30MHz-200MHz 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION CISPR25 Class 5 Peak Radiated Emissions Horizontal, 200MHz-1GHz CISPR25 Class 5 Average Radiated Emissions Horizontal,200MHz-1GHz 200 300 400 500 600 700 800 900 1000 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION 200 300 400 500 600 700 800 900 1000 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION CISPR25 Class 5 Peak Radiated Emissions Vertical, 200MHz-1GHz CISPR25 Class 5 Average Radiated Emissions Vertical,200MHz-1GHz 200 300 400 500 600 700 800 900 1000 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION 200 300 400 500 600 700 800 900 1000 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION NOTE: 7) The EMC test results are based on the application circuit with EMI filters as shown in Figure14.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 11 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01 0 5 10 15 20 25 30 35 40 Line Regulation INPUT VOLTAGE(V) LINE REGULATION (%) IOUT=0.5A IOUT=1A IOUT=2A -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 Load Regulation LOAD CURRENT (A) LOAD REGULATION (%) VIN=12V VIN=24V VIN=36V

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 12 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 13 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 14 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 15 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 16 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 17 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 18 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, fSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 19 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. PIN FUNCTIONS Pin # QFN-16 (3mmx4mm) Name Description

1 PHASE

Selectable in-phase or 180° out-of-phase of the SYNC input. Pull PHASE high to be in-phase. Pull PHASE low to be 180° out-of-phase. Recommend to connect this pin to GND if not used.

2 VIN

Input supply. VIN supplies power to all of the internal control circuitr ies and the power switch connected to SW. Place a decoupling capacitor to ground close to VIN to minimize switching spikes. 3, 10 SW Switch node. SW is the output of the internal power switch. Pin 3 and Pin 10 are internally connected. 4, 9 PGND Power ground. PGND is the reference ground of the power device and requires careful consideration during PCB layout. For best results, connect PGND with copper pours and vias. 5 EN Enable. Pull EN below the specified t hreshold to shut the chip down. Pull EN above the specified threshold to enable the chip.

6 SYNC

Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the internal oscillator frequency to the external clock. The external clock should b e at least 250kHz larger than the RFREQ set frequency. SYNC can also be used to select forced continuous conduction mode ( CCM) or advanced asynchronous mode (AAM). Before the chip starts up , drive SYNC low or leave SYNC floating to choose AAM , and drive SYNC high to external power source or pull up SYNC to VCC directly to set the part forced CCM mode. 7 PG Power good output. The output of PG is an open drain. Float PG if not used.

8 BIAS

Bias input. Connect BIAS to an external power supply (5V ≤ VBIAS ≤ 18V) to reduce power dissipation and increase efficiency. Float BIAS or connect BIAS to ground if not used. 11 BST Bootstrap. BST is the positive power supply for the high-side MOSFET driver connected to SW. Connect a bypass capacitor between BST and SW. 12 VCC Bias supply. VCC supplies power to the internal control circuit and gate drivers. Place a decoupling capacitor (≥1µF) to ground close to VCC. 13 AGND Analog ground. AGND is the reference ground of the logic circuit. 14 SS Soft-start input. Place a capacitor from SS to AGND to set the soft-start period. The MPQ9842 sources 10µA from SS to the soft-start capacitor during start-up. As the SS voltage rises, the feedback threshold voltage increas es to limit inrush current during start-up. There is an internal 0.7ms soft -start setting, the final SS time is determined by the longer time between 0.7ms and external SS setting time. 15 FB Feedback input. For adjustable output version, connect FB to the center point of the external resistor divider. The feedback threshold voltage is 0.8V. Place the resistor divider as close to FB as possible. Avoid placing vias on the FB traces. For fixed output version, connect FB pin to the output directly. 16 FREQ Switching frequency program. Connect a resistor from FREQ to ground to set the switching frequency.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 22 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. At a higher duty cycle operation condition, the time period available to the bootstrap charging is less , so the bootstrap capacitor may not be charged sufficiently. In case the external circuit does not have sufficient voltage or time to charge the bootstrap ca pacitor, extra external circuitry can be used to ensure that the bootstrap voltage is in the normal operation region. Low Dropout Operation (BST Refresh) To improve dropout, the MPQ9842 is designed to operate at close to 100% duty cycle for as long as the BST to SW voltage is greater than 2.5V. When the voltage from BST to SW drops below 2.5V, the HS-FET is turned off using a n under-voltage lockout (UVLO) circuit, which allows the LS-FET to conduct and refresh the charge on the BST capacitor. In PSM or DCM, the LS -FET is forced on to refresh the BST voltage. Since the supply current sourced from the BST capacitor is low, the HS-FET can remain on for more switching cycles than are required to refresh the capacitor, making the effective duty cycle of the switching regulator high. The effective duty cycle during the dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low -side diode , and printed circuit board resistance. Internal Regulator Most of the internal circuitry is powered on by the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5V, the output of the regulator is in full regulation. When VIN is lower than 5V, the output degrades. For better thermal performance, connect BIAS to an external 5V source. VCC and the internal circuit are then powered by BIAS. Since there is an internal diode between BIAS and the internal circuit, float BIAS or connect BIAS to GND if not being used. Enable (EN) Control EN is a digital control pin that turns the regulator on and off. When EN is pulled below its threshold voltage, the chip is put into the lowest shutdown current mode. Pulling EN above its threshold voltage turns on the part. Do not float EN. Frequency Programmable (FREQ) The MPQ9842 oscillating frequency is programmed by either an external resistor (RFREQ) from FREQ to ground or by a logic level SYNC signal. The value of RFREQ can be calculated with Equation (1): 170000)( 11.1 kHzf kΩR s FREQ = (1) The chip can be synchronized to an external clock range from 350kHz up to 2.5MHz through FREQ/SYNC. SYNC and PHASE The internal oscillator frequency can also be synchronized to an exte rnal clock ranging from 350kHz to 2.5MHz through SYNC. The external clock should be at least 250kHz larger than the RFREQ set frequency. Ensure that the high amplitude of the SYNC clock is higher than 1.8V, and low amplitude is lower than 0.4V. There is no pulse width requirement, but there is always parasitic capacitance of the pad, so if the pulse width is too short, a clear rising and falling edge may not be seen due to the parasitic capacitance. The pulse should be longer than 100ns in application. PHASE is used when two or more MPQ 9842 devices are in parallel with the same SYNC clock. Pulling PHASE high forces the device to operate in -phase of the SYNC clock. Pulling PHASE low forces the device to be 180° out-of- phase of the SYNC clock. By setting diffe rent voltages for PHASE, two devices can operate in 180° out -of-phase to r educe the total input current ripple, so a smaller input bypass capacitor can be used (see Figure 3). The PHASE rising threshold is about 2.5V with a 400mV hysteresis.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 23 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. SYNC CLK SW1 SW2 t SW1, 2 has a 180o phase shift SW1: Phase high SW2: Phase low Figure 3: In-Phase and 180° Out-of-Phase Soft Start (SS) Soft start (SS) is implemented to prevent the converter output voltage from overshooting during start -up. When the chip starts up, an internal current source begins charging the external soft -start capacitor. The internal SS voltage (V SSI) rises with the soft -start voltage (VSS), but V SSI differs from VSS in that it has a 0.5V offset and some delay. When VSS is below 0.5V, VSSI is 0V. VSSI rises from 0V to 0.8V while VSS rises from 0.5V to 1.6V. At this time , the error amplifier uses V SSI as the reference, and the output voltage ramps up from 0V to the regulated value following V SSI rising. When V SS reaches 1.6V, V SSI is 0.8V and overrides the internal V REF, so the error amplifier uses the internal VREF as the reference. The soft -start time (t SS) set by the external SS capacitor can be calculated with Equation (2): =  SS SS SS C (nF) 1.1Vt (ms) I ( A) (2) Where CSS is the external SS capacitor, and I SS is the internal 10μA SS charge current. There is also an internal 0.7ms soft start when the SS pin is floating. The final SS time is determined by the longer tim e between 0.7ms and the external SS set time. SS can be used for tracking and sequencing. Pre-Bias Start-Up During start-up, if VFB > VSSI-150mV, then the output has a pre-bias voltage, and neither the HS-FET or LS -FET turn on until VSSI-150mV is higher than FB. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from running away thermally. When the silicon die temperature is higher than its upper threshold, the power MOSFETs are shut down . When the temperature is lower than its lower threshold, thermal shutdo wn is removed, and the MPQ9842 is enabled again. Current Comparator and Current Limit The power MOSFET current is accurately sensed via a current sense MOSFET. The current is then fed to the high -speed current comparator for current -mode control purpose s. The current comparator takes this sensed current as one of its inputs. When the HS-FET is turned on, the comparator is first blanked until the end of the turn -on transition to avoid noise. Then the comparator compares the power switch current with VCOMP. W hen the sensed current is higher than VCOMP, the comparator outputs low to turn off the HS-FET. The maximum current of the internal power MOSFET is limited cycle-by-cycle internally. Hiccup Protection When the output is shorted to ground, causing the output voltage to drop below 55% of its nominal output, the IC shuts down momentarily and begins discharging the soft -start capacitor. The IC restarts with a full soft start when the soft-start capacitor is fully discharged. This hiccup process is repeated until the fault is removed. Start-Up and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current , and then the internal regulator is enabled. The regulator provides a stable supply for the rest of the circuitries. While the internal supply rail is up, an internal timer holds the power MOSFET off for about 50µs to blank the start -up glitches. When the soft-start block is enabled , it first holds its SS output low to ensure that the rest of the circuitries are ready before ramping up slowly. Three events can shut down the chip: EN low, VIN low, and thermal shutdown. In the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to this

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 24 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. shutdown command, but its charging path is disabled. Power Good (PG) Output The MPQ9842 has a power good (PG) indicator. PG is the open drain of a MOSFET and should be connected to VCC or another voltage source through a resistor (e.g.: 100kΩ). In the presence of an input voltage, the MOSFET turns on so that PG is pulled low before SS is ready. When the regulator output is within ±10% of its nominal output , the PG output is pulled high after a delay, typically 30μs. When the output voltage moves outside of this range with a hysteresis, the PG output is pulled low with a 50μs delay to indicate a failure output status.

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 25 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

APPLICATION INFORMATION

Setting the Output Voltage For adjustable output version, the external resistor divider connected to FB sets the output voltage (see Figure 4). RFB1 VoutFB MPQ9842 RFB2 Figure 4: Feedback Network Choose R FB1 first, then RFB2 can be calculated with Equation (3): 10.8V V RR OUT FB1 FB2 = (3) Table 1 lists the recommended feedback resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) RFB1 (kΩ) RFB2 (kΩ) For fixed output version, connect FB pin to the output directly. Selecting the Inductor A 1µH to 10µH inductor with a DC current rating at least 25% higher than the maximum load current is recommended for mos t applications. For higher efficiency, choose an inductor with a lower DC resistance. A n inductor with a larger value results in less ripple current and a lower output ripple voltage , but also has a larger physical size, higher series resistance, and lower saturation current. A good rule for determining the inductor value is to allow the inductor ripple current to be approximately 30% of the maximum load current. The inductance value can then be calculated with Equation (4): =  − OUT OUT SW L IN VVL (1 )f I V (4) Where ∆IL is the peak -to-peak inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (5): = +  −  OUT OUT LP LOAD SW IN VVI I (1 ) 2f L V (5) Selecting the Input Capacitor The input current to the step -down converter is discontinuous and therefore requires a capacitor to supply AC current to the converter while maintaining the DC input voltage. For the best performance, use low ESR capacitors. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most application s, use a 4.7µF to 10µF capacitor. It is strongly recommended to use another lower-value capacitor (e.g. : 0.1µF) with a small package size (0603) to absorb high - frequency switching noise. Place the small er capacitor as close to VIN and GND as possible. Since CIN absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (6): =   − OUT OUT CIN LOAD IN IN VVI I (1 ) VV (6) The wors t-case condition occurs at VIN = 2VOUT, shown in Equation (7): = LOAD CIN II 2 (7) For simplification, choose an input capacitor with an RMS current ratin g greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high -quality ceramic capacitor (e.g. : 0.1μF) as close to the IC as possible. When u sing ceramic capacitors,

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 27 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. a tradeoff between EMI and efficiency, a ≤20 Ω RBST is recommended. Hot-Plug Application In a hot -plug application, the VIN pin may turn on and off frequently before the power supply can establish a co nnection with the IC. In applications where the input power turns on and off frequently, the BST capacitor may have a residual voltage when the IC turns on. This may turn on the high-side MOSFET (HS -FET) for a short time before V CC can rise sufficiently high, which can cause an unexpected overshoot on VOUT. To protect the IC, hot -plug applications are not recommended. If a hot-plug application must be initiated, use a small BST capacitor (e.g. 47nF), a large VCC capacitor (e.g. 4. 7μF), and a large PG resistor (e.g. 1MΩ) to reduce the overshoot risk. Contact an MPS FAE to confirm the design. PCB Layout Guidelines (8) Efficient PCB layout , especially for the input capacitor placement , is critical for stable operation. A four -layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 7 and follow the guidelines below. 1. Place symmetric input capacitors as close to VIN and GND as possible. Recommend to connect pin1 to GND for symmetric input structure if in -phase not used. Pin3 and pin10 are internally connected. Connecting together on layout or not are both OK. Recommend to leave pin3 floating for shorter pin4 and pin1 trace and smaller input hot loop. 2. Use a large ground plane to connect to PGND directly. 3. Add vias near PGND if the bottom layer is a ground plane. 4. Ensure that the high-current paths at GND and VIN have short, direct, and wide traces. 5. Place the ceramic input capacitor , especially the small package size (0603) input bypass capacitor, as close to VIN and PGND as possible to minimize high - frequency noise. 6. Keep the connection of the input capacitor and VIN as short and wide as possible. 7. Place the VCC capacitor as close to VCC and GND as possible. 8. Route SW and BST away fr om sensitive analog areas such as FB. 9. Place the feedback resistors close to the chip to ensure that the trace connect ing to FB is as short as possible. 10. Use multiple vias to connect the power planes to internal layers. NOTE: 8) The recommended PCB layout is based on Figure 8. Top Layer Inner Layer 1

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 28 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. Inner Layer 2 Bottom Layer Figure 7: Recommended PCB Layout

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 33 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 10μF C1A 0.1μF C1C 100kΩ R1 0.1μF 10μH 22μF C2A 5V/2A EN VOUT 10μF C1B SW 3, 10EN5 VIN2 FB 15VCC12 BST 11 PGND 4, 9 PG7 1μF 100kΩ PG GND VIN GND 3.3V-36V MPQ9842 14SS AGND 16FREQ BIAS SYNC6 PHASE1 8 4.7nF SYNC PHASE 169kΩ 22μF C2B 0.1μF C1D 0.1µF 10Ω Figure 16: 5V Fixed Output, fSW = 500kHz

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 34 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-16 (3mmx4mm) Non-Wettable Flank SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS . 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX . 3) JEDEC REFERENCE IS MO -220. 4) DRAWING IS NOT TO SCALE . TOP VIEW RECOMMENDED LAND PATTERN PIN 1 ID MARKING PIN 1 ID INDEX AREA PIN 1 ID 0.15x45°TYP. 0.15x45°

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 35 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. PACKAGE INFORMATION (continued) QFN-16 (3mmx4mm) Wettable Flank SIDE VIEW BOTTOM VIEW NOTE: 1) THE LEAD SIDE IS WETTABLE. 2) ALL DIMENSIONS ARE IN MILLIMETERS. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. TOP VIEW RECOMMENDED LAND PATTERN PIN 1 ID MARKING PIN 1 ID INDEX AREA PIN 1 ID 0.15x45° TYP. 0.15x45° SECTION A-A

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER MPQ9842 Rev. 1.1 www.MonolithicPower.com 36 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. CARRIER INFORMATION Pin1 1 1 1 1 ABCD ABCD ABCD ABCD Feed Direction Part Number Package (3mmx4mm) 5000 N/A N/A 13in 12mm 8mm MPQ9842GL-AEC1-Z MPQ9842GLE-AEC1-Z MPQ9842GLE-33- AEC1-Z MPQ9842GLE-5-AEC1- Z

MPQ9842 – 36V, 2A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ9842 Rev. 1.1 www.MonolithicPower.com 37 7/29/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 3/3/2017 Initial Release - 1.01 10/23/2017 Updated the Recommended Operating Conditions 4 1.02 4/19/2019 Added the MPQ9842-5/33 order package information 1, 2, 3, 20 Updated the Recommended Operating Conditions 4 Added the EMC result of CISPR 25 class 5 9, 10 Added the PHASE and PG pin connection when not used in pin description 19 Added the force CCM setting when start ing up in the pin description 19 1.1 7/29/2022 Added the MSL rating 2 Deleted “Under Qualification” in the Ordering Information section 2 Added the ESD ratings 4 Updated the thermal resistance description for θJA and θJC, based on the EVB and the continuous power dissipation 4 Added the 3.3V and 5V fixed output accuracy 5 Updated the load and line regulation curves 11 Updated the Soft Start (SS) section 23 Added the Hot-Plug Application section 27 Modified the POD error for the wettable flank 35 Added the Carrier information section 36

Product Information

MPQ9842 specifications and overview.

Summary

36V, 2A, Low IQ,Step-Down Converter AEC-Q100 Qualified Rev. 1.1 7/29/2022

Description

36V, 2A, Low IQ,Step-Down Converter AEC-Q100 Qualified Rev. 1.1 7/29/2022

Source title MPQ9842 Datasheet(PDF) - MPS Industries, Inc.

Related Parts

More parts from the same family.

Browse manufacturer