MPQ9841GL

MPQ9841 MPS | Alldatasheet

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Technical content

MPQ9841 36V, 1A, Low IQ, Synchronous Step-Down Converter AEC-Q100 Qualified MPQ9841 Rev.1.02 www.MonolithicPower.com 1 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. The Future of Analog IC Technology

DESCRIPTION

The MPQ9841 is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built-in power MOSFETs. It offers a very compact solution that achieves 1A of continuous output current with excellent load and line regulation over a wide 3.3V to 36V input supply range. The switching frequency can be programmed or synchronized to an external clock in the range of 350kHz to 2.5MHz. The synchronous operation and ultra- low 14μA sleep mode quiescent current provide high efficiency over the output current load range, allowing the MPQ9841 to be used in a variety of step-down applications in automotive input environments and battery-powered applications. Peak-current-mode operation provides fast transient response and eases loop stabilization. The excellent low dropout performance allows the MPQ9841 to be used in high duty cycle applications. Full protection features include over-current protection (OCP), short-circuit protection (SCP), and thermal shutdown. An open-drain power good (PG) signal indicates when the output is within 10% of its nominal voltage. The MPQ9841 is available in a space-saving QFN-16 (3mmx4mm) package.

FEATURES

 2 μA Low Shutdown Supply Current  14 μA No-Load Quiescent Current  Internal 125m Ω High-Side and 115mΩ Low- Side MOSFET  350kHz to 2.5MHz Programmable Switching Frequency  Power Good (PG) Output  External Soft Start (SS)  80ns Minimum On Time  Selectable Forced CCM and AAM  Low Dropout Mode  Hiccup Over-Current Protection (OCP)  AEC-Q100 Grade 1  Available in a QFN-16 (3mmx4mm) Package

APPLICATIONS

 Automotive Systems  Industrial Power Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website unde r Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION PGND AGND 100 10 100 1000 Output Adjustable Version Output Fixed Version

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 2 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MPQ9841GL QFN-16 (3mmx4mm) See Below MPQ9841GL-AEC1 MPQ9841GLE-AEC1 MPQ9841GLE-33-AEC1-Z* MPQ9841GLE-5-AEC1-Z*** * For Tape & Reel, add suffix –Z (e.g. MPQ9841GL–Z) Wettable flank *Under Qualification, wettable flank TOP MARKING (MPQ9841GL & MPQ9841GL-AEC1) MP: MPS prefix Y: Year code W: Week code 9841: First four digits of the part number LLL: Lot number TOP MARKING (MPQ9841GLE-AEC1) MP: MPS prefix Y: Year code W: Week code 9841: First four digits of the part number LLL: Lot number E: Wettable lead flank

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 3 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TOP MARKING (MPQ9841GLE-33-AEC1) MP: MPS prefix Y: Year code W: Week code 9841: First four digits of the part number LLL: Lot number E: Wettable lead flank 33: 3.3V fixed output TOP MARKING (MPQ9841GLE-5-AEC1) MP: MPS prefix Y: Year code W: Week code 9841: First four digits of the part number LLL: Lot number E: Wettable lead flank 5: 5V fixed output

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 4 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW (MPQ9841GL & MPQ9841GL-AEC1 & MPQ9841GLE-AEC1) TOP VIEW (MPQ9841GLE-33-AEC1 & MPQ9841GLE-5-AEC1) QFN-16 (3mmx4mm) QFN-16 (3mmx4mm) ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (T A = +25°C) (2) Recommended Operating Conditions Operating junction temp. (T J) (3) Thermal Resistance (4) θJA θJC QFN-16 (3mmx4mm) Thermal Characterization Parameter (5) QFN-16 (3mmx4mm) ΨJT NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J(MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)- TA)/ θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulato r to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Mission profiles requiring operation above 125°C T J may be supported; contact MPS for details. 4) Measured on JESD51-7, 4-layer PCB. 5) Measured on EV9841-L-00A, 6.35cm* 6.35cm size, 2oz, 4- layer PCB.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 5 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 12V, V EN = 2V, T J = -40°C to +125°C, unless otherwise noted. Typical values are at T J = +25°C. Parameter Symbol Condition Min Typ Max Units VIN quiescent current I Q VFB = 0.85V, no load, no switching, TJ = +25°C 14 21 µA VFB = 0.85V, no load, no switching 29 VIN shutdown current I SHDN V EN = 0V 2 6 µA VIN under-voltage lockout threshold rising INUVRISING 2.4 2.8 3.2 V VIN under-voltage lockout threshold hysteresis INUVHYS 150 mV EN rising threshold V EN_RISING 0.9 1.05 1.2 V EN threshold hysteresis V EN_HYS 120 mV Feedback reference voltage V REF 784 800 816 mV TJ = 25°C 792 800 808 mV HS switch on resistance R ON_HS V BST - VSW = 5V 125 165 m Ω LS switch on resistance R ON_LS 115 155 m Ω Switching frequency F SW RFREQ = 180kΩ or from sync clock 400 475 550 kHz RFREQ = 82kΩ or from sync clock 850 1000 1150 kHz RFREQ = 27kΩ or from sync clock 2250 2500 2750 kHz Minimum on time (6) t ON_MIN 80 ns SYNC input low voltage V SYNC_LOW 0.4 V SYNC input high voltage V SYNC_HIGH 1.8 V Current limit I LIMIT_HS Duty cycle = 40% 2.1 2.5 2.9 A ZCD current I ZCD 0.05 A Reverse current limit I LIMIT_REVERSE 1.5 A Switch leakage current I SW_LKG 0.01 1 µA Soft-start current I SS V SS = 0.8V 5 10 15 µA VCC regulator V CC 5 V VCC load regulation I CC = 5mA 3.5 % Thermal shutdown (6) T SD 170 C Thermal shutdown hysteresis (6) T SD_HYS 20 °C PG rising threshold (VFB/VREF) PG RISING VFB rising 85 90 95 % VFB falling 105 110 115 PG falling threshold (VFB/VREF) PG FALLING VFB falling 79 84 89 % VFB rising 113.5 118.5 123.5 % PG deglitch timer T PG_DEGLITCH PG from low to high 30 µs PG from high to low 50 µs PG output voltage low V PG_LOW I SINK = 2mA 0.2 0.4 V NOTE: 6) Not tested in production, guaranteed by design and characterization.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 6 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VIN=12V, TJ=-40oC to +125oC, unless otherwise noted. -50 -30 -10 10 30 50 70 90 110 130 950 970 990 1010 1030 1050 -50 -30 -10 10 30 50 70 90 110130 -50 -30 -10 10 30 50 70 90110130 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 -50 -30 -10 10 30 50 70 90 110130 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 2.2 2.3 2.4 2.5 2.6 2.7 2.8 1.0 1.1 1.2 1.3 1.4 1.5 100 1.2 1.3 1.4 1.5 1.6 1.7 100 90 90 110 120 130 140 150 160 170 100 110 120 130 140 150

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 7 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN=12V, TJ=-40oC to +125oC, unless otherwise noted. 0.90 0.95 1.00 1.05 1.10 -50 -30 -10 10 30 50 70 90 110130 89.0% 89.5% 90.0% 90.5% 91.0% -50 -30 -10 10 30 50 70 90110130 108% 109% 110% 111% 112% -50 -30 -10 10 30 50 70 90110130 83.0% 83.5% 84.0% 84.5% 85.0% -50 -30 -10 10 30 50 70 90110130 116% 117% 118% 119% 120% -50 -30 -10 10 30 50 70 90 110130 Rising Falling -50 -30 -10 10 30 50 70 90 110 130 797.0 797.5 798.0 798.5 799.0 799.5 800.0 800.5 801.0 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 2.4 2.5 2.6 2.7 2.8 2.9 3.0 Rising Falling 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 8 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, V OUT = 5V, Io=1A, L = 4.7 μH, F SW = 450kHz, with EMI filters, T A = +25°C, unless otherwise noted. (7) CISPR25 Class 5 Peak Conducted Emissions 150kHz -108MHz CISPR25 Class 5 Average Conducted Emissions 150kHz - 108MHz -20 -15 -10 0.1 108 PEAK CONDUCTED EMI (dBuV) Frequency (MHz)11 0 CISPR25 CLASS 5 LIMITS NOISE FLOOR -20 -15 -10 0.1 108 AVERAGE CONDUCTED EMI (dBuV) Frequency (MHz)11 0 CISPR25 CLASS 5 LIMITS NOISE FLOOR CISPR25 Class 5 Peak Radiated Emissions 150kHz-30MHz CISPR25 Class 5 Average Radiated Emissions 150kHz-30MHz -10 0.1 30 PEAK RADIATED EMI (dBuV/m) Frequency (MHz)11 0 CISPR25 CLASS 5 LIMITS NOISE FLOOR -10 0.1 30 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz)11 0 CISPR25 CLASS 5 LIMITS NOISE FLOOR CISPR25 Class 5 Peak Radiated Emissions Horizontal, 30MHz-200MHz CISPR25 Class 5 Average Radiated Emissions Horizontal, 30MHz-200MHz 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 20 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 9 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, V OUT = 5V, Io=1A, L = 4.7 μH, F SW = 450kHz, with EMI filters, T A = +25°C, unless otherwise noted. (7) CISPR25 Class 5 Peak Radiated Emissions Vertical, 30MHz-200MHz CISPR25 Class 5 Average Radiated Emissions Vertical, 30MHz-200MHz 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION CISPR25 Class 5 Peak Radiated Emissions Horizontal, 200MHz-1GHz CISPR25 Class 5 Average Radiated Emissions Horizontal,200MHz-1GHz 200 300 400 500 600 700 800 900 1000 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION 200 300 400 500 600 700 800 900 1000 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR HORIZONTAL POLARIZATION CISPR25 Class 5 Peak Radiated Emissions Vertical, 200MHz-1GHz CISPR25 Class 5 Average Radiated Emissions Vertical,200MHz-1GHz 200 300 400 500 600 700 800 900 1000 PEAK RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION 200 300 400 500 600 700 800 900 1000 AVERAGE RADIATED EMI (dBuV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS NOISE FLOOR VERTICAL POLARIZATION NOTE: 7) The EMC test results are based on the application circuit with EMI filters as shown in Figure14.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 10 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS(continued) VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted. 0 1 02 03 04 05 06 07 08 09 0 1 0 0 500 1,000 1,500 2,000 2,500 3,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0 5 10 15 20 25 30 35 40 1.0 1.5 2.0 2.5 3.0 3.5 -0.10 -0.05 0.00 0.05 0.10 0 0.2 0.4 0.6 0.8 1 0 200 400 600 800 1,000

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 11 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 12 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 13 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted. VOUT/AC 50mV/div. VOUT 2V/div. VSW 10V/div. VIN 5V/div. IL 500mA/div. VSW 5V/div. IL 200mA/div. VOUT 2V/div. VIN 5V/div. VSW 5V/div. IL 1A/div. VOUT 5V/di VIN 2V/di VSW 10V/div. IL 500mA/div. VOUT 2V/div. VIN 5V/div. VSW 5V/div. IL 1A/div. VOUT 2V/div. VEN 2V/div. VSW 10V/div. IL 200mA/div. VOUT 2V/div. VEN 2V/div. VSW 10V/div. IL 1A/div. VOUT/AC 10mV/div. VSW 5V/div. IL 200mA/div. VOUT/AC 5mV/div. VSW 5V/div. IL 500mA/div. VIN VIN VIN VIN

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 14 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 15 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, VOUT=3.3V, L=10µH, FSW=500kHz, AAM, TA=+25oC, unless otherwise noted. VSW 20V/div. 3.3V

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 16 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description

1 PHASE

Selectable in-phase or 180° out-of-phase of SYNC input. Drive PHASE high to be in- phase. Drive PHASE low to be 180° out-of-phase. Recommend to connect this pin to GND if not used.

2 VIN

Input supply. VIN supplies power to all of the internal control circuitries and the power switch connected to SW. A decoupling capacitor to ground must be placed close to VIN to minimize switching spikes. 3, 10 SW Switch node. SW is the output of the internal power switch. Pin 3 and Pin 10 are internally connected. 4, 9 PGND Power ground. PGND is the reference ground of the power device and requires careful consideration during PCB layout. For best results, connect PGND with copper pours and vias. 5 EN Enable. Pull EN below the specified threshold to shut the chip down. Pull EN above the specified threshold to enable the chip.

6 SYNC

Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the internal oscillator frequency to the external clock. The external clock should be at least 250kHz larger than the R FREQ set frequency. SYNC can also be used to select forced continuous conduction mode (CCM) or advanced asynchronous mode (AAM). Before the chip starts up, drive SYNC low or leave SYNC floating to choose AAM, and drive SYNC high to external power source or pull up SYNC to VCC directly to set the part forced CCM mode. 7 PG Power good indicator. The output of PG is an open drain and goes high if the output voltage is within ±10% of the nominal voltage. Float PG if not used.

8 BIAS

External power supply for the internal regulator. Connect BIAS to an external power supply (5V ≤ VBIAS ≤ 18V) to reduce power dissipation and increase efficiency. Float BIAS or connect BIAS to ground if not used. 11 BST Bootstrap. BST is the positive power supply for the high-side MOSFET driver connected to SW. Connect a bypass capacitor between BST and SW. 12 VCC Internal bias supply. VCC supplies power to the internal control circuit and gate drivers. A ≥1µF decoupling capacitor to ground is required close to VCC. 13 AGND Analog ground. AGND is the reference ground of the logic circuit. 14 SS Optional external soft-start time setting. Connect an external capacitor between this pin and GND to set soft-start time externally. The MPQ9841 sources 10µA from SS to the soft-start capacitor during start-up. As the SS voltage rises, the feedback threshold voltage increases to limit inrush current during start-up. Floating the pin will activate the internal 0.7ms soft-start setting.

15 FB VOUT

Feedback input for output adjustable version. Connect FB to the tap of an external resistor divider from the output to AGND to set the output voltage. The feedback threshold voltage is 0.8V. Place the resistor divider as close to FB as possible. Avoid placing vias on the FB traces. Regulated output voltage for fixed output version. Connect VOUT pin to the output directly. 16 FREQ Switching frequency program. Connect a resistor from FREQ to ground to set the switching frequency.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 19 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. enough voltage headroom to facilitate charging. When the HS-FET is on, VIN is about equal to SW, so the bootstrap capacitor cannot be charged. At a higher duty cycle operation condition, the time period available to the bootstrap charging is less, so the bootstrap capacitor may not be charged sufficiently. In case the external circuit does not have sufficient voltage or time to charge the bootstrap capacitor, extra external circuitry can be used to ensure that the bootstrap voltage is in the normal operation region. Low Dropout Operation (BST Refresh) To improve drop out, the MPQ9841 is designed to operate at close to 100% duty cycle for as long as the BST to SW voltage is greater than 2.5V. When the voltage from BST to SW drops below 2.5V, the HS-FET is turned off using an under-voltage lockout (UVLO) circuit, which allows the LS-FET to conduct and refresh the charge on the BST capacitor. In DCM or PSM, the LS-FET is forced on to refresh the BST voltage. Since the supply current sourced from the BST capacitor is low, the HS-FET can remain on for more switching cycles than are required to refresh the capacitor, making the effective duty cycle of the switching regulator high. The effective duty cycle during the dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode, and printed circuit board resistance. Internal Regulator Most of the internal circuitry is powered on by the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5V, the output of the regulator is in full regulation. When VIN is lower than 5V, the output degrades. For better thermal performance, connect BIAS to an external 5V source. VCC and the internal circuit are powered by BIAS. Since there is an internal diode between BIAS and the internal circuit, float BIAS or connect BIAS to GND if it is not being used. Enable Control (EN) EN is a digital control pin that turns the regulator on and off. When EN is pulled below its threshold voltage, the chip is put into the lowest shutdown current mode. Pulling EN above its threshold voltage turns on the part. Do not float EN. Frequency Programmable (FREQ) The MPQ9841 oscillating frequency can be programmed either by an external resistor FREQ) from FREQ to ground or by a logic level SYNC signal. The value of (R FREQ) can be calculated with Equation (1): )kHz(f )kΩ(R . s FREQ 111 170000 (1) The chip can be synchronized to an external clock ranging from 350kHz up to 2.5MHz through FREQ/SYNC. SYNC and PHASE The internal oscillator frequency can be synchronized to an external clock ranging from 350kHz up to 2.5MHz through SYNC. The external clock should be at least 250kHz larger than the R FREQ set frequency. Ensure that the high amplitude of the SYNC clock is higher than 1.8V, and the low amplitude is lower than 0.4V. There is no pulse width requirement, but there is always parasitic capacitance of the pad, so if the pulse width is too short, a clear rising and falling edge may not be seen due to the parasitic capacitance. A pulse longer than 100ns is recommended in application. PHASE is used when two or more MPQ9841 devices are in parallel with the same SYNC clock. Pulling PHASE high forces the MPQ9841 to operate in-phase of the SYNC clock. Pulling PHASE low forces the device to be 180° out-of- phase of the SYNC clock. By setting different voltages for PHASE, two devices can operate 180° out-of-phase to reduce the total input current ripple, so a smaller input bypass capacitor can be used (see Figure 3). The PHASE rising threshold is about 2.5V with a 400mV hysteresis.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev. 1.0 www.MonolithicPower.com 20 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. Figure 3: In-Phase and 180° Out-of-Phase Soft Start (SS) Soft start (SS) is implemented to prevent the converter output voltage from overshooting during start-up. When the chip starts up, an internal current source begins charging the external soft-start capacitor. The internal SS voltage (V SSI) rises with the soft-start voltage (VSS), but VSSI is a little different with V SS due to a 0.5V offset and some delay. When V SS is lower than 0.5V, VSSI is 0V. VSSI rises from 0V to 0.8V during the period of VSS rising from 0.5V to 1.6V. At this time the error amplifier uses V SSI as the reference, so the output voltage ramps up from 0V to the regulated value following V SSI rising. When VSS reaches 1.6V, VSSI is 0.8V and overrides the internal V REF, so the error amplifier uses the internal V REF as the reference. The soft-start time (t SS) set by the external SS capacitor can be calculated with Equation (2):   SS SS SS C( n F )1 . 1 Vt( m s ) I( A ) (2) Where CSS is the external SS capacitor, and I SS is the internal 10μA SS charge current. There is also an internal fixed 700us soft start. The final SS time is determined by the longer time between 700us and the external SS setting time. SS can be used for tracking and sequencing. Pre-Bias Start-Up At start-up, if V FB is higher than V SSI-150mV, which means the output has a pre-bias voltage, neither the HS-FET nor the LS-FET are turned on until V SSI-150mV is higher than VFB. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from running away thermally. When the silicon die temperature is higher than its upper threshold, the power MOSFETs are shut down. When the temperature is lower than its lower threshold, thermal shutdown is removed and the chip is enabled again. Current Comparator and Current Limit The power MOSFET current is accurately sensed via a current sense MOSFET. The current is then fed to the high-speed current comparator for current-mode control purposes. The current comparator takes this sensed current as one of its inputs. When the HS-FET is turned on, the comparator is first blanked until the end of the turn-on transition to avoid noise. Then the comparator compares the power switch current with V COMP. When the sensed current is higher than V COMP, the comparator outputs low to turn off the HS-FET. The maximum current of the internal power MOSFET is limited cycle-by-cycle internally. Hiccup Protection When the output is shorted to ground, causing the output voltage to drop below 55% of its nominal output, the IC is shut down momentarily and begins discharging the soft- start capacitor. The IC restarts with a full soft start when the soft-start capacitor is fully discharged. This hiccup process is repeated until the fault is removed. Start-Up and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current, and then the internal regulator is enabled. The regulator provides a stable supply for the rest of the circuitries. While the internal supply rail is up, an internal timer holds the power MOSFET off for about 50µs to blank any start-up glitches. When the soft-start block is enabled, the SS output is held low to ensure that the rest of the circuitries are ready before slowly ramping up. Three events can shut down the chip: EN low, VIN low, and thermal shutdown. In the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. V COMP and the internal supply rail are then pulled down.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev. 1.0 www.MonolithicPower.com 21 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. The floating driver is not subject to this shutdown command, but its charging path is disabled. Power Good (PG) Output The MPQ9841 includes an open-drain power good (PG) output that indicates whether the regulator output is within ±10% of its nominal output range. When the output voltage moves outside of this range, the PG output is pulled to ground.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 22 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

APPLICATION INFORMATION

Setting the Output Voltage The external resistor divider connected to FB sets the output voltage (see Figure 4). Figure 4: Feedback Network Choose R FB1 first, R FB2 can then be calculated with Equation (3): 0.8V V RR OUT FB1 FB2 (3) Table 1 lists the recommended feedback resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) R FB1 (kΩ) R FB2 (kΩ) For fixed output version, connect VOUT pin to the output directly. Selecting the Inductor A 1µH to 10µH inductor with a DC current rating at least 25% higher than the maximum load current is recommended for most applications. For higher efficiency, choose an inductor with a lower DC resistance. A larger-value inductor results in less ripple current and a lower output ripple voltage, but also has a larger physical size, higher series resistance, and lower saturation current. A good rule for determining the inductor value is to allow the inductor ripple current to be approximately 30% of the maximum load current. The inductance value can then be calculated with Equation (4): OUT OUT SW L IN VVL( 1 )fI V (4) Where ∆IL is the peak-to-peak inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (5): OUT OUT LP LOAD SW IN VVII ( 1 ) 2f L V (5) Selecting the Input Capacitor The input current to the step-down converter is discontinuous and therefore requires a capacitor to supply AC current to the converter while maintaining the DC input voltage. For the best performance, use low ESR capacitors. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most application, use a 4.7µF to 10µF capacitor. It is strongly recommended to use another lower-value capacitor (e.g.: 0.1µF) with a small package size (0603) to absorb high- frequency switching noise. Place the smaller capacitor as close to VIN and GND as possible. Since C IN absorbs the input switching current, it requires an adequate rippl e current rating. The RMS current in the input capacitor can be estimated with Equation (6):    OUT OUT CIN LOAD IN IN VVII ( 1 ) VV (6) The worst-case condition occurs at VIN = 2V OUT, shown in Equation (7):  LOAD CIN II 2 (7) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high-quality ceramic capacitor (e.g.: 0.1 μF) as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at the input.

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 24 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PCB Layout Guidelines (8) Efficient PCB layout is critical for stable operation, especially for the input capacitor placement. A four-layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 7 and follow the guidelines below. 1. Use a large ground plane to connect directly to PGND. Recommend to connect pin1 to GND for symmetric input structure if in-phase not used. Pin3 and pin10 are internally connected. Connecting together on layout or not are both OK. Recommend to leave pin3 floating for shorter pin4 and pin1 trace and smaller input hot loop. 2. Add vias near PGND if the bottom layer is a ground plane. 3. Ensure that the high-current paths at GND and VIN have short, direct, and wide traces. 4. Place the ceramic input capacitors, especially the small package size (0603) input bypass capacitor, as close to VIN and PGND as possible to minimize high- frequency noise. 5. Keep the connection of the input capacitor and VIN as short and wide as possible. 6. Place the VCC capacitor as close to VCC and GND as possible. 7. Route SW and BST away from sensitive analog areas such as FB. 8. Place the feedback resistors close to the chip to ensure that the trace connecting to FB is as short as possible. 9. Use multiple vias to connect the power planes to the internal layers. NOTE: 8) The recommended PCB layout is based on Figure 8. Top Layer Inner Layer 1 Inner Layer 2 Bottom Layer Figure 7: Recommended PCB Layout

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 29 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 10μF C1A 0.1μF C1C 100kΩ R1 0.1μF 10μH 22μF C2A 5V/1A EN VOUT 10μF C1B SW 3, 10EN5 VIN2 VOUT 15VCC12 BST 11 PGND 4, 9 PG7 1μF 100kΩ PG GND VIN GND 3.3V-36V MPQ9841 14SS AGND 16FREQ BIAS SYNC6 PHASE1 8 4.7nF SYNC PHASE 169kΩ 22μF C2B 0.1μF C1D 0.1µF 10Ω Figure 16: 5V Fixed Output, FSW = 500kHz

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 MPQ9841 Rev.1.02 www.MonolithicPower.com 30 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-16 (3mmx4mm) Non-Wettable Flank

MPQ9841 – 36V, 1A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100 NOTICE: The information in this document is subject to change wi thout notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ9841 Rev.1.02 www.MonolithicPower.com 31 5/10/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PACKAGE INFORMATION (continued) QFN-16 (3mmx4mm) Wettable Flank

Summary

36V, 1A, Low IQ, Synchronous Step-Down Converter AEC-Q100 Qualified 5/10/2019 Rev.1.02

Description