MPQ8633BGLE-Z

MPQ8633B_V01 MPS | Alldatasheet

Document overview

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Technical content

MPQ8633B 16V, 20A, Synchronous, Step-Down Converter with Adjustable Current Limit, Programmable Frequency, and Voltage Tracking MPQ8633B Rev. 1.1 www.MonolithicPower.com 1 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

DESCRIPTION

The MPQ8633B is a fully integrated, high - frequency, synchronous , buck converter. It offers a very compact solution that achieves up to 20A of output current with excellent load and line regulation over a wide input supply range . The MPQ8633B operates at high efficiency over a wide output current load range. The MPQ8633B adopts an internally compensated constant-on-time (COT) control mode that provides fast transient response and eases loop stabilization. The operating frequency can be set to 600kHz, 800kHz, or 1000kHz easily with MODE configuration, allowing the MPQ8633B frequency to remain constant regardless of the input and output voltages. The output voltage start -up ramp is controlled by an internal 1ms timer. It can be increased by adding a capacitor on TRK/REF. An open -drain power good (PGOOD) signal indicates if the output is within its nominal voltage range. PGOOD is clamped at around 0.7V with an external pull -up voltage when the input supply fails to power the MPQ8633B. Full protection features include over-current protection ( OCP), over-voltage protection (OVP), under-voltage protection ( UVP), and over-temperature protection (OTP). The MPQ8633B requires a minim al number of readily available, standard, external components and is available in a QFN -21 (3mmx4mm) package.

FEATURES

• Wide Input Voltage Range o 2.7V to 16V with External 3.3V VCC Bias o 4V to 16V with Internal Bias or External 3.3V VCC Bias
• Differential Output Voltage Remote Sense
• Programmable Accurate Current Limit Level
• 20A Output Current
• Low RDS(ON) Integrated Power MOSFETs
• Proprietary Switching Loss Reduction Technique
• Adaptive COT for Ultrafast Transient Response
• Stable with Zero ESR Output Capacitor
• 0.5% Reference Voltage over 0°C to +70°C Junction Temperature Range
• 1% Reference Voltage from -40°C to +125°C Junction Temperature Range
• Selectable Pulse Skip or Forced CCM Operation
• Excellent Load Regulation
• Output Voltage Tracking
• Output Voltage Discharge
• PGOOD Active Clamped at Low Level during Power Failure
• Programmable Soft-Start Time from 1ms
• Pre-Bias Start-Up
• Selectable Switching Frequency from 600kHz, 800kHz, and 1000kHz
• Non-Latch OCP, UVP, UVLO, Thermal Shutdown, and Latch-Off for OVP
• Output Adjustable from 0. 6V to 90%* VIN, up to 5.5V Max
• Available in a QFN -21 (3mmx4mm) Package

APPLICATIONS

• Telecom and Networking Systems
• Servers, Cloud-Computing, Storage
• Base Stations
• General Purpose Point-of-Load (PoL)
• 12V Distribution Power Systems
• High-end TV
• Game Consoles and Graphic Cards All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 2 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL APPLICATION EN FB BSTVIN SW MPQ8633B COUT1 RCS EN PG VIN VOUT VOSENSE+ VOSENSE - CIN3 CIN2 CIN1 CVCC Cff RFB1 RFB2 CSS1 CSS2 CBST RMODE COL RGND RFF RPG CPG

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 3 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number Package Top Marking MPQ8633BGLE* QFN-21 (3mmx4mm) See Below * For Tape & Reel, add suffix –Z (e.g. MPQ8633BGLE–Z) TOP MARKING MP: MPS prefix Y: Year code W: Week code 8633B: First five digits of the part number LLL: Lot number E: MPQ8633BGLE PACKAGE REFERENCE TOP VIEW PGND VCC CS AGND MODE EN TRK/REF FB RGND PGOOD BST PGND PGND PGND PGND PGND PGND PGND SW VIN VIN QFN-21 (3mmx4mm)

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 4 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Recommended Operating Conditions (3) Thermal Resistance (4) θJB θJC_TOP NOTES: 1) Exceeding these ratings may damage the device. 2) Measured using a differential oscilloscope probe. 3) The device is not guaranteed to function outside of its operating conditions. 4) θJB is the thermal resistance from the junction to the board around the PGND soldering point. θJC_TOP is the thermal resistance from the junction to the top of the package.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 5 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Supply Current Supply current (shutdown) IIN VEN = 0V 0 10 μA Supply current (quiescent) IIN VEN = 2V, VFB = 0.62V 650 850 μA MOSFET Switch leakage SWLKG_HS VEN = 0V, VSW = 0V 0 10 μA SWLKG_LS VEN = 0V, VSW = 12V 0 30 HS on-state resistance RDS_ON_HS VEN = 2V @ 25oC 8.6 mΩ LS on-state resistance RDS_ON_LS VEN = 2V @ 25oC 2.5 mΩ Current Limit Current limit threshold VLIM 1.15 1.2 1.25 V ICS to IOUT ratio ICS/IOUT IOUT ≥ 2A 9 10 11 μA/A Low-side negative current limit ILIM_NEG -10 A Negative current limit time out6) tNCL_Timer 200 ns Switching Frequency Switching frequency (6) fSW MODE = GND, IOUT = 0A, VOUT = 1V 480 600 720 kHz MODE = 30.1kΩ, IOUT = 0A, VOUT = 1V 680 800 920 kHz MODE = 60.4 kΩ, IOUT = 0A, VOUT = 1V 850 1000 1150 kHz Minimum on time (5) TON_MIN VFB = 500mV 50 ns Minimum off time (5) TOFF_MIN VFB = 500mV 180 ns Over-Voltage and Under-Voltage Protection OVP threshold VOVP 113% 116% 119% VREF UVP threshold VUVP 77% 80% 83% VREF Feedback Voltage and Soft Start Feedback voltage VREF TJ = -40°C to +125°C 594 600 606 mV TJ = 0°C to +70°C 597 600 603 mV TRK/REF sourcing current ITRACK_Source VTRK/REF = 0V 42 μA TRK/REF sinking current ITRACK_Sink VTRK/REF = 1V 12 μA Soft-start time tSS CTRACK = 1nF, TJ = +25°C 0.75 1 1.25 ms Error Amplifier Error amplifier offset VOS -3 0 3 mV Feedback current IFB VFB = REF 50 100 nA

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 6 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Enable and UVLO Enable input rising threshold VIHEN 1.17 1.22 1.27 V Enable hysteresis VEN-HYS 200 mV Enable input current IEN VEN = 2V 0 μA Soft shutdown discharge FET RON_DISCH 80 150 Ω VIN UVLO VIN under-voltage lockout threshold rising VINVth_Rise VCC = 3.3V 2.1 2.4 2.7 V VIN under-voltage lockout threshold falling VINvth_Fall 1.55 1.85 2.15 VCC Regulator VCC under-voltage lockout threshold rising VCCVth_Rise 2.65 2.8 2.95 V VCC under-voltage lockout threshold falling VCCvth_Fall 2.35 2.5 2.65 V VCC regulator VCC 2.88 3.00 3.12 V VCC load regulation Icc = 25mA 0.5 % Power Good Power good high threshold PGVth_Hi_Rise FB from low to high 89.5% 92.5% 95.5% VREF Power good low threshold PGVth_Lo_Rise FB from low to high 113% 116% 119% VREF PGVth_Lo_Fall FB from high to low 77% 80% 83% VREF Power good low to high delay PGTd TJ = 25°C 0.63 0.9 1.17 ms Power good sink current capability VPG IPG = 10mA 0.5 V Power good leakage current IPG_LEAK VPG = 3.3V 3 µA Power good low-level output voltage VOL_100 VIN = 0V, pull PGOOD up to 3.3V through a 100kΩ resistor @ 25oC 650 800 mV VOL_10 VIN = 0V, pull PGOOD up to 3.3V through a 10kΩ resistor @ 25oC 750 900 mV Thermal Protection Thermal shutdown (5) TSD 160 °C Thermal shutdown hysteresis (5) 30 °C NOTE: 5) Guaranteed by design. 6) Guaranteed by design over temperature.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 7 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, TA = 25˚C, VOUT = 1V, FS = 800kHz unless otherwise noted.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 8 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, TA = 25˚C, VOUT = 1V, FS = 800kHz unless otherwise noted.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 9 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, TA = 25˚C, VOUT = 1V, FS = 800kHz unless otherwise noted.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 10 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, TA = 25˚C, VOUT = 1V, FS = 800kHz unless otherwise noted.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 11 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. PIN FUNCTIONS QFN-21 PIN # Name Description 1 BST Bootstrap. Connect a capacitor between SW and BS to form a floating supply across the high-side switch driver. 2 AGND Analog ground. Select AGND as the control circuit reference point. 3 CS Current limit. Connect a resistor to AGND to set the current limit trip point. See equation 4 for additional details. 4 MODE Operation mode se lection. Program MODE to select CCM, pulse skip mode, and the operating switching frequency. See Table 1 for additional details.

5 TRK/REF

External tracking voltage input. The output voltage tracks this input signal. Decouple TRK/REF with a ceramic capaci tor placed as close to it as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. The capacitance of this capacitor determines the soft - start time. See Equation 2 and 3 for additional details.

6 RGND

Differential remote sense negative input. Connect RGND to the negative side of the voltage sense point directly. Short RGND to GND if the remote sense is not used. 7 FB Feedback (differential remote sense positive input). An external resistor d ivider from the output to RGND tapped to FB sets the output voltage. It is recommended to place the resistor divider as close to FB as possible. Vias should be avoided on the FB traces. 8 EN Enable. EN is an input signal that turns the regulator on or off. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. Connect EN to VIN through a pull-up resistor or a resistive voltage divider for automatic start-up. Do not float EN.

9 PGOOD

Power good output. PGOOD is an open-drain signal. A pull-up resistor connected to a DC voltage is required to indicate a logic high signal if the output voltage is within regulation. There is a delay of about 1ms between the time FB ≥ 92.5% and PGOOD pulling high. 10, 21 VIN Input voltage. VIN supplies power for the internal MOSFET and regulator. Input capacitors are needed to decouple the input rail. Use wide PCB traces to make the connection. 11-18 PGND System ground. PGND is the reference ground of the regulated output voltage. Therefore, care must be taken during PCB layout. Use wide PCB traces to make the connection.

19 VCC

Internal 3V LDO output. The driver and control circuits are powered from the VCC voltage. Decouple VCC with a ceramic capacitor at least 1µF placed as close to it as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 20 SW Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to VIN by the high -side switch during the on -time of the PWM duty cycle. The inductor current drives SW low during the off -time. Use wide PCB traces to make the connection.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 12 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. BLOCK DIAGRAM VCC EN Reference 3V LDO System Monitor MODE Select TRK/REF RGND FB Error Amplifier PWM Comparator PGOOD Comparator PGOOD Ramp On Timer MODE HS Driver LS Driver SW Logic Control BST REG BST IN PGND Valley Current Limit & ZCD HSG HSG LSG LSG CS ZCD xS xR Q Off Timer OV Detect Comparator UV Detect Comparator xLIM FAULT OV_TH UV_TH OV_TH UV_TH Figure 1: Functional Block Diagram

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 15 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. Output Voltage Tracking and Reference The MPQ8633B provides an analog input pin (TRK/REF) to track another power supply or accept an external reference. When an external voltage signal is connected to TRK/REF, it acts as a reference for the MPQ8633B output voltage. The FB voltag e follows this external voltage signal exactly, and the soft -start settings are ignored. The TRK/REF input signal can be in the range of 0.3V to 1.4V. During the initial start-up, the TRK/REF must reach at least 600mV first to ensure proper operation. Afte r that, it can be set to any value between 0.3V and 1.4V. Pre-Bias Start-Up The MPQ8633B is designed for monotonic start-up into pre -biased loads. If the output is pre-biased to a certain voltage during start -up, the IC disable s switching for both the HS-FET and LS-FET until the voltage on the TRK/REF capacitor exceeds the sensed output voltage at FB. Before the TRK/REF voltage reaches the pre-biased FB level, if the BST voltage (from BST to SW) is lower than 2.3V, the LS -FET is turned on to allow the BST voltage to be charged through VCC. The LS-FET is turned on for very narrow pulses, so the drop in the pre- biased level is negligible. Output Voltage Discharge When the MPQ8633B is disabled through EN, output voltage discharge mode is enabled. This causes b oth the HS -FET and the LS -FET to latch off. A discharge FET connected between SW and PGND is turned on to discharge the output voltage. The typical switch on r esistance of this FET is about 8 0Ω. Once the FB voltage drops below 10%*REF, the discharge FET is turned off. Current Sense and Over -Current Protection (OCP) The MPQ8633B features an on-die current sense and a programmable positive current limit threshold. The current limit is active when the MPQ8633B is enabled. During the LS-FET on state, the SW current (inductor current) is sensed and mirrored to CS with the ratio of G CS. By using a resistor (RCS) from CS to AGND, the V CS voltage is proportional to the SW current cycle - by-cycle. The HS-FET is only allowed to turn on when V CS is below the intern al OCP voltage threshold (VOCP) during the LS -FET on state to limit the SW valley current cycle-by-cycle. Calculate the current limit threshold setting from RCS with Equation (4): OCP CS IN O O CS LIM IN s VR ( ) (V V ) V 1G (I ) V 2 L f (4) Where VOCP = 1.2V, GCS = 10µA/A, and ILIM is the desired output current limit (A). The OCP hiccup is active 3ms after the MPQ8633B is enabled . Once OCP hiccup is active, if the MPQ8633B detects the over- current condition for 31 consecutive cycles, or if FB drops below the under-voltage protection (UVP) th reshold, it enters hiccup mode. In hiccup mode, the MPQ8633B latches off the HS-FET immediately, and latches off the LS- FET after ZCD is detected. Meanwhile, the TRK/REF capacitor is also discharged. After about 11ms, the MPQ8633B attempts to soft start automatically. If the over -current condition still remains after 3ms of running, the MPQ8633B repeats this operation cycle until the over -current condition disappears, and the output voltage rises back to the regulation level smoothly. Negative Inductor Current Limit When the LS-FET detects a -10A current, the MPQ8633B turns off the LS-FET for 200ns to limit the negative current. Output Sinking Mode (OSM) The MPQ8633B employs output sinking mode (OSM) to regulate the output voltage to the targeted value. Whe n the FB voltage is higher than 10 4%*REF but is below the OVP threshold, OSM is triggered . During OSM operation, the LS-FET remains on until it reaches the -9A current limit. The LS-FET is then turned off momentarily for 200ns before turning on again. The MPQ8633B repeats this operation until FB drops below 102%*REF. The MPQ8633B exits OSM after 15 consecutive cycles of forced CCM.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 16 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. Over-Voltage Protection (OVP) The MPQ8633B monitors the output voltage by connecting FB to the tap of the output voltage feedback resistor divide r to detect an over- voltage condition. This provides latch -off OVP mode. If the FB voltage exceeds 1 16% of the REF voltage, the MPQ8633B enters latch-off OVP mode. The HS -FET latches off and PGOOD latches low until VCC or EN is recycled (turned off and turned on again) . Meanwhile, the LS - FET remains on until it reaches the low -side negative current limit (NOCP). The LS-FET is then turned off momentarily for 200ns before turning on again. The MPQ8633B repeats this operation to attempt to b ring down the output voltage. When the FB voltage drops below 50% of the REF voltage, the LS -FET is turned off for pulse skip mode and continues turning on for forced CCM operation. If FB rises higher than 116% of the REF voltage again, the LS -FET turns on again with NOCP until FB drops back below 50% of the REF voltage. The MPQ8633B needs EN or VIN to recycle to clear the OVP fault. The OVP function is enabled after TRK/REF reaches 600mV. Over-Temperature Protection (OTP) The MPQ8633B has over-temperature protection (OTP). The IC monitor s the junction temperature internally. If the junction temperature exceeds the threshold value (typically 160°C), the converter shuts off and discharges the TRK/REF capacitors . This is a non-latch protection. There is a hyst eresis of about 30°C. Once the junction temperature drops to about 130°C, a soft start is initiated . The OTP function is effective once the MPQ8633B is enabled. Output Voltage Setting and Remote Output Voltage Sensing First, choose a value for RFB1. Then RFB2 can be determined with Equation (5): REF FB2 FB1 O REF VR (k ) R (k )VV =  − (5) To optimize the load transient response, a feed- forward capacitor (C FF) is recommended to be placed in parallel with RFB1. RFB1 and CFF add an extra zero t o the system, which improves loop response. RFB1 and CFF are selected so that the zero formed by R FB1 and CFF is located around 5kHz to 40kHz. Calculate this zero with Equation (6): Z FB1 FF 1f 2 R C=   (6) Power Good (PGOOD) The MPQ8633B has a power good ( PGOOD) output. PGOOD is the open -drain of a MOSFET. Connect PGOOD to VCC or another external voltage source less than 3.6V through a pull-up resistor (typically 10kΩ). After applying the input voltage, the MOSFET turn s on, so PGOOD is pulled to GND before TRK/REF is ready. After the FB voltage reaches 9 2.5% of the REF voltage, PGOOD is pulled high after a 0.8ms delay. When the FB voltage drops to 80% of the REF voltage, or exceeds 116% of the nominal REF voltage, PGOOD is latched low. PGOOD can only be pulled high again after a new SS. If the input supply fails to power the MPQ8633B, PGOOD is clamped low, even though PGOOD is tied to an external DC source through a pull- up resistor. The relationship between the PGOOD voltage and the pull -up current is shown in Figure 5.

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 18 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

APPLICATION INFORMATION

The input current to the step -down converter is discontinuous and t herefore requires a capacitor to supply AC current to the step -down converter while maintaining the DC input voltage. Use c eramic capacitors for the best performance. During layout, place the input capacitors as close to VIN as possible. The capacitance can vary significantly with temperature. Capacitors with X5R and X7R ceramic dielectrics are recommended because they are fairly stable over a wide temperature range and offer very low ESR. The capacitors must have a ripple current rating that exceeds the converter’s maximum input ripple current. Estimate t he input ripple current with Equation (9): V1(V VII IN OUT IN OUT OUTCIN −= (9) The worst-case condition occurs at V IN = 2VOUT, shown in Equation (10): II OUT CIN = (10) For simplific ation, choose an input capacitor with an RMS current rating that exceeds half the maximum load current. The input capacit or value determines the converter input voltage ripple. If there is an input voltage ripple requirement in the system, s elect an input capacitor that meets the specification. Estimate the input voltage ripple with Equation (11): V1(V V CF IV IN OUT IN OUT INSW OUT (11) The worst-case condition occurs at V IN = 2VOUT, where: INSW OUT IN CF I 1V = (12) Output Capacitor The output capacitor maintains the DC output voltage. Use POSCAP or ceramic capacitors . Estimate the output voltage ripple with Equation (13): )CF8 1R()V V1(LF VV OUTSW ESR IN OUT SW OUT OUT (13) When using ceramic capacitors, the capacitance dominates the impedance at the switching frequency. The capacitance also dominates the output voltage ripple. For simplification, estimate the output voltage ripple with Equation (14): V1( CLF8 VV IN OUT OUT SW OUT OUT −  (14) For simplification, the output ripple can be approximated with Equation (15): ESR IN OUT SW OUT OUT R)V V1(LF (15) Inductor The inductor supplies a constant current to the output load while being driven by the switching input voltage. A larger value inductor result s in less ripple current and lower output ripple voltage, but also has a larger physical size, a higher series resistance, and a lower saturation current. Generally, select an inductor value that allows the inductor peak-to-peak ripple current to be 30% to 40% of the max imum switch current limit. Also design for a peak inductor current that is below th e m aximum switch current limit. Calculate t he inductance value with Equation (16): V1(IF VL IN OUT LSW OUT −= (16) Where ∆IL is the peak -to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The pea k inductor current can be calculated with Equation (17): V1(LF2 VII IN OUT SW OUT OUTLP −+= (17)

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 19 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. PCB Layout Guidelines Efficient PCB layout is critical for stable operation. For best performance, refer to Figure 8 and follow the guidelines below. 1. Place the input MLCC capacitors as close to VIN and PGND as possible. 2. Place the major MLCC capacitors on the same layer as the MPQ8633B. 3. Maximize the VIN and PGND copper plane to minimize the parasitic impedance. 4. Place as many PGND vias as possible as close to PGND as possible to minimize both parasitic impedance and thermal resistance. 5. Place the VCC decoupling capacitor close to the device. 6. Connect AGND and PGND at the point of the VCC capacitor's ground connection. 7. Place the BST capacitor as close to BST and SW as possible with 20 mil or wider traces to route the path. It is recommended to use a bootstrap capacitor 0.1µF to 1µF. 8. Place the REF capacitor close to TRK/REF to RGND. 9. Place via at least 10mm away from the positive side of the first input decoupli ng capacitor close to the IC if it must be placed on the PGOOD pad. 10. Place COL between the output sense lines and close to the device. It is recommended to use a 1nF to 100nF capacitor. 11. Do not place vias on the VOSENSE+/- trace. 12. Use a 10Ω to 49.9Ω resistor for R PG and a 1nF capacitor for CPG. 13. It is recommended for the feed-forward resistor (RFF) to be 1/10 of the top feedback resistor (RFB1). SW PGND PGND VCC CS AGND MODE EN REF/TRK FB RGND BST PGND PGND PGND PGND PGND PGND PGND SW VIN VIN VOUTPGND VIN VO- RFB2 CFF RFB1 CSS1 CSS2 VOSENSE + VOSENSE - CVCC CIN3 CIN2 CIN1 PGOOD VIN RGND COL RFF PGND CPG RPG Figure 8: Recommended PCB Layout

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING MPQ8633B Rev. 1.1 www.MonolithicPower.com 20 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-21 (3mmx4mm) SIDE VIEW BOTTOM VIEW NOTE: 1) LAND PATTERN OF PIN1,9,10,11,19,20 AND 21 HAVE THE SAME WIDTH. 2) ALL DIMENSIONS ARE IN MILLIMETERS. 3) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 4) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-220. 6) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID

0.15 X 45° TYP

0.15 X 45°

MPQ8633B – 16V, 20A, SYNCHRONOUS, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT, PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING NOTICE: The information in this document is subject to change without notice. Users should warrant a nd guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ8633B Rev. 1.1 www.MonolithicPower.com 21 3/26/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 07/27/2016 Initial Release - 1.01 08/03/2017 Updated and edited the Electrical Characteristics table All 1.02 03/01/2018 Updated the PG low level output voltage parameter 6 Updated the PG Clamped Voltage vs. Current curve 15 1.03 11/2/2018 Added more applications to the Applications section 1 Updated the plot scale for VOUT Load Regulation 7 Added Equation (3) 14 1.1 3/26/2024 Updated Typica l Application section (desig ns on PGOOD, VCC, FB, and RGND):

• Added RPG and CPG to PGOOD
• Added RGND to VCC
• Added RFF to FB
• Added COL to from RFB1 to RGND Updated Absolute Maximum Ratings section:
• Deleted VSW(DC), VSW (25ns), VSW (25ns), and VBST
• Added VIN - VSW (DC), VIN - VSW (25ns), VSW (DC), VSW (25ns), and VBST, VBST - VSW (25ns)
• Updated Recommended Operating Conditions: o VIN(DC) - VSW(DC), VSW(DC)
• Updated Thermal Resistance (5) to Thermal Resistance (4)
• Deleted the original note 4; note 5 became note 4 Updated Notes 6 and 7 to Notes 5 and 6, respectively 5–6 Updated the Output Voltage Setting and R emote Output Voltage Sensing section by changing the fz range from “20~60kHz” to “5kHz to 40kHz”
• Added the Enable (EN) Thre sholds section and the Power Sequence with External VCC Bias section
• Added Figure 6 and Figure 7 Updated the PCB layout Guidelines section:
• Deleted step 10: “Place the OSENSE capacitor in between the output sense lines and close to the device.”
• Added step 10. “Place COL between the output sense lines and close to the device. It is recommended to use a 1nF to 100nF capacitor."
• Added s tep 11: “Do not place vias on the VOSENSE+/- trace.”
• Added step 12: “Use a 10Ω to 49.9Ω f or resistor for RPG and a 1nF capacitor for CPG."
• Added step 13: “It is recommended for the feed - forward resistor (R FF) to be 1/10 of the top feedback resistor (RFB1).”
• Updated Figure 6 to Figure 8 and made additional changes