MPQ8632-8 MPS | Alldatasheet
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Technical content
High Efficiency 18V Synchronous Step-down Converter Family for 4A to 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 1 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. Part Number Current Rating (A) Input Voltage OVP Mode MPQ8632GLE-4 4 2.5V to 18V Non-Latch MPQ8632GLE-6 6 2.5V to 18V Non-Latch MPQ8632GLE-8 8 2.5V to 18V Non-Latch MPQ8632HGLE-10 10 2.5V to 18V Non-Latch MPQ8632GLE-10 10 2.5V to 18V Latch-Off MPQ8632GLE-12 12 2.5V to 18V Non-Latch MPQ8632GVE-15 15 2.5V to 18V Non-Latch MPQ8632GVE-20 20 2.5V to 18V Non-Latch
DESCRIPTION
The MPQ8632 is a fully integrated high frequency synchronous rectified step-down switch mode converter. It offers a very compact solution to achieve 4A/6A/8A/10A/12A/15A/20A output current over a wide input supply range with excellent load and line regulation. The MPQ8632 uses Constant-On-Time (COT) control mode to provide fast transient response and ease loop stabilization. An external resistor programs the o perating frequency from 200kHz to 1MHz and the frequency keeps nearly constant as input supply varies with the feedforward compensation. The default u nder voltage lockout threshold is internally set at 4.1V, but a resistor network on the enable pin can increase this threshold. The soft start pin controls the output voltage startup ramp. An open drain power good signal indicates that the output is within nominal voltage range. It has f ully integrated protection features that include over-current protection , over-voltage protection and thermal shutdown. The MPQ8632 require s a minim al number of readily available standard external components and is available in a 16-Pin QFN 3mm×4mm or a 29-Pin QFN 5mm×4mm package.
FEATURES
Low Input Voltage Range from 2.5V: -- 2.5V to 18V with External 5V Bias -- 4.5V to 18V with Internal Bias Scalable Family of Products for 4A to 20A Output Current Applications -- 4A/6A/8A/10A/12A Share the Same Footprint --15A/20A Share the Same Footprint, with Slight Change on Power Stage Section from 4A/6A/8A/10A/12A Optimal Low RDS(ON) Internal Power MOSFETs Per Device Proprietary Switching Loss Reduction Technique Adaptive COT for Ultrafast Transient Response 0.5% Reference Voltage Over 0C to 70C Junction Temperature Range Programmable Soft Start Time Pre-Bias Start up Programmable Switching Frequency from 200kHz to 1MHz Non-latch OCP, OVP and Thermal Shutdown Protection Output Adjustable from 0.611V to 13V
APPLICATIONS
Telecom and Networking Systems Base Stations Servers Personal Video Recorders Flat Panel Television and Monitors Distributed Power Systems All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 2 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL APPLICATION IN FREQ VCC EN PGND BST FB SW MPQ8632 VIN ON/OFF C1 RFREQ C3 L1 R4 C4 PG AGND SS VOUT
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 3 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number Package Top Marking MPQ8632GLE-4* QFN(3X4mm) MP8632 MPQ8632GLE-6 QFN(3X4mm) MP8632 MPQ8632GLE-8 QFN(3X4mm) MP8632 MPQ8632GLE-10 QFN(3X4mm) MP8632 E10 MPQ8632HGLE-10 QFN(3X4mm) MP8632H E10 MPQ8632GLE-12 QFN(3X4mm) MP8632 E12 MPQ8632GVE-15 QFN(5X4mm) MP8632 E15 MPQ8632GVE-20 QFN(5X4mm) MP8632 E20 * For Tape & Reel, add suffix –Z (e.g. MPQ8632GLE–4–Z) PACKAGE REFERENCE TOP VIEW FB BST VCC PG AGND SS FREQ EN VIN PGND PGND VIN PGND PGND SW SW 11 12 TOP VIEW FB BST VCC PG AGND SS FREQ EN VIN PGND PGND VIN PGND PGND SW SW 11 12 Part Number* Package Part Number* Package MPQ8632GLE-4 QFN (3x4mm) MPQ8632GLE-6 QFN (3x4mm) Junction Temperature Top Marking Junction Temperature Top Marking –40C to +125C MP8632 E4 –40C to +125C MP8632 * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-4–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-6–Z)
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 4 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TOP VIEW FB BST VCC PG AGND SS FREQ EN VIN PGND PGND VIN PGND PGND SW SW 11 12 TOP VIEW FB BST VCC PG AGND SS FREQ EN VIN PGND PGND VIN PGND PGND SW SW 11 12 Part Number* Package Part Number* Package MPQ8632GLE-8 QFN (3x4mm) MPQ8632GLE-10 QFN (3x4mm) Junction Temperature Top Marking Junction Temperature Top Marking –40C to +125C MP8632 E8 –40C to +125C MP8632 E10 * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-8–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-10–Z) TOP VIEW FB BST VCC PG AGND SS FREQ EN VIN PGND PGND VIN PGND PGND SW SW 11 12 TOP VIEW FB BST VCC PG AGND SS FREQ EN VIN PGND PGND VIN PGND PGND SW SW 11 12 Part Number* Package Part Number* Package MPQ8632HGLE-10 QFN (3x4mm) MPQ8632GLE-12 QFN (3x4mm) Junction Temperature Top Marking Junction Temperature Top Marking –40C to +125C MP8632H E10 –40C to +125C MP8632 E12 * For Tape & Reel, add suffix –Z (eg. MPQ8632HGLE-10–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-12–Z)
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 5 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TOP VIEW 1EN 12 13 FREQ FB SS AGND PG VCC BST PGND IN IN PGND PGND PGND PGND PGND PGND SW PGND PGND PGND SW SW SW SW SW SW SW SW TOP VIEW 1EN 12 13 FREQ FB SS AGND PG VCC BST PGND IN IN PGND PGND PGND PGND PGND PGND SW PGND PGND PGND SW SW SW SW SW SW SW SW Part Number* Package Part Number* Package MPQ8632GVE-15 QFN (5x4mm) MPQ8632GVE-20 QFN (5x4mm) Junction Temperature Top Marking Junction Temperature Top Marking –40C to +125C MP8632 E15 –40C to +125C MP8632 E20 * For Tape & Reel, add suffix –Z (eg. MPQ8632GVE-15–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GVE-20–Z)
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 6 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Enable Current IEN Continuous Power Dissipation (TA=+25)(3) Recommended Operating Conditions (4) Operating Junction Temp. (TJ).-40°C to +125°C Thermal Resistance (5) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) Refer to the section “Configuring the EN Control”. 3) The maximum allowable power dissipation is a function of the maximum junction temperature T J(MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)- TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on JESD51-7, 4-layer PCB.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 7 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40C to +125C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Supply Current Supply Current (Shutdown) IIN VEN = 0V 0 1 μA Supply Current (Quiescent) IIN VEN = 2V, VFB = 1V 700 860 1000 μA MOSFET High-side Switch On Resistance HSRDS-ON MPQ8632GLE-4,6,8, TJ =25C 28 mΩ MPQ8632GLE-10,12, MPQ8632HGLE-10, TJ =25C 19.6 mΩ MPQ8632GVE-15,20, TJ =25C 9.9 mΩ Low-side Switch On Resistance LSRDS-ON MPQ8632GLE-4, TJ =25C 16.4 mΩ MPQ8632GLE-6, TJ =25C 15.8 MPQ8632GLE-8, TJ =25C 15.3 MPQ8632GLE-10, MPQ8632HGLE-10, TJ =25C 5.7 MPQ8632GLE-12, TJ =25C 5.2 MPQ8632GVE-15, TJ =25C 3 MPQ8632GVE-20, TJ =25C 2.4 Switch Leakage SWLKG VEN = 0V, VSW = 0V or 12V 0 10 μA Current Limit High-side Peak Current Limit ILIMIT_PEAK MPQ8632GLE-10 13 17.3 21.6 A Low-side Valley Current Limit(6) ILIMIT_VALLEY MPQ8632GLE-4 4 5 6 A MPQ8632GLE-6 6.5 7.5 8.5 MPQ8632GLE-8 8 10 12 MPQ8632GLE-10 9.5 11 12.5 MPQ8632HGLE-10 10 13 16 MPQ8632GLE-12 12 15 18 MPQ8632GVE-15 15 20 25 MPQ8632GVE-20 20 25 30 Low-side Negative Current Limit(6) ILIMIT_NEGATIVE MPQ8632GVE-15 -6.6 -5.6 -4.6 A All other parts -4 -2.5 -1
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 8 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40C to +125C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Timer One-Shot On Time TON RFREQ=453kΩ, VOUT=1.2V 250 ns Minimum On Time(6) TON_MIN 20 30 40 ns Minimum Off Time(6) TOFF_MIN MPQ8632GLE-10 50 100 150 ns Other parts 200 360 420 Over-voltage and Under-voltage Protection OVP Latch Threshold(6) VOVP_LATCH MPQ8632GLE-10 127% 130% 133% VFB OVP Non-latch Threshold VOVP_NON- LATCH 117% 120% 123% VFB OVP Delay TOVP 2 μs UVP Threshold(6) VUVP 47% 50% 53% VFB Reference And Soft Start Reference Voltage VREF TJ = 0°C to +70°C 608 611 614 mV TJ = 0°C to +125°C 605 611 617 mV TJ = -40°C to +125°C 602 611 620 mV Feedback Current IFB VFB = 611mV 50 100 nA Soft Start Charging Current ISS VSS=0V 16 20 25 μA Enable And UVLO Enable Input Low Voltage VILEN 1.1 1.3 1.5 V Enable Hysteresis VEN-HYS 250 mV Enable Input Current IEN VEN = 2V 0 μA VEN = 0V 0 VCC Regulator VCC Under Voltage Lockout Threshold Rising VCCVth 3.8 V VCC Under Voltage Lockout Threshold Hysteresis VCCHYS 500 mV VCC Regulator VCC 4.8 V VCC Load Regulation Icc=5mA 0.5 % Power Good Power Good Rising Threshold PGVth-Hi 87% 91% 94% VFB Power Good Falling Threshold PGVth-Lo 80% VFB Power Good Lower to High Delay PGTd 2.5 ms Power Good Sink Current Capability IOL VOL=600mV 12 mA Power Good Leakage Current IPG_LEAK VPG = 3.3V 10 nA
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 9 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40C to +125C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Thermal Protection (6) Thermal Shutdown TSD 150 °C Thermal Shutdown Hysteresis 25 °C Note: 6) Guaranteed by design.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 10 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. PIN FUNCTIONS MPQ8632GLE-4, MPQ8632GLE-6, MPQ8632GLE -8, MPQ8632GLE -10, MPQ8632HGLE-10, MPQ8632GLE-12 PIN # Name Description 1 EN Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Connect EN to IN through a pull -up resistor or a resistive voltage divider for automatic startup. Do not float this pin.
2 FREQ
Frequency Set. Require a resistor connected between FREQ and IN to set the switching frequency. The input voltage and the resistor connected to the FREQ pin determine the ON time. The connection to the IN pin provides line feed-forward and stabilizes the frequency during input voltage’s variation. 3 FB Feedback. Connect to the tap of an external resistor divider from the output to GND to set the output voltage. FB is also configured to realize over-voltage protection (OVP) by monitoring output voltage. MPQ8632 and MPQ8632H provide different OVP mode. Please refer to the section “Over-Voltage-Protection (OVP)”. Place the resistor divider as close to FB pin as possible. Avoid using vias on the FB traces. 4 SS Soft Start. Connect an external capacitor to program the soft start time for the switch mode regulator. 5 AGND Analog ground. The control circuit reference. 6 PG Power Good. The output is an open drain signal. Require a pull-up resistor to a DC voltage to indicate high if the output voltage exceeds 91% of the nominal voltag e. There is a delay from FB ≥ 91% to PG goes high.
7 VCC
Internal 4.8V LDO Output. Power t he driver and control circuits. 5V external bias can disable the internal LDO. Decouple with a ≥ 1µF ceramic capacitor as close to the pin as possible . For best res ults, use X7R or X5R dielectric ceramic capacitors for their stable temperature characteristics. 8 BST Bootstrap. Require a capacitor connected between SW and BS T pins to form a floating supply across the high-side switch driver. 9, 14 IN Supply Voltage . Supply power to the internal MOSFET and regulator. The MPQ8632 operates from a +2.5V to + 18V input rail with 5V external bias and a +4.5V to +18V input rail with internal bias. Require an input decoupling capacitor. Connect using wide PCB traces and multiple vias. 10-13 PGND System Ground. Reference ground of the regulated output voltage. PCB layout requires extra care. Connect using wide PCB traces. 15, 16 SW Switch Output. Connect to the inductor and bootstrap capacitor. The high -side switch drives the pin up to the VIN during the PWM duty cycle ’s ON time . The inductor current drives the SW pin negative during the OFF-time. The low -side switch’s ON-resistance and the internal Schottky diode clamp the negative voltage. Connect using wide PCB traces.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 11 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. MPQ8632GVE-15, MPQ8632GVE-20 PIN # Name Description 1 EN Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the regulator; drive it low to turn it off. Connect EN to IN through a pull -up resistor or a resistive voltage divider for automatic startup. Do not float this pin. Frequency Set. Require a resistor connected between FREQ and IN to set the switching frequency. The input voltage and the resistor connected to the FREQ pin determine the ON time. The connection t o the IN pin provides line feed-forward and stabilizes the frequency during input voltage’s variation. 3 FB Feedback. Connect to the tap of an external resistor divider from the output to GND to set the output voltage. Place the resistor divider as close to FB pin as possible. Avoid using vias on the FB traces. 4 SS Soft-Start. Connect an external capacitor to program the soft start time for the switch mode regulator. 5 AGND Analog Ground. The control circuit reference. 6 PG Power-Good. The output is a n open drain signal. Requires a pull-up resistor to a DC voltage to indicate HIGH if the output voltage exceeds 91% of the nominal voltage. There is a delay from FB ≥ 91% to when PG goes high. Internal 4.8V LDO Output. Powers the driver and control circuits. 5V external bias can disable the internal LDO. Decouple with a ≥1µF ceramic capacitor as close to the pin as possible . For best results, use X7R or X5R dielectric ceramic capacitors for their stable temperature characteristics. 8 BST Bootstrap. Require a capacitor connected between SW and BS T pins to form a floating supply across the high-side switch driver. 15-18, 25-29 SW Switch Output. Connect to the inductor and bootstrap capacitor. The high-side switch drives these pins up to V IN during th e PWM duty cycle’s ON time. The inductor current drives the SW pin negative during the OFF -time. The low-side switch’s ON- resistance and the internal Schottky diode holds the negative voltage. Connect all SW pins using wide PCB traces. 10-14, 19-23 PGND System Ground. Reference ground of the regulated output voltage. PCB layout requires extra care. Connect using wide PCB traces. 9, 24 IN Supply Voltage. Supplies power to the internal MOSFET and regulator. The MPQ8632GVE operate from a 4.5V-to-18V input ra il. If 5V external bias is tied to VCC pin, the input voltage can be low as 2.5V. Requires an input decoupling capacitor. Connect using wide PCB traces and multiple vias.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 12 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 13 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 14 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 15 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 16 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 17 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 18 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. BLOCK DIAGRAM FREQ VCC EN SS FB PG IN BST SW GND AGND HS-FETHS Driver LS-FETLS Driver ZCD Current Modulator LOGIC BST BIAS FB Comparator UV OV UV Detect Comparator OV Detect Comparator PGOOD Comparator SOFT START REFERENCE VCC LDO ON Timer Minimum OFF Timer VCC LS Current Limit Figure 1—Functional Block Diagram
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 22 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. reasonable that the jitter in skip mode is larger To achieve less jitter during ultra light load condition, reduce R1 and R2, but that will decrease the light load efficiency. Configuring the EN Control The regulator turns on when En goes high; conversely it turns off when EN goes low. Do not float the pin. For automatic start-up, pull the EN pin up to input voltage through a resistive voltage divider. Choose the values of the pull -up resistor ( RUP from the IN pin to the EN pin) and the pull -down resistor (RDOWN from the EN pin to GND) to determine the automatic start-up voltage: UP DOWN IN START DOWN (R R )V 1.5 (V) R (11) For example, for R UP=100kΩ and R DOWN=51kΩ, the VIN-START is set at 4.44V. To reduce noise, a dd a 10nF ceramic c apacitor from EN to GND. An internal zener diode on the EN pin clamps the EN pin voltage to prevent run away. The maximum pull up current assuming the worst case 6V for the internal zener clamp should be less than 1mA. Therefore, when driving EN with an external logic signal, use an EN voltage less than 6V . W hen connecting EN to IN through a pull-up resistor or a resistive voltage divider, select a resistance that ensures a maximum pull-up current less than 1mA. If using a resistive voltage divider and V IN exceeds 6V, then the minimum resistance for the pull-up resistor RUP should meet: IN UP DOWN V 6V 6V 1mARR (12) With only RUP (the pull -down resistor , RDOWN, is not connected), the n the VCC UVLO threshold determines VIN-START, so the minimum resistor value is: IN UP V 6VR ( ) 1mA (13) A typical pull-up resistor is 100kΩ. External VCC bias An external 5V VCC bias can disable the internal LDO, in this case, Vin can be as low as 2.5V. Soft Start The MPQ8632 employs a soft start (SS) mechanism to ensure a smooth output during power-up. Whe n the EN pin goes high, an internal current source ( 20μA) charges the SS capacitor. The SS capacitor voltage takes over the REF voltage to the PWM comparator. The output voltage smoothly ramps up with the SS voltage. Once the SS voltage reaches the REF voltage, it continues ramping up while VREF takes over the PWM comparator. At this point, soft start finishes and the device enters steady state operation. Determine the SS capacitor value as follows: SS SS SS REF T ms I AC nF VV (14) If the output capacitors are large, then avoid setting a short SS time or risk hitting the current limit during SS. Use a minimum value of 4.7nF if the output capacitance value exceeds 330μF. Pre-Bias Startup The MPQ8632 has been designed for monotonic startup into pre-biased loads. If the output is pre - biased to a certain voltage during startup, the IC will disable switching for both high-side and low- side switches until the voltage on the soft -start capacitor exceeds the sensed output voltage at the FB pin. Power Good (PG) The MPQ8632 has a power-good (PG) output. The PG pin is the open drain of a MOSFET. Connect it to VCC or some other voltage source that measures less than 5.5V through a pull-up resistor (typically 100kΩ). After applying the input voltage, the MOSFET turns on so that the PG pin is pulled to GND before the SS is ready. After the FB voltage reaches 9 1% of the REF voltage, the PG pin is pulled high after a 2.5ms delay.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 23 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. When the FB voltage drops to 80% of the REF voltage or exceeds 12 0% of the nominal REF voltage, the PG pin is pulled low. If the input supply fails to power the MPQ8632, the PG pin is also pulled low even though this pin is tied to an external DC source through a pull-up resistor (typically 100kΩ). Over-Current Protection (OCP) The MPQ8632 features three current limit levels for over-current conditions: high-side peak current limit, low-side valley current limit and low- side negative current limit. However, the OCP operation mechanism of MPQ8632GL-10 is different from other parts in this family. For MPQ8632GLE-10: High-Side Peak Current Limit: The part has a cycle-by-cycle over-current limiting function. The device monitors the inductor current during the HS-FET ON state. W hen the sensed inductor current hits the peak current limit, the output over-current comparator goes high, the device enters OCP mode immediately and turns off the HS-FET and turns on the LS-FET. Low-Side Valley Current Limit : The device also monitors the inductor current dur ing the LS-FET ON state. When ILIM=1 and at the end of the OFF time, the LS -FET sourcing current is compared to the internal positive -valley–current limit. If the valley current limit is less than the LS- FET sourcing current, the HS -FET remains OFF and the LS-FET remains ON for the next ON time. When the LS-FET sourcing current drops below the valley current limit , the HS -FET turn s on again. For other parts except MPQ8632GLE-10: These parts enter OCP mode if only the LS-FET sourcing valley current exceeds the valley current limit. Once the OCP is triggered, the LS -FET keeps ON state until the LS-FET sourcing valley current is less than the valley current limit . A nd then the LS-FET turns off, the HS-FET turns on for a fixed time determined by frequency-set resistor RFREQ and input voltage. During OCP, the device tries to recover from the over-current fault with hiccup mode : the chip disables the output power stage, discharges the soft-start capacitor and then automatically retries soft-start. If the over-current condition still holds after soft -start ends, the device repeats this operation cycle until the over-current conditions disappear and then output rises back to regulation level. OCP offers non-latch protection. Low-Side Negative Current Limit: If the sensed LS-FET negative current exceeds the negative current limit, the LS -FET turn s off immediately and stays OFF for the remainder of the OFF period. In this situation, both MOSFETs are OFF until the end of a fixed interval. The HS-FET body diode conducts the inductor current for the fixed time. Over -Voltage Protection (OVP) The MPQ8632 monitors the output voltage using the FB pin connected to the tap of a resistor divider to detect over-voltage. MPQ8632 and MPQ8632H provide non-latch and latch off OVP mode as showed in Table 1. Table 1—OVP Mode OVP Mode Non-Latch Mode Latch-Off Mode Part # MPQ8632-4 MPQ8632-6 MPQ8632-8 MPQ8632H-10 MPQ8632-12 MPQ8632-15 MPQ8632-20 MPQ8632-10 For MPQ8632GLE-10: If the FB voltage exceeds the nominal REF voltage but remains lower than 120% of the REF voltage (0.611V), both MOSFETs are off. If t he FB voltage exceeds 120% of the REF voltage but remains below 130%, the LS -FET turns on while the HS -FET remains off. The LS- FET remains on until the FB voltage drops below 110% of the REF voltage or the low -side negative current limit is hit. If the FB voltage exceeds 130% of the REF voltage, then the device is latched off. Need cycle the input power supply or EN to restart.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 25 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltage -Large ESR Capacitors For applications that electrolytic capacitor or POS capacitor with a large ESR is set as output capacitors. The feedback resistors —R1 and R2 as shown in Figure 10—set the output voltage. ESR POSCAP SW VOUTL FB Figure10—Simplified POSCAP Circuit First, choose a value for R2 that balances between high quiescent current loss (low R2) and high noise sensitivity on FB (high R2) . A typical value falls within 5kΩ to 50kΩ, using a comparatively larger R2 w hen VOUT is low, and a smaller R2 when VOUT is high. Then calculate R1 as follows, which considers the output ripple: OUT OUT REF REF 1V V V 2R1 R2 V (15) Where OUTV is the output ripple determined by equation 24. Setting the Outpu t Voltage -Small ESR Capacitors Ceramic SW FB VOUTL R4 C4 Figure11—Simplified Ceramic Capacitor Circuit When using a low ESR ceramic capacitor on the output, add an external voltage ramp to the FB pin consisting of R4 and C4.The ramp voltage, VRAMP, and the resistor divider influence the output voltage as shown in Figure 11 . Calculate VRAMP as shown in equation 7. Select R2 to balance between high quiescent current loss and FB noise sensitivity. Choose R2 within 5kΩ to 50kΩ, using a larger R2 when VOUT is low, and a smaller R2 wh en VOUT is high. Determine the value of R1 as follows: 9R4R VV V 2R1R )AVG(FBOUT )AVG(FB (16) Where VFB(AVG) is the average FB voltage. VFB(AVG) varies with the V IN, V OUT, and load condition, where the load regulation is strictly related to the VFB(AVG). Also the line regulation is related to the VFB(AVG); improving the load or line regulation involves a lower VRAMP that meets equation 9. For PWM operation, estimate VFB(AVG) from equation 17. 9R2R//1R 2R//1RV2 1VV RAM PREF)AVG(FB (17) Usually, R9 is 0Ω, though it can also be set following equation 18 for better noise immunity. It should also be less than 20% of R1//R2 to minimize its influence on VRAMP.
1 R1 R2R9 5 R1 R2
(18) Using equation s 16 and 1 7 to calculate the output voltage can be complicated. To simplify the R1 calculation in equation 1 6, add a DC - blocking capacitor, CDC, to filter the DC influence from R4 and R9. Figure 12 shows a simplified circuit with external ramp compensation and a DC-blocking capacitor. The a ddition of this capacitor, simplifies the R1 calculation as per equation 19 for PWM mode operation.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 26 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1VV RAMPREF RAMPREFOUT (19) For best results, select a CDC Value at least 10× C4 for better DC blocking performance , but smaller than 0.47µF account for start-up performance. To use a larger CDC for better FB noise immunity, reduce R1 and R2 to limit effects on system start-up. Note that even with Cdc, the load and line regulation are still related to VRAMP. Ceramic SW FB VOUTL CDC R4 C4 Figure12—Simplified Ceramic Capacitor Circuit with DC Blocking Capacitor Input Capacitor The input current to the step -down converter is discontinuous, and t herefore, requires a capacitor to supply the AC current to the step - down converter while maintaining the DC input voltage. Use c eramic cap acitors for best performance. During layout, Place the input capacitors as close to the IN pin as possible. The capacitance can vary significantly with temperature. Use c apacitors with X5R and X7R ceramic dielectrics because they are fairly stable over a wide temperature range. The capacitors must also have a ripple current rating that exceeds the converter’s maximum input ripple current. Estimate t he input ripple current as follows: V1(V VII IN OUT IN OUT OUTCIN (20) The worst-case condition occur s at V IN = 2VOUT, where: II OUT CIN (21) For simplification, choose an input capacitor with an RMS current rating that exceeds half the maximum load current. The input capacitance value deter mines the converter input voltage ripple. Select a capacitor value that meets any input voltage ripple requirements. Estimate the input voltage ripple as follows: V1(V V CF IV IN OUT IN OUT INSW OUT (22) The worst-case condition occurs at V IN = 2VOUT, where: INSW OUT IN CF I 1V (23) Output Capacitor The output capacitor maintain s the DC output voltage. Use c eramic capacitors or POSCAP s. Estimate the output voltage ripple as: )CF8 1R()V V1(LF VV OUTSW ESR IN OUT SW OUT OUT (24) When using ceramic capacitors, the capacitance dominates the impedance at the switching frequency. The capacitance also dominates the output voltage ripple. For simplification, estimate the output voltage ripple as: V1( CLF8 VV IN OUT OUT SW OUT OUT (25) The ESR only contributes minimally to the output voltage ripple, thus requiring an external ramp to stabilize the system. Design t he external ramp with R4 and C4 as per equation 5, 8 and 9.
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 27 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. The ESR dominates the switching-frequency impedance for POSCAPs,. The ESR ramp voltage is high enough to stab ilize the system. thus eliminating the need for an external ramp. Select a minimum ESR value around 12mΩ to ensure stable operation. For simplification, the output ripple can be approximated as: ESR IN OUT SW OUT OUT R)V V1(LF (26) Inductor The inductor supplies constant current to the output load while being driven by the switc hing input voltage. A larger value inductor result s in less ripple current and lower output ripple voltage, but is l arger physical size, has a higher series resistance, and/or lower saturation current. Generally, select an inductor value that allows the inductor peak-to-peak ripple current to 30 % to 40% of the maximum switch current limit. Also, design for a peak inductor current that is below the maximum switch current limit. Calculate the inductance value as: V1(IF VL IN OUT LSW (27) Where ΔI L is the peak -to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated as: V1(LF2 VII IN OUT SW OUT (28) Table 2 lists a few highly-recommended high- efficiency inductors. Table 2—Inductor Selection Guide Part Number Manufacturer Inductance (µH) DCR (mΩ) Current Rating (A) Dimensions L x W x H (mm3) Switching Frequency (kHz) FDU1250C-1R0M TOKO 1 1.72 31.3 13.3 x 12.1 x 5 500 Typical Design Parameter Tables The following tables include recommended component values for typical output voltages (1V, 2.5V, 3.3V) and switching frequenc y (500kHz). Refer to Tables 3-9 for design cases without external ramp compensation . And Tables 10-16 are for design cases with external ramp compensation. An external ramp is not needed when using high-ESR output capacitors, such as electrolytic or POSCAPs. Use an e xternal ramp when using low-ESR capacitors, such as ceramic capacitors. For cases not listed in this datasheet, an excel spreadsheet provided by local sales representatives can assist with the calculations. Table 3—MPQ8632-4, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) 1 1.8 13.3 20 357 2.5 3.3 63.4 20 887 3.3 3.9 91 20 1200 Table 4—MPQ8632-6, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) 1 1 13.3 20 357 2.5 2.2 63.4 20 887 3.3 3.3 91 20 1200
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 28 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. Table 5—MPQ8632-8, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) 1 0.72 13.3 20 357 2.5 1.8 63.4 20 887 3.3 2.2 91 20 1200 Table 6—MPQ8632-10, MPQ8632H-10, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) 1 0.72 13.3 20 357 2.5 1.5 63.4 20 887 3.3 1.8 91 20 1200 Table 7—MPQ8632-12, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) 1 0.72 13.3 20 357 2.5 1.5 63.4 20 887 3.3 1.8 91 20 1200 Table 8—MPQ8632GVE-15, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) 1 0.72 13.3 20 357 2.5 0.72 63.4 20 887 3.3 1 91 20 1200 Table 9— MPQ8632GVE-20, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) 1 0.72 13.3 20 357 2.5 0.72 63.4 20 887 3.3 0.72 91 20 1200 Table 10—MPQ8632-4, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) (pF) (kΩ) 1 1.8 13.7 20 750 220 357 2.5 3.3 66.5 20 1000 220 887 3.3 3.9 95.3 20 1200 220 1200 Table 11—MPQ8632-6, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) (pF) (kΩ) 1 1 13.7 20 750 220 357 2.5 2.2 66.5 20 1000 220 887 3.3 3.3 95.3 20 1200 220 1200 Table 12—MPQ8632-8, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) (pF) (kΩ) 1 0.72 13.7 20 750 220 357 2.5 1.8 66.5 20 1000 220 887 3.3 2.2 95.3 20 1200 220 1200 Table 13—MPQ8632-10, MPQ8632H-10, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) (pF) (kΩ) 1 0.72 13.7 20 750 220 357 2.5 1.5 66.5 20 1000 220 887 3.3 1.8 95.3 20 1200 220 1200 Table 14—MPQ8632-12, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) (pF) (kΩ) 1 0.72 13.7 20 750 220 357 2.5 1.5 66.5 20 1000 220 887 3.3 1.8 95.3 20 1200 220 1200 Table 15—MPQ8632GVE-15, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) (pF) (kΩ) 1 0.72 13.7 20 750 220 357 2.5 0.72 68 20 1000 220 887 3.3 1 95.3 20 1200 220 1200 Table 16—MPQ8632GVE-20, FSW=500kHz, VIN=12V VOUT (V) L (μH) (kΩ) (kΩ) (kΩ) (pF) (kΩ) 1 0.72 13.7 20 750 220 357 2.5 0.72 68 20 1000 220 887 3.3 0.72 95.3 20 1200 220 1200
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A MPQ8632 Rev.1.24 www.MonolithicPower.com 45 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.
PACKAGE INFORMATION
QFN(3X4mm) PACKAGE OUTLINE DRAWING FOR 16L FCQFN (3X4MM) MF-PO-D-0170 revision 0.0 SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. TOP VIEW RECOMMENDED LAND PATTERN PIN 1 ID MARKING PIN 1 ID INDEX AREA PIN 1 ID 0.125x45° TYP. 0.125x45°
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ8632 Rev.1.24 www.MonolithicPower.com 46 8/28/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. QFN(5X4mm) SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN 0.125x45° PIN 1 ID 0.125x45° TYP.