MPQ7920GRM-XXXX-AEC1-Z

MPQ7920 MPS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
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Technical content

5V PMIC with Four 2A/2.5A/4.5A/4.5A Buck Converters, 5 LDOs, and Flexible System Settings via I2C and MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 1 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved.

DESCRIPTION

The MPQ7920 is a complete power management solution that integrates four high - efficiency step -down DC/DC converters, five low-dropout regulators , and a flexible logic interface. Constant-on-time ( COT) control in the DC/DC converter provides fast transient response. The adjustable switching frequency (up to 2.75MHz) during CCM greatly reduces external inductor and capacitor value. Full protection feature s include UVLO, OCP, OVP , and thermal shutdown. The output voltage is adjustable through the I2C bus or preset by the MTP ( multiple-time programmable). The power -on/off sequence is also programmable via the MTP and can be controlled through I2C bus online. The MPQ7920 requires a minimal number of external components, and is available in a space-saving QFN-26 (3.5mmx4.5mm) package with wettable flank s. This part is AEC -Q100 qualified.

FEATURES

 High-Efficiency Step-Down Converters o Buck 1: 4.5A DC/DC Converter o Buck 2: 2.5A DC/DC Converter o Buck 3: 4.5A DC/DC Converter o Buck 4: 2A DC/DC Converter o Buck 1 and Buck 3 Can Work in Parallel o Buck 2 and Buck 4 Can Work in Parallel o 2.7V to 5.5V Operating Input Range o 0.4V to 3.58V/12.5mV Step or 0.4V to 2.2V/7.4mV Step Option VOUT Range for Buck 1, Buck 2, and Buck 3 o 0.4V to 3.58V/12.5mV step VOUT Range for Buck 4 o Adjustable Switching Frequency o Adjustable Soft-Start Time o Adjustable Phase Delay o Programmable Forced PWM, Auto- PFM, PWM Mode o Output OCP, OVP  Low-Dropout Regulators o One RTC Dedicated LDO o Four Low-Noise LDOs o Two Separate Input Power Supplies o 50mV Dropout at 300mA Load  System o I2C Bus and User Programmable MTP o Two-Time Programmable MTP (1) o Power-On/Off Control o Multi-Function LDO2/EN1 Pin (EN1 Input Logic Level ≤ 3.3V) o Power-On Reset Output o Flexible Power-On/Off Sequence via MTP (0.5ms/2ms/8ms/16ms Selectable Time Slot) o Flexible DC/DC, LDO On/Off via the MTP o ±4kV HBM and ±2kV CDM ESD Rating for All Pins o Available in a QFN-26 (3.5mmx4.5mm) Package o Available in AEC-Q100 Grade 1 Note: 1) The two-time p rogrammable MTP is only for the standard version of the MPQ7920GRM-0000-AEC1 (see page 39).

APPLICATIONS

 Automotive Infotainment  Automotive Video Recorder  Automotive Display Electronics All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries .

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 2 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. TYPICAL APPLICATION MPQ7920 VIN1 GND1 PWRON SCL SW1 FB1 OUTRTC OUT2/ EN1 OUT3 VIN1: 2.7V to 5.5V VOUT1: 1.15V 1.8V 22µF 22µFX2 1µH SW2 FB2 1.5µH SW3 FB3 22µFX2 SW4 FB4 VIN2 GND2 22µF VIN3 22µF VIN4 22µF 2.2µF C12 2.2µF C11 1.8V3.3V 1µF C10 10µF C15 VIN5 2.2µF C14 OUT5 1.8V 2.2µF C13 OUT4 1.1V RSTO AVIN 0.1µF AGND SDA VOUT2: 1.5V VOUT3: 1.15V VOUT4: 1.8V 1µH 1.5µH 100k 3.3V VIN5: 2.7V to 5.5V 4.7 22µFX2 22µFX2 C3B 100µF MTP E-FUSE SELECTED TABLE BY DEFAULT (MPQ7920GRM-0003): OTP Items Buck 1 Buck 2 Buck 3 Buck 4 LDORTC LDO2 LDO3 LDO4 LDO5 Initial on/off On On On On On On On On On Mode FPWM FPWM FPWM FPWM N/A Power-on delay 0ms 4.5ms 0ms 4.5ms Always on 5.5ms 5.5ms 5.5ms 9.5ms Soft-start time 300μs 300μs 300μs 300μs N/A Switching frequency 2.2MHz PWRON MODE 0 (level trigger) RSTODELAY 50ms Buck 1 peak current limit 9.3A Buck 2 peak current limit 6.1A Buck 3 peak current limit 9.3A Buck 4 peak current limit 6.1A I2C slave address 0x69 MTP configure code 0003

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 3 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL Rating MPQ7920GRM-xxxx-AEC1** QFN-26 (3.5mmx4.5mm) See Below 1 MPQ7920GRM-0003-AEC1 QFN-26 (3.5mmx4.5mm) See Below * For Tape & Reel, add suffix –Z (e.g. MPQ7920GRM-xxxx-AEC1–Z). ** “xxxx” is the configuration code identifier for the register setting stored in the OTP. The default number is “0003”. Each “x” can be a hexadecimal value between 0 and F. Work with an MPS FAE to create this unique number, even if ordering the “0003” code. MPQ7920GRM-0003-AEC1 is the default version, which can be MTP 1 time. MPQ7920GRM-0000-AEC1 is the standard version for sampling, which can be MTP 2 times. TOP MARKING MPS: MPS prefix Y: Year code W: Week code M7920: Part number LLLLL: Lot number EVALUATION KIT EVKT-MPQ7920 EVKT-MPQ7920 kit contents (items below can be ordered separately): # Part Number Item Quantity

1 EVQ7920-R-00A MPQ7920GRM evaluation board 1

2 EVKT-USBI2C-02 Includes one USB to I2C communication interface device, one USB

cable, and one ribbon cable 1

3 MPQ7920-0000 MPQ7920 IC, which can be used for MTP programming 2

Order direct from MonolithicPower.com or our distributors. Figure 1: EVKT-MPQ7920 Evaluation Kit Set-Up

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 4 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW 3VIN1 4SW1 5GND1 6SW3 VIN3 VIN2 SW2 GND2 SW4 VIN4 26 25 AVIN AGND OUT RTC OUT2/ EN1 SCL SDA OUT4 VIN5 2PWRON 2324

21 FB2

15 FB4FB3

QFN-26 (3.5mmx4.5mm) PIN FUNCTIONS Pin # Name Description 1 FB1 Feedback of buck 1. Connect buck 1’s output directly to this pin. 2 PWRON Power-on/off input. Logic input pin to start up or shut down the device. This pin should be pulled high by an external voltage.

3 VIN1

Buck 1 s upply voltage input. The MPQ7920 operates from a 2.7V to 5.5V input rail. It requires a ceramic capacitor to decouple the input rail. Connect using a wide PCB trace. VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage. 4 SW1 Buck 1 switch output. Connect using a wide PCB trace. 5 GND1 Buck 1 and buck 3 power ground. Requires special consideration during PCB layout. Connect to GND with copper traces and vias. 6 SW3 Buck 3 switch output. Connect using a wide PCB trace.

7 VIN3

Buck 3 supply voltage input. The MPQ7920 operates from a 2.7V to 5.5V input rail. It requires a ceramic capacitor to decouple the input rail. Connect using a wide PCB trace. VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage. 8 FB3 Buck 3 feedback. Directly connect buck 3’s output to this pin. 9 RSTO Reset output from the PMIC to CPU. Open-drain output. This pin requires an external pull- up resistor. 10 SCL I2C clock signal input. 11 SDA I2C data pin.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 5 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. PIN FUNCTIONS (continued) Pin # Name Description 12 OUT4 LDO4 output. LDO4 is powered by VIN5. 13 VIN5 LDO4 and LDO5 power input pin. This pin operates from a 2.7V to 5.5V input voltage. 14 OUT5 LDO5 output. LDO5 is powered by VIN5. 15 FB4 Buck 4 feedback. Directly connect buck 4’s output to this pin.

16 VIN4

Buck 4 supply voltage input. The MPQ7920 operates from a 2.7V to 5.5V input rail. It requires a ceramic capacitor to decouple the input rail. Connect using a wide PCB trace. VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage. 17 SW4 Buck 4 switch output. Connect using a wide PCB trace. 18 GND2 Buck 2 and buck 4 power ground. This pin requires special consideration during PCB layout. Connect to GND with copper traces and vias. 19 SW2 Buck 2 switch output. Connect using a wide PCB trace.

20 VIN2

Buck 2, LDORTC, LDO2 , and LDO3 supply voltage input. The MPQ7920 operates from a 2.7V to 5.5V input rail. It requires a ceramic capacitor to decouple the input rail. Connect using a wide PCB trace. VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage. 21 FB2 Buck 2 feedback. Directly connect buck 2’s output to this pin. 22 OUT3 LDO3 output. LDO3 is powered by VIN2.

23 OUT2/EN1

LDO2 output or EN1. LDO2 is powered by VIN2 . When configuring this pin as EN1, it acts as an input pin. Pull EN1 up or down to enable or disable the MPQ7920 , respectively. 24 OUTRTC RTC LDO output. This LDO is powered by VIN2. 25 AGND Analog ground. Connect this pin to GND1 and GND2.

26 AVIN

Power supply input for logic circuitry. Bypass this pin with a 0.1µF ceramic capacitor to AGND. Connect AVIN to the system input through a 4.7Ω resistor. VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 6 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) -0.6V (-5V for <10ns) to VIN + 0.3V (7V for <10ns) Continuous power dissipation (TA = 25°C) (2) (6) Storage temperature.………….-65°C to +150°C ESD Rating (3) Recommended Operating Conditions (4) Step-down regulator (VIN)………..…2.7V to 5.5V Step-down regulator (VOUT)………………….0.4V to 3.5875V or VIN LDO regulator (VOUTL)…..0.65V to 3.5875V or VIN Thermal Resistance θJA θJC QFN-26 (3.5mmx4.5mm) Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation may cause excessive die temperature, and the regulator can go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) HBM, per JEDEC specification JESD22 -A114; CDM, per JEDEC specification JESD22 -C101, AEC specific ation AECQ100-011. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. 4) The device is not guaranteed to function outside of its operating conditions. 5) Operating devices at junction temperatures greater than 125°C is possible; contact MPS for details. 6) Measured on EVQ7920-R-00A, 4-layer PCB. 7) Measured on JESD51-7, 4-layer PCB. The value of θ JA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51 -7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 7 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = AVIN = 5V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted. (8) Parameter Symbol Condition Min Typ Max Units Supply current (no switching) IIN No switching, feedback is high, TJ = 25°C 300 600 μA Shutdown current IIN_STD All regulators disabled except LDORTC, TJ = 25°C 30 60 μA All regulators disabled except LDORTC, TJ = -40°C to +125°C 30 120 μA Default oscillation frequency fSW 1.8 2.2 2.4 MHz Thermal shutdown entry threshold (9) TOTP_R 153 °C Thermal shutdown recovery threshold (9) THYS 130 °C Step-Down Regulator AVIN UVLO rising VAIN1_R 2.4 2.55 2.7 V AVIN UVLO hysteresis VAIN1_HYS 300 mV VIN1 UVLO rising VIN1_R 2.3 2.45 2.6 V VIN1 UVLO hysteresis VIN1_HYS 300 mV VIN2 UVLO rising VIN2_R 2.35 2.5 2.65 V VIN2 UVLO hysteresis VIN2_HYS 300 mV VIN3 UVLO rising VIN3_R 2.3 2.45 2.6 V VIN3 UVLO hysteresis VIN3_HYS 300 mV VIN4 UVLO rising VIN4_R 2.3 2.45 2.6 V VIN4 UVLO hysteresis VIN4_HYS 300 mV VIN5 UVLO rising VIN5_R 2.3 2.45 2.6 V VIN5 UVLO hysteresis VIN5_HYS 300 mV Feedback voltage accuracy VFB1 Default output of buck 1 1.127 1.15 1.173 V VFB2 Default output of buck 2 1.47 1.5 1.53 V VFB3 Default output of buck 3 1.127 1.15 1.173 V VFB4 Default output of buck 4 1.764 1.8 1.836 V Maximum duty cycle (9) DMAX Buck 1 to buck 4 100 % Buck 1, Buck 3 (4.5A/4.5A) HS-FET on resistance HSRDS-ON1 500mA, TJ = 25°C 25 35 mΩ HSRDS-ON3 HSRDS-ON1 500mA, TJ = -40°C to +125°C 25 45 mΩ HSRDS-ON3

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 8 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = AVIN = 5V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted. (8) Parameter Symbol Condition Min Typ Max Units LS-FET on resistance LSRDS-ON1 500mA, TJ = 25°C 12 16 mΩ LSRDS-ON3 LSRDS-ON1 500mA, TJ = -40°C to +125°C 12 20 mΩ LSRDS-ON3 Switch leakage 1 HSWILK1 EN = 0V, VIN = 5.5V, SW = 0V or 5.5V, TJ = 25°C 0 1 μA HSWILK3 Switch leakage 2 LSWILK1 EN = 0V, VIN = 5.5V, SW = 0V or 5.5V, TJ = 25°C 0 1 μA LSWILK3 High-side current limit ILIMIT1 TJ = -40°C to +125°C 7.4 9.3 11.4 A ILIMIT3 TJ = -40°C to +125°C 7.4 9.3 11.4 A Minimum on time (9) tON_MIN1 50 ns tON_MIN3 50 ns Minimum off time (9) tOFF_MIN1 120 ns tOFF_MIN3 120 ns Output discharge resistance RO_DIS1 3 7 20 Ω Soft-start time tSS_B1 VOUT = 10% to 90% 140 300 430 μs tSS_B3 VOUT = 10% to 90% 140 300 430 μs Output OVP rising threshold VOVP1_H 115 120 125 % VREF Output OVP recovery threshold VOVP1_L 105 110 115 % VREF Buck 2, Buck 4 (2.5A/2A) HS-FET on resistance HSRDS-ON2 500mA, TJ = 25°C 40 55 mΩ HSRDS-ON4 HSRDS-ON2 500mA, TJ = -40°C to +125°C 40 70 mΩ HSRDS-ON4 LS-FET on resistance LSRDS-ON2 500mA, TJ = 25°C 40 55 mΩ LSRDS-ON4 LSRDS-ON2 500mA, TJ = -40°C to +125°C 40 85 mΩ LSRDS-ON4 Switch leakage 3 HSWILK2 Shutdown, VIN = 5.5V, SW = 0V or 5.5V, TA = 25°C 0 1 μA HSWILK4 Switch leakage 4 LSWILK2 Shutdown, VIN = 5.5V, SW = 0V or 5.5V, TA = 25°C 0 1 μA LSWILK4 Minimum on time (9) tON_MIN2 50 ns tON_MIN4 50 ns Minimum off time (9) tOFF_MIN2 100 ns tOFF_MIN4 100 ns Output discharge resistance RO_DIS2 3 7.5 20 Ω

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 9 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = AVIN = 5V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted. (8) Parameter Symbol Condition Min Typ Max Units Soft-start time tSS_B2 VOUT = 10 to 90% 140 300 430 μs tSS_B4 VOUT = 10 to 90% 140 300 430 μs Output OVP rising threshold VOVP2_H 115 120 125 % VREF Output OVP recovery threshold VOVP2_L 105 110 115 % VREF 10mA RTC LDO Default output voltage VRTC_LDO IOUT = 10mA, power-on state 3.24 3.37 3.5 V Ground current IQ_RTC No load 6.5 μA Dropout voltage VDROP1 VOUT = 3V, IOUT = 5mA 50 mV Current limit ILIM_RTC VIN = 3.3V, VOUT drops 33%, TJ = 25°C 25 55 85 mA Soft-start slew rate tSS_RTC VOUT = 10% to 90%, COUT = 1µF 25 mV/μs Low-Dropout LDO Regulator: LDO2 to LDO5 Output voltage VLDO2 IOUT = 10mA 1.764 1.8 1.836 V VLDO3 IOUT = 10mA 1.764 1.8 1.836 V VLDO4 IOUT = 10mA 1.078 1.1 1.122 V VLDO5 IOUT = 10mA 1.764 1.8 1.836 V PSRR (8) PSRR1K For LDO4 and LDO5, VOUT = 1.8V 52 dB Dropout voltage VDROP1 VOUT = 3V, IOUT = 300mA 50 mV Current limit ILIMIT_LDO For LDO2 and LDO3, VIN = 3.3V, VOUT drops 33% 300 430 600 mA ILIMIT_LDO_L LDO4 and LDO5 set ILIM bit = 0, VIN = 3.3V, VOUT drops 33% 380 520 660 mA ILIMIT_LDO_H LDO4 and LDO5 set ILIM bit = 1, VIN = 3.3V, VOUT drops 33% 580 790 1000 mA Output discharge resistance RO_DIS2 3 7 20 Ω Soft-start time tSS_B2 VOUT = 10% to 90%, COUT = 2.2µF 50 μs Line regulation VIN2 = VIN5 = 2.7V to 5.5V 0.3 %/V Load regulation VIN2 = VIN5 = 3.3V, Iout from 10mA to 100mA 0.5 % Logic Pins PWRON pull-up current IPWRON Internal pull-up to AVIN 5 9 13 μA PWRON rising threshold VPWR_R 0.8 1 1.2 V PWRON voltage hysteresis VPWR_HYS 100 mV EN1 rising threshold VEN1_R 0.8 1 1.2 V EN1 rising hysteresis VEN1_HYS 100 mV PG rising threshold VPG_R RSTO_MODE = 01 86% 90% 94% VFB PG falling threshold VPG_F RSTO_MODE = 01 76% 80% 84% VFB PFI rising threshold VPFI_R RSTO_PFI_THLD = 01, adjustable via the I2C/MTP 2.78 2.9 3.02 V

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 10 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN1 = VIN2 = VIN3 = VIN4 = VIN5 = AVIN = 5V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted. (8) Parameter Symbol Condition Min Typ Max Units PFI hysteresis VPFI_HYS 7% VPFI_R RSTO rising delay tRSTO Adjustable via the I2C/MTP 20 50 70 ms I2C Interface Specifications (10) Input logic high VIH 1.4 V Input logic low VIL 0.4 V Output voltage logic low VOUT_L RSTO pin sink 4mA 0.4 V SCL clock frequency fSCL 3.4 MHz SCL high time tHIGH 60 ns SCL low time tLOW 160 ns Data set-up time tSU_DAT 10 ns Data hold time tHD_DAT 70 ns Set-up time for repeated start tSU_STA 160 ns Hold time for repeated start tHD_STA 160 ns Bus free time between a start and a stop condition tBUF 160 ns Set-up time for stop condition tSU_STO 160 ns SCL and SDA rise time tR 10 300 ns SCL and SDA fall time tF 10 300 ns Pulse width of suppressed spike tSP 0 50 ns Capacitance bus for each bus line CB 400 pF Notes: 8) Tested with default version MPQ7920GRM-0003-AEC1. 9) Guaranteed by engineering sample characterization. 10) It is recommended to begin operating the I2C function after the power-on sequence is complete (all enabled power rails have finished starting up). See the I2C timing chart below when reading I2C interface specifications. I2C Timing Diagram

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 11 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS Performance waveforms are tested on the evaluation board , VIN = 5V, T A = 25°C, test ed using MPQ7920-0003 parts, unless otherwise noted. Efficiency VIN = 5V, fSW = 1.65MHz, buck 1 through buck 4 work in PWM mode Efficiency VIN = 5V, fSW = 2.2MHz, buck 1 through buck 4 work in PWM mode Load Regulation IC Power Dissipation vs. Case Temperature Rise Quiescent Current vs. Input Voltage VIN Rising Threshold vs. Temperature 100 EFFICIENCY (% ) OUTPUT CURRENT (A) buck1=1V buck2=3.3V buck3=1.5V buck4=2.5V 100 EFFICIENCY (% ) OUTPUT CURRENT (A) buck1=1.15V buck2=1.5V buck3=1.15V buck4=1.8V -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 0 1 2 3 4 5 LOAD REGULATION (% ) OUTPUT CURRENT (A) buck1=1.15V buck2=1.5V buck3=1.15V buck4=1.8V 100 120 0 1 2 3 4 5 6 CASE TEMPERATURE RISE (℃) IC POWER LOSS (W) 100 150 200 250 300 350 2 2.5 3 3.5 4 4.5 5 5.5 6 QUIESCENT CURRENT (µA) INPUT VOLTAGE (V) 2.2 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 -40 10 60 110 160 VIN RISING THRESHOLD (V) TEMPERATURE (℃) AVIN VIN1 VIN2 VIN3 VIN4 VIN5

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 12 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board , VIN = 5V, T A = 25°C, test ed using MPQ7920-0003 parts, unless otherwise noted. Switching Frequency vs. Temperature 1.8 1.9 2.1 2.2 -50 -30 -10 10 30 50 70 90 110 130 150 SWITCHING FREQEUNCY (MHz) TEMPERATURE (℃）

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 13 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS Performance waveforms are tested on the evaluation board , VIN = 5V, T A = 25°C, test ed using MPQ7920-0003 parts, unless otherwise noted. Steady State All buck rails with no load Steady State All buck rails with full load CH1: SW1 CH2: SW2 CH3: SW3 CH4: SW4 CH1: SW1 CH2: SW2 CH3: SW3 CH4: SW4 PWRON On All buck rails without load PWRON On All LDO rails without load R1: PWRON 5V/div. CH1: Buck 1 CH2: Buck 2 CH3: Buck 3 CH4: Buck 4 R1: PWRON 5V/div. CH1: LDO2 CH2: LDO3 CH3: LDO4 CH4: LDO5 PWRON Off All buck rails without load PWRON Off All LDO rails without load, disable all buck rails R1: PWRON 5V/div. CH1: Buck 1 CH2: Buck 2 CH3: Buck 3 CH4: Buck 4 R1: PWRON 5V/div. CH1: LDO2 CH2: LDO3 CH3: LDO4 CH4: LDO5

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 14 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board , VIN = 5V, T A = 25°C, test ed using MPQ7920-0003 parts, unless otherwise noted. VIN Start-Up All buck rails without load VIN Shutdown All buck rails without load R1: VIN 5V/div. CH1: Buck 1 CH2: Buck 2 CH3: Buck 3 CH4: Buck 4 R1: VIN 5V/div. CH1: Buck 1 CH2: Buck 2 CH3: Buck 3 CH4: Buck 4 SCP Entry Buck 4 output = 1.8V SCP Steady State Buck 4 output = 1.8V CH1: Buck 4 CH2: RSTO CH3: SW4 CH4: IL4 CH1: Buck 4 CH2: RSTO CH3: SW4 CH4: IL4 SCP Recovery Buck 4 output = 1.8V Load Transient Response IOUT transient from 2.25A to 4.5A, slew rate is 2.5A/µs CH1: Buck 4 CH2: RSTO CH3: SW4 CH4: IL4 CH1: Buck 1 / AC CH4: IOUT1

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 15 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board , VIN = 5V, T A = 25°C, test ed using MPQ7920-0003 parts, unless otherwise noted. Load Transient Response IOUT transient from 1.25A to 2.5A, slew rate is 2.5A/µs Load Transient Response IOUT transient from 2.25A to 4.5A, slew rate is 2.5A/µs CH1: Buck 2 / AC CH4: IOUT2 CH1: Buck 3 / AC CH4: IOUT3 Load Transient Response IOUT transient from 1A to 2A, slew rate is 2.5A/µs CH1: Buck 4 / AC CH4: IOUT4

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 16 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM 300mA LDO2 300mA/700mA LDO4 DCDC1 5.5V/4.5A I2C VID, 0.4V to 3.5875V with 12.5mV/step or 0.4V to 2.2V with 7.4mV/step option UVLO Programmable OSC Phase shift GND1 SW1 FB1 Driver & Control I2C Register & MTP Power Logic Control DCDC2 5.5V/2.5A I2C VID, 0.4V to 3.5875V with 12.5mV/step or 0.4V to 2.2V with 7.4mV/step option SW2 FB2 DCDC3 5.5V/4.5A I2C VID, 0.4V to 3.5875V with 12.5mV/step or 0.4V to 2.2V with 7.4mV/step option SW3 FB3 DCDC4 5.5V/2A I2C VID, 0.4V to 3.5875V with 12.5mV/step SW4 FB4 OUT4 300mA/700mA LDO5 Driver & Control OUT5 Control Logic VIN1 VIN3 AGND 10mA LDORTC Driver & Control Driver & Control 300mA LDO3 Driver & Control OUTRTC OUT2/EN1 OUT3 VIN2 AVIN VIN5 GND2 VIN2 VIN4 SCL SDA PWRON RSTO EN Logic Figure 2: Functional Block Diagram

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 17 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. OPERATION The MPQ7920 provides a complete power management solution for automotive 5V systems, including infotainment, video recorders, and more . It integrates four 4-channel high- frequency, synchronous , rectified, step -down, switch-mode converter s and five low-dropout regulators. With all components inside a compact QFN-26 (3.5mmx4.5mm) package, it greatly reduces component count and PC B space. I2C and MTP interfaces provide an adjustable default output voltage, power-on sequence, and dynamic voltage scaling . In addition , the I2C provides powerful logic functions. See the Register Map section on page 26 for more details. Any State No Supply Power Off Thermal Shutdown (Following Shutdown Sequence) Power On Power-On Sequence Power-Off Sequence Detect the power-on factor DC/DC converters and LDOs turn on sequentially depending on the MTP and register settings RSTO switches high Detect power-off factor RSTO switches low AVIN > UVLO Rising Threshold AVIN < UVLO Falling Threshold Program MTP Detect MTP enter factor MTP Done, Reload MTP to I2C Registers Figure 3: Power Control State Machine Diagram Power Control State Machine Description The state machine (see Figure 3) has a number of status options, including no supply, power off, power-on sequence, power on, power -off sequence, program MTP, and shutdown. These statuses are described below. No Supply The PMIC’s input pin has a UVLO detection circuit. If the input voltage (AVIN) is below the UVLO rising threshold, all of the PMIC’s functions are disabled. Power Off All power rails are power ed off. When AVIN exceeds its rising UVLO, the PMIC enters the power-off state. In this state, the PMIC is always monitoring the power-on factors; once a power- on factor is detected, the device changes to the power-on sequence state.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 18 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. Power-On Sequence The DC/DC converters and LDOs turn on sequentially according to the order programmed by the MTP e-fuse. Power On The DC/DC converters and LDOs are turned on. The RSTO pin’s output switches high. In this state, the PMIC is always monitoring the power off and program MTP factors. Power-Off Sequence The PMIC enters this sequence when it detects the power off factors during a power on state . First, the RSTO is switched low, then the DC/DC converters and LDOs turn off sequentially according to the order programmed by the MTP e-fuse. Program MTP The PMIC shut s down all buck regulators and LDOs with the power-off sequence when entering program MTP mode. After MTP programming is complete, the PMIC reloads the MTP to the I2C registers and then monitors for power-on factors. Shutdown Event If the PMIC detects any of the conditions shown below, it immediately changes to a no supply or power off state, regardless of the current state.  If the input voltage is below the UVLO falling threshold, the device enters a no sup ply state.  If o ver-temperature protection (OTP) is triggered, the device enters a power-off state. Note: 11) If the PMIC enters a power-off state due to OTP being triggered, then LDORTC is off. Power-On Factor The PMIC has several power-on factors , including PWR_ON, thermal recovery, and EN1. These factors are described below. PWRON_ON If the PWRON pin is pulled to logic high (PWRON_MODE = 0) or there is a falling edge on the PWRON pin (PWRON_MODE = 1), the PMIC enter s the power-on sequence. See the PWRON Functions section on page 21 for more details. Thermal Recovery The part enters a power off state if the die temperature exceed s the thermal protection threshold. Once the die temperature falls below the threshold , the PMIC enter s the power-on sequence again. EN1 If pin 22 is selected as EN1, and EN1 is pulled to logic high (EN1_INV defines EN1’s active high) or EN1 is pulled to logic low ( EN1_INV defines EN1’s active low), then the power rails controlled by EN1 enter the power-on sequence. See the EN1 Functions section on p age 23 for more details. Power-On Sequence There are 16 time slots for the power-on sequence. All of the DC/DC converters and LDOs except OUTRTC LDO can be programmed between 0 and 15 time slots by the MTP e-fuse. The delay time between each time slot is adjustable with the MTP TIME_SLOT bits. The time does not change the switching frequency. RSTO switch es high with RSTO_DELAY time when the power-on sequence is complete. The DC/DC converter and LDO power-on sequence is set by POWE R_ON_SLOT_NO and PWR_ON_TIME_SLOT_MODE. See the MTP table on page 26 for more details. VIN DC/DC LDO Output Time Slot Number 1 2 3 13 Time Slot RSTO RSTO_DELAY No Supply PWRON 14 15 Time Slot Figure 4: Power-On Sequence

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 19 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. OUTRTC ON The OUTRTC LDO is always on if both VIN2 and AVIN are above their respective UVLO rising thresholds, regardless of any other pin statuses. OUTRTC turns off if either VIN2 or AVIN fall below their respective UVLO falling thresholds or if thermal shutdown is triggered. Other Buck Regulators and LDOs On The MPQ7920 provides a programmable power- on sequence. The MTP configuration table on page 26 shows bits to set the time slot number for each channel. Power-Off Factor The PMIC power -off factors are PWRON_OFF and EN1. They are described below. PWRON_OFF If the PWRON pin is pulled to logic low (PWRON_MODE = 0) or a falling edge on the PWRON pin (PWRON_MODE = 1), the PMIC enters a power-off sequence. See the PWRON Functions section on page 21 for more details. EN1 If pin 22 is selected as EN1, and EN1 is pulled to logic low (EN1_INV defines EN1 as active high) or EN1 is pulled to logic high ( EN1_INV defines EN1 as active low), then the power rails controlled by EN1 enter the power-off sequence. See the EN1 Functions section on page 23 for more details. Power-Off Sequence There are 16 time slots for the power-off sequence. All of the DC/DC converters and LDOs, except OUTRTC LDO, can be programmed between 0 and 15 time slots by the MTP e-fuse. The delay time between each time slot is adjustable with the MTP TIME_SLOT bits. The time does not change the switching frequency. The power-off sequence begins at the maximum used time slot number. Therefore, the power-off sequence does not always start from time slot 15. RSTO is pulled low prior to the DC/DC converters and LDOs starting to turn off. The DC/DC converter and LDO power-off sequence is set by POWER_OFF_SLOT_NO and POWER_OFF_SLOT_MODE. See the MTP table on page 26 for more details. VIN PWRON DC/DC LDO Output 15 14 13 2 1 0 Time Slot RSTO Power-Off Sequence No Supply UVLO Power-Off Time Slot Time Slot Number Figure 5: Power-Off Sequence (PWRON_MODE = 0)

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 20 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. Program MTP Programming the MTP e-fuse through the I2C interface must strictly follow the steps below: 1. Ensure that all bucks and LDOs have no load before programming the MTP e-fuse. 2. Write the correct MTP program password to register 0x26. 3. Set ENTER_MTP_MODE = 1 to enter MTP program mode. All buck regulators and LDOs shut down in this mode. 4. Write the desired content to the I2C registers. 5. Increase the VIN1 and AVIN power supply to between 6.4V and 6.5V with a minimum 150mA current capability. 6. Set PROGRAM_MTP = 1 to start the MTP e- fuse program. 7. The PMIC calculates the sum of all related I2C registers to be burned to the MTP register. The checksum result will also be written to the MTP register. 8. After the MTP write operation finishes (typically ta kes 100ms), the PMIC sets the PROGRAM_MTP bit to 0, and the I 2C register write protection is unlocked. ENTER_MTP_MODE is also set to 0. 9. After MTP programming, the MPQ7920 reloads the MTP to the related I 2C registers and the PWRON pin function is re -enabled. The buck and LDO regulators then power up based on their power -on factors. After the power-up sequence completes, I 2C communication is enabled. 10. Decrease the VIN1 and AVIN voltage to <5.5V, then restart the power supply for normal operation. During VIN power-up, before loading the MTP data into the I2C register, the PMIC do es a checksum calculation for all related MTP registers, then compares it with the checksum byte. If they match, the MTP data is loaded into the I2C register. If not, the I2C register uses the hard-coded default value. There is a n I2C register flag bit to indicate a checksum error.

1.7 Shutdown Sequence

If the input voltage is below the UVLO falling threshold or if the IC is over -temperature, the PMIC ent ers the shutdown sequence immediately. All of the DC /DC and LDO regulators turn off at the same time. RSTO DC/DC1 DC/DCx LDOx ... Shutdown Event Detected Figure 6: Shutdown Sequence High-Efficiency Buck Regulator Buck 1 through buck 4 are synchronous, step- down DC/DC converters that have built-in UVLO, soft start, compensation, and hiccup current limit protection. Fixed -frequency, constant-on-time (COT) control provides fast transient response. The switching clock is phase shifted from buck 1 through buck 4 during CCM operation. Buck 1 through buck 4 support 100% duty cycle mode. Power Supply and UVLO VIN1 is the power supply for buck 1. VIN2 is the power supply for buck 2, LDORTC, LDO2 , and LDO3. VIN3 is the power supply for buck 3. VIN4 is the supply for buck 4. VIN5 is the power supply for LDO4 and LDO5. AVIN is the power input to bias the internal logic blocks. VIN1, VIN2, VIN3, VIN4, VIN5, and AVIN have their own UVLO threshold s with proper hysteresis. Once AVIN ramps up and exceeds the UVLO rising threshold, the PWRON logic is enabled and ready to a ccept start -up and shutdown comma nds. LDORTC is active once VIN2 exceeds its rising threshold. Internal Soft Start Soft start is implemented to prevent the PMIC output voltage from overshooting during start-up. When the PMIC starts up, the internal circuitry of each power rail generates a soft -start voltage that ramps up from 0V. The soft-start period lasts until the voltage on the soft -start capacitor exceeds the reference voltage. At this point, the reference voltage takes over.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 21 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. For the four 4 -channel buck outputs, the soft- start time s are MTP-adjustable. For the LDO2 through LDO5 outputs, the soft -start time s are internally fixed at 50µs. For LDORTC, the soft - start slew rate is consistent at 25mV/µs. Output Discharge In order to discharge the output capacitor during the power-off sequence, there is a passive discharge path from the DC/DC converters’ and LDOs’ output to ground. The discharge path is turned on when its corresponding channel is disabled. The typical discharge resistance is 7Ω. The discharge function can be enabled or disabled through the I2C interface. Over-Voltage Protection (OVP) The MPQ7920 monitors the feedback voltage to detect an over-voltage condition. When the feedback voltage exceeds 120% of the target voltage, the controller turns off both the high-side MOSFET (HS-FET) and low-side MOSFET (LS- FET), and the discharge path is turn ed on. The part exit s this regulation period once the feedback v oltage falls below 110 % of the reference voltage. Over-Current Protection (OCP) If the peak inductor current reaches its limit (set via the I2C registers) when the HS-FET is on, OCP is triggered. The LS-FET is forced on until the inductor current drops to the valley current limit; then the HS-FET turns on again. The part does not exit OCP unless the inductor peak current falls below the limit. If the OCP time lasts for longer than 150µs (typical), the buck enters hiccup mode. System Control Signals PWRON Functions PWRON is an input pin to the IC that generates a power-on or power-off event. This pin can be configured to detect a level or a falling edge via the MTP. When the PWRON_MODE bit = 1, the PWRON_DEBOUNCE_TIMER bit can set the PWRON pin ’s debounce timer to filter out mechanical switch short press noise. When the PWRON_MODE bit = 0, PWRON works as an enable pin. Apply a logic high voltage to turn the PMIC on; apply a logic low voltage to turn the PMIC off. PWRON_MODE = 1 (Edge Trigger) Power On If AVIN is above the UVLO threshold and PWRON is asserted low for longer than PWRON_DEBOUNCE_TIMER when the PMIC is powered off , the power -on sequence begins. The power -on sequence must complete , and then the PWRON detection function is re - enabled. Power Off If PWRON assert s low for longer than PWRON_DEBOUNCE_TIMER when the device is powered on , the power -off sequence begins. The MPQ7920 turns off all regulators and LDOs (except OUTRTC). The power -off sequence is pre-programmed by the MTP e-fuse. OUT1 OUT4 RSTO PWRON Debounce Timer Remains in the power on-state when PWRON stays low Figure 7: PWRON_MODE = 1, Press PWRON to Power On If the PWRON pin is still pulled low after the power-off sequence completes , the MPQ7920 remains in its power off state. If the PWRON pin is pulled high after the power -off sequence completes, the MPQ7920 continues the power-off sequence.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 23 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. EN1 Functions EN1 is a multi-function pin with an LDO2 output. If the EN1 function is selected on pin 22, the MPQ7920 supports the operations described below. The EN1 pin can be used to control the power rails’ on/off sequence. This is very useful for non- I2C interface applications. Figure 10 shows EN1 function. For example, EN1 controls buck 2 and buck 3. When EN1 is pulled low, buck 2 and buck 3 power off sequentially. When EN1 is pulled high, buck 2 and buck 3 power on sequentially. EN1_INV defines EN1 as active high or active low. PWRON has higher priority than EN1, so when PWRON is pulled low, all power rails enter the power-off sequence. The b uck and LDO regulator enable/disable functions are controlled by both the PWRON and EN1 pins.

3.2 Thermal Warning and Shutdown

Thermal warning and shutdown prevent the part from operating at exceedingly high temperatures. When the silicon die temperature exceeds 120°C, the MPQ7920 sets the OTWARNING bit to 1 . When th e temperature falls to 97°C, this bit can be cleared by writing 1 to it. If the die temperature exceeds 153°C, the MPQ7920 sets the OTEMPP bit to 1, and the system enters the shutdown sequence . When the temperature falls to 130°C, the regulator enters the power-on sequence again. I2C Timing The PMIC’s I2C interface is powered by an internal, fixed, 2V power supply. When VIN exceeds its under-voltage lockout ( UVLO) threshold during VIN power -up, this indicates that the 2V LDO power supply is ready. The I2C function is disabled during the power-on sequence. When the power -on sequence is complete (for all enabled power rails), the I2C is available (see Figure 11). When the I2C is not used, SCL and SDA should be pulled high by a resistor. VIN Internal I2C Command Power-On Sequence VIN reaches UVLO System POR Delay From this point, the I2C can be operated normally Figure 11: I2C Timing Graph

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 25 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. S Slave Address Wr A Register Address K Read Data KA A P Master to Slave Slave to Master A = Acknowledge (SDA = Low) S = Start Condition P = Stop ConditionNA = NOT Acknowledge (SDA = High) 8 bits 8 bits 8 bits Sr Slave Address RD NA 8 bits Wr (Write) = 0 Rd (Read) = 1 Register address to read specified Read register data from current register location Sr = Repeat Start Condition Figure 15: I2C Read Example – Read Single Register

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 26 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. REGISTER DESCRIPTION MTP E-Fuse Configuration Table OFFSET NAME D7 D6 D5 D4 D3 D2 D1 D0

00 CTL0 DVS SLEW RATE FREQUENCY N/A PWRON_DEBOUNCE_TIMER N/A

01 CTL1 RSTO_MODE RSTO_DELAY RSTO_PFI_THLD N/A

02 CTL2 N/A N/A TIME_SLOT

PWR_ON_ TIME_SLOT_ MODE PWR_OFF_ TIME_SLOT_ MODE Buck 1

04 N/A OVPEN1 DISCHGEN

05 ILIM1 PHASE_DELAY1 SOFTSTART1 N/A

06 POWER_OFF_SLOT_NO_B1 POWER_ON_SLOT_NO_B1

08 N/A OVPEN2 DISCHGEN

09 ILIM2 PHASE_DELAY2 SOFTSTART2 N/A

0A POWER_OFF_SLOT_NO_B2 POWER_ON_SLOT_NO_B2 Buck 3 0C N/A OVPEN3 DISCHGEN MODE BUCK3 N/A 0D ILIM3 PHASE_DELAY3 SOFTSTART3 0E POWER_OFF_SLOT_NO_B3 POWER_ON_SLOT_NO_B3 Buck 4 BUCK4_VREF: 0.4V to 3.5875V/12.5mV

10 N/A OVPEN4 DISCHGEN

11 ILIM4 PHASE_DELAY4 SOFTSTART4 N/A

12 POWER_OFF_SLOT_NO_B4 POWER_ON_SLOT_NO_B4

13 RTCL

DO RTCLDO_VREF: 0.65V to 3.5875V/12.5mV LDO2 LDO2_VREF: 0.65V to 3.5875V/12.5mV

15 N/A N/A DISCHGEN

_LDO2 I2C_SLAVE_ADDRESS

16 POWER_OFF_SLOT_NO_LDO2 POWER_ON_SLOT_NO_LDO2

LDO3_VREF: 0.65V to 3.5875V/12.5mV

18 N/A N/A DISCHGEN

_LDO3 N/A N/A

19 POWER_OFF_SLOT_NO_LDO3 POWER_ON_SLOT_NO_LDO3

LDO4_VREF: 0.65V to 3.5875V/12.5mV 1B N/A ILIM_LDO4 DISCHGEN _LDO4 N/A N/A 1C POWER_OFF_SLOT_NO_LDO4 POWER_ON_SLOT_NO_LDO4 LDO5 LDO5_VREF: 0.65V to 3.5875V/12.5mV 1E N/A ILIM_LDO5 DISCHGEN _LDO5 N/A N/A 1F POWER_OFF_SLOT_NO_LDO5 POWER_ON_SLOT_NO_LDO5

20 Mode PARALLEL

PWRON_M ODE EN_EN1 _PIN N/A N/A

21 EN1 EN1_INV EN1_POWER_RAILS_CONTROL

22 EN EN_BUCK

EN_BUCK

2 EN_BUCK3 EN_

BUCK4 EN_LDO2 EN_LDO3 EN_LDO4 EN_LDO5 23 ID1 MTP configuration code. “0x00” refers to a standard MPQ7920. “0x03” refers to the MPQ7920-0003 part. 24 ID2 MTP revision number: This is where the revision number is stored if the user must update the MTP value.

25 CRC

Checksum of MTP registers 0x00 to 0x24: While writing the I2C register’s data to the MTP, the IC initiates a checksum of all related I2C registers, and writes the result in this byte. During power-up, the IC calculates and compares the MTP data with the 0x25 register’s content. If they match, the MTP data is loaded to the I2C register; otherwise, the I2C register ignores the MTP data and uses the default setting. Notes: 12) The default register value is based on the MPQ7920-0003 specifications.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 27 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. REGISTER DESCRIPTION MTP E-Fuse Table Description Bits Bit Name Default Description D[7:6] DVS_SLEW_ RATE 10 Voltage scaling slew rate for the buck 1 to buck 4 converters. The soft-start slew rate is determined by the SOFTSTART bits. 00: Reserved 01: Reserved 10: 8mV/µs 11: 4mV/µs D[5:4] FREQUENCY 10 Switching frequency set bit. 00: 1.1MHz 01: 1.65MHz 10: 2.2MHz 11: 2.75MHz D[2:1] PWRON_ DEBOUNCE_ TIMER Sets the PWRON pin’s debounce timer. It is valid only if PWRON_MODE is set to 1. (see the PWRON_MODE section on page 21 for more information). The debounce time is not related to the PMIC switching frequency. 00: 0.5ms 01: 10ms 10: 40ms 11: 160ms D[7:6] RSTO_MODE 01 Sets RSTO behavior. 00: Do not monitor any power rails. Switch low when the power-off sequence starts or VIN1 drops below the under-voltage lockout (UVLO) threshold. Switch high when the RSTO delay is complete 01: Monitor buck 4’s PG. RSTO goes high once buck 4’s PG is OK after the RSTO delay. If buck 4 is disabled by the I2C, PG4 is always high. When PG4 goes low, RSTO has no delay 10: Monitor the VIN1 voltage (see the RSTO_PFI_THLD section below for details) . RSTO goes high when VIN1 > UVLO threshold. RSTO goes low when VIN1 < UVLO threshold. RSTO switches high after a delay; RSTO switches low with no delay. RSTO monitors VIN1 while the device is on (if VIN1 > UVLO and PWRON are active) 11: Monitor all enabled buck and LDO power rails (including RTCLDO). RSTO goes high after the enabled bucks and LDOs have an OK PG, and the RS TO delay is complete. When any PG goes low, RSTO has no delay D[5:4] RSTO_DELAY 01 Resets the output switching high delay. The RSTO delay time is no t related to the PMIC switching frequency. 00: 100ms 01: 50ms 10: 10ms 11: 1ms D[3:2] RSTO_PFI_ THLD 10 Sets the VIN1 rising threshold when RSTO_MODE is set to 10. 00: 2.7V 01: 2.9V 10: 4.0V 11: 4.4V D[3:2] TIME_SLOT 00 Sets the power-on and power -off sequences’ time slot s and intervals. The se sequences share the same time slot value. The time slot value is not related to the PMIC switching frequency. 00: 0.5ms 01: 2ms 10: 8ms 11: 16ms

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 28 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. REGISTER DESCRIPTION (continued) MTP E-Fuse Table Description Bits Name Default Description D[1] PWR_ON_ TIME_SLOT _MODE Selects the power-on sequence’s time slot mode. 0: The time slot is a fixed number set by TIME_SLOT 1: The time slot increases linearly in the following ways:  Time slot 0 to slot 3 has a (TIME_SLOT x 1) interval  Time slot 3 to slot 7 has a (TIME_SLOT x 2) interval  Time slot 7 to slot 11 has a (TIME_SLOT x 4) interval  Time slot 11 to slot 15 has a (TIME_SLOT x 8) interval Time Slot Number 0.5ms 0.5ms 0.5ms 3 4 1ms 1ms 6 7 1ms1ms 2ms 2ms 2ms 2ms 4ms 4ms 4ms 2 11 12 13 14 15 VOUT TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 Example: 4ms In a standard application, the power-on sequence ends at the maximum used time slot value. For example, if time slot 7 is the maximum value (no slot number above 7 is used) during the power-on sequence, the counter only works until time slot 7. Then the power- on sequence is complete, and the higher time slots are not executed. D[0] PWR_OFF_ TIME_SLOT _MODE Selects the power-off sequence’s time slot mode. 0: The time slot is a fixed number set by TIME_SLOT 1: The time slot increases linearly in the following ways:  Time slot 0 to slot 3 has a (TIME_SLOT x 1) interval  Time slot 3 to slot 7 has a (TIME_SLOT x 2) interval  Time slot 7 to slot 11 has a (TIME_SLOT x 4) interval  Time slot 11 to slot 15 has a (TIME_SLOT x 8) interval Time Slot Number 0.5ms0.5ms0.5ms1ms1ms1ms 1ms2ms 2ms 2ms 2ms4ms4ms4ms 21112131415 VOUT TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx1 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx2 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx4 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 TIME_ SLOTx8 Example: 1 034567 4ms In a standard application, the power-off sequence starts at the maximum used time slot. For example, if time slot 7 is the maximum used number (no slot number above 7 is used), during the power-off sequence, the counter only works from time slot 7 to time slot 0, then the power-off sequence is complete. The higher time slots are not executed.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 29 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. REGISTER DESCRIPTION (continued) MTP E-Fuse Table Description Bits Name Default Description D[6:0] BUCK1_VREF BUCK2_VREF BUCK3_VREF BUCK4_VREF RTCLDO_VREF LDO2_VREF LDO3_VREF LDO4_VREF LDO5_VREF 1150mV 1500mV 1150mV 1800mV 3300mV 1800mV 1800mV 1100mV 1800mV Sets the internal reference voltage . Buck outputs are f rom 400mV to 3587.5mV with 12.5mV per step . LDO outputs are from 650mV to 3587.5mV with 12.5mV per step. D[6:0] = 000 0000: 400mV D[6:0] = 000 0001: 412.5mV ... D[6:0] = 111 1111: 3587.5mV See Table 2 on page 38 for details. D[6] OVPEN1 OVPEN2 OVPEN3 OVPEN4 Enable bit for buck 1 through buck 4’s output over-voltage protection (OVP) function. 0: Disable the over-voltage protection (OVP) function 1: Enable the OVP function D[5] DISCHGEN1 DISCHGEN2 DISCHGEN3 DISCHGEN4 Enable bit for buck 1 through buck 4’s output discharge function. 0: Disable the discharge function 1: Enable the discharge function D[4] MODEBUCK1 MODEBUCK2 MODEBUCK3 MODEBUCK4 Selects the mode (auto-PFM/PWM mode or forced PWM mode) 0: Auto-PFM/PWM mode 1: Forced PWM mode (FPWM) D[7:6] ILIM1 ILIM3 11 Configures the current limit threshold for the buck regulator. 00: 4.6A typical high-side peak current limit 01: 6.6A typical high-side peak current limit 10: 7.6A typical high-side peak current limit 11: 9.3A typical high-side peak current limit D[7:6] ILIM2 ILIM4 11 Configures the current limit threshold for the buck regulator. 00: 2.7A typical high-side peak current limit 01: 3.9A typical high-side peak current limit 10: 5.1A typical high-side peak current limit 11: 6.1A typical high-side peak current limit D[5:4] PHASE_DELAY1 PHASE_DELAY2 PHASE_DELAY3 PHASE_DELAY4 Sets the phase delay for buck 1 through buck 4. 00: 0° delay 01: 90° delay 10: 180° delay 11: 270° delay D[3:2] SOFTSTART1 SOFTSTART2 SOFTSTART3 SOFTSTART4 Soft-start time setting bit for each buck regulator. The s oft-start time is between 10% and 90% of the target output voltage. 00 :150μs 01: 300μs 10: 610μs 11: 920μs

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 30 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. REGISTER DESCRIPTION (continued) MTP E-Fuse Table Description Bits Name Default Description D[7:4] POWER_OFF_SLOT_ NO_B1 POWER_OFF_SLOT_ NO_B2 POWER_OFF_SLOT_ NO_B3 POWER_OFF_SLOT_ NO_B4 POWER_OFF_SLOT_ NO_LDO2 POWER_OFF_SLOT_ NO_LDO3 POWER_OFF_SLOT_ NO_LDO4 POWER_OFF_SLOT_ NO_LDO5 0000 0110 0000 0110 0111 0111 0111 1001 This bit sets e ach power rail ’s time slot number during the power-off sequence (see the TIME_SLOT section on page 2 7 and the PWR_OFF_TIME_SLOT_MODE section on page 28 for more details). The delay time between neighboring slots are not related to the PMIC default switching frequency. 0000: Time slot 0 0001: Time slot 1 0010: Time slot 2 0011: Time slot 3 0100: Time slot 4 0101: Time slot 5 0110: Time slot 6 0111: Time slot 7 1000: Time slot 8 1001: Time slot 9 1010: Time slot 10 1011: Time slot 11 1100: Time slot 12 1101: Time slot 13 1110: Time slot 14 1111: Time slot 15 D[3:0] POWER_ON_SLOT_ NO_B1 POWER_ON_SLOT_ NO_B2 POWER_ON_SLOT_ NO_B3 POWER_ON_SLOT_ NO_B4 POWER_ON_SLOT_ NO_LDO2 POWER_ON_SLOT_ NO_LDO3 POWER_ON_SLOT_ NO_LDO4 POWER_ON_SLOT_ NO_LDO5 0000 0110 0000 0110 0111 0111 0111 1001 This bit sets e ach power rail ’s time slot number during the power-on sequence (see the TIME_SLOT section on page 2 7 and the PWR_ON_TIME_SLOT_MODE section on page 28 for more detail s). The delay time between neighboring slots are not related to the PMIC default switching frequency. 0000: Time slot 0 0001: Time slot 1 0010: Time slot 2 0011: Time slot 3 0100: Time slot 4 0101: Time slot 5 0110: Time slot 6 0111: Time slot 7 1000: Time slot 8 1001: Time slot 9 1010: Time slot 10 1011: Time slot 11 1100: Time slot 12 1101: Time slot 13 1110: Time slot 14 1111: Time slot 15 D[5] DISCHGEN_LDO2 DISCHGEN_LDO3 DISCHGEN_LDO4 DISCHGEN_LDO5 Enable bit for LDO2 through LDO5’s output discharge function. 0: Disable the discharge function 1: Enable the discharge function D[4:0] I2C_SLAVE_ ADDRESS 01001 Sets the A5 to A1 bit of the slave I2C address (see the I2C Bus Slave Address section on page 34 for more details). D[6] ILIM_LDO4 ILIM_LDO5 0 Selects the LDO4 and LDO5 current limit. 0: Lower current limit supports 300mA IOUT 1: Higher current limit supports 700mA IOUT

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 31 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. REGISTER DESCRIPTION (continued) MTP E-Fuse Table Description Bits Name Default Description D[7] PARALLEL_1 0 Sets buck 1 and buck 3 to w ork in parallel mode. Use FB1 as the feedback pin. After entering parallel mode, buck 3’s I2C/MTP register is invalid. Parallel mode only takes effect during VIN power-up. After powering up, the PMIC does not respond to changes of this bit in the I2C register. The current limit is doubled based on buck 1’s register setting. 0: Buck 1 and buck 3 do not work in parallel mode 1: Buck 1 and buck 3 work in parallel mode D[6] PARALLEL_2 0 Sets buck 2 and buck 4 to work in parallel mode. Use FB2 as the feedback pin . After entering parallel mode, buck 4’s I2C/MTP register is invalid. Parallel mode only takes effect during VIN power-up. After powering up, the PMIC does not respond to changes on this bit. The current limit is doubled based on buck 2’s register setting. 0: Buck 2 and buck 4 do not work in parallel mode 1: Buck 2 and buck 4 work in parallel mode D[5] PWRON_ MODE 0 This bit defines the PWRON pin’s behavior (level trigger or falling edge trigger). 0: Level trigger. This functions like an EN pin. When the PWRON pin’s input voltage exceeds the rising threshold, the PMIC begins the power-on sequence 1: Falling edge trigger. When the PWRON pin detects a high -to-low transition, if the PMIC is off, the PMIC starts the power-on sequence after a delay. If the PMIC is on, the PMIC begins the power-off sequence after a delay. The delay time is edited by PWRON_DEBOUNCE_TIMER D[4] EN_EN1_PIN 0 Sets pin 22 as the LDO2 output or EN1 pin. EN1 is an input pin to turn several power rails on and off. EN1_POWER_RAILS_CONTROL defines which power rails are controlled by EN1; EN1_INV defines the EN1 pin’s active low or active high. 0: Pin 22 is an LDO2 output 1: Pin 22 is EN1 D[7] EN1_INV 1 Sets EN1 to active low or active high. 0: A low-level input to EN1 turns on the related power rails 1: A high-level input voltage to EN1 turns on the related power rails D[6:0] EN1_ POWER_ RAILS_ CONTROL 0000111 This bit sets which power rails are controlled by EN1. Buck 1 Buck 2 Buck 3 Buck 4 LDO3 LDO4 LDO5 From D[6] to D[0], each bit controls 1 power rail. 0: EN1 does not control this power rail’s on/off sequence 1: EN1 controls this power rail’s on/off sequence D[7:0] EN_BUCK1 EN_BUCK2 EN_BUCK3 EN_BUCK4 EN_LDO2 EN_LDO3 EN_LDO4 EN_LDO5 0xFF Enable control bit for each power rail. 0: Disable 1: Enable

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 32 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. Table 1: Output Reference Voltage Chart (Used for 12.5mV DVS Resolution) D[7:0] VREF (mV) D[7:0] VREF (mV) D[7:0] VREF (mV) 00000000 400 01010110 1475 10101100 2550 00000001 412.5 01010111 1487.5 10101101 2562.5 00000010 425 01011000 1500 10101110 2575 00000011 437.5 01011001 1512.5 10101111 2587.5 00000100 450 01011010 1525 10110000 2600 00000101 462.5 01011011 1537.5 10110001 2612.5 00000110 475 01011100 1550 10110010 2625 00000111 487.5 01011101 1562.5 10110011 2637.5 00001000 500 01011110 1575 10110100 2650 00001001 512.5 01011111 1587.5 10110101 2662.5 00001010 525 01100000 1600 10110110 2675 00001011 537.5 01100001 1612.5 10110111 2687.5 00001100 550 01100010 1625 10111000 2700 00001101 562.5 01100011 1637.5 10111001 2712.5 00001110 575 01100100 1650 10111010 2725 00001111 587.5 01100101 1662.5 10111011 2737.5 00010000 600 01100110 1675 10111100 2750 00010001 612.5 01100111 1687.5 10111101 2762.5 00010010 625 01101000 1700 10111110 2775 00010011 637.5 01101001 1712.5 10111111 2787.5 00010100 650 01101010 1725 11000000 2800 00010101 662.5 01101011 1737.5 11000001 2812.5 00010110 675 01101100 1750 11000010 2825 00010111 687.5 01101101 1762.5 11000011 2837.5 00011000 700 01101110 1775 11000100 2850 00011001 712.5 01101111 1787.5 11000101 2862.5 00011010 725 01110000 1800 11000110 2875 00011011 737.5 01110001 1812.5 11000111 2887.5 00011100 750 01110010 1825 11001000 2900 00011101 762.5 01110011 1837.5 11001001 2912.5 00011110 775 01110100 1850 11001010 2925 00011111 787.5 01110101 1862.5 11001011 2937.5 00100000 800 01110110 1875 11001100 2950 00100001 812.5 01110111 1887.5 11001101 2962.5 00100010 825 01111000 1900 11001110 2975 00100011 837.5 01111001 1912.5 11001111 2987.5 00100100 850 01111010 1925 11010000 3000 00100101 862.5 01111011 1937.5 11010001 3012.5 00100110 875 01111100 1950 11010010 3025 00100111 887.5 01111101 1962.5 11010011 3037.5

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 33 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. Table 1: Output Reference Voltage Chart (Used for 12.5mV DVS Resolution) (continued) D[7:0] VREF (mV) D[7:0] VREF (mV) D[7:0] VREF (mV) 00101000 900 01111110 1975 11010100 3050 00101001 912.5 01111111 1987.5 11010101 3062.5 00101010 925 10000000 2000 11010110 3075 00101011 937.5 10000001 2012.5 11010111 3087.5 00101100 950 10000010 2025 11011000 3100 00101101 962.5 10000011 2037.5 11011001 3112.5 00101110 975 10000100 2050 11011010 3125 00101111 987.5 10000101 2062.5 11011011 3137.5 00110000 1000 10000110 2075 11011100 3150 00110001 1012.5 10000111 2087.5 11011101 3162.5 00110010 1025 10001000 2100 11011110 3175 00110011 1037.5 10001001 2112.5 11011111 3187.5 00110100 1050 10001010 2125 11100000 3200 00110101 1062.5 10001011 2137.5 11100001 3212.5 00110110 1075 10001100 2150 11100010 3225 00110111 1087.5 10001101 2162.5 11100011 3237.5 00111000 1100 10001110 2175 11100100 3250 00111001 1112.5 10001111 2187.5 11100101 3262.5 00111010 1125 10010000 2200 11100110 3275 00111011 1137.5 10010001 2212.5 11100111 3287.5 00111100 1150 10010010 2225 11101000 3300 00111101 1162.5 10010011 2237.5 11101001 3312.5 00111110 1175 10010100 2250 11101010 3325 00111111 1187.5 10010101 2262.5 11101011 3337.5 01000000 1200 10010110 2275 11101100 3350 01000001 1212.5 10010111 2287.5 11101101 3362.5 01000010 1225 10011000 2300 11101110 3375 01000011 1237.5 10011001 2312.5 11101111 3387.5 01000100 1250 10011010 2325 11110000 3400 01000101 1262.5 10011011 2337.5 11110001 3412.5 01000110 1275 10011100 2350 11110010 3425 01000111 1287.5 10011101 2362.5 11110011 3437.5 01001000 1300 10011110 2375 11110100 3450 01001001 1312.5 10011111 2387.5 11110101 3462.5 01001010 1325 10100000 2400 11110110 3475 01001011 1337.5 10100001 2412.5 11110111 3487.5 01001100 1350 10100010 2425 11111000 3500 01001101 1362.5 10100011 2437.5 11111001 3512.5 01001110 1375 10100100 2450 11111010 3525 01001111 1387.5 10100101 2462.5 11111011 3537.5

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 34 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. Table 1: Output Reference Voltage Chart (Used for 12.5mV DVS Resolution) (continued) D[7:0] VREF (mV) D[7:0] VREF (mV) D[7:0] VREF (mV) 01010000 1400 10100110 2475 11111100 3550 01010001 1412.5 10100111 2487.5 11111101 3562.5 01010010 1425 10101000 2500 11111110 3575 01010011 1437.5 10101001 2512.5 11111111 3587.5 01010100 1450 10101010 2525 N/A N/A 01010101 1462.5 10101011 2537.5 N/A N/A I2C Bus Slave Address The slave address is a 7-bit address followed by an 8th read or write (R/W) data direction bit. The A5 to A1 bits can be configured by the MTP e-Fuse. A7 A6 A5 A4 A3 A2 A1 Setting Value 1 1 0* 1* 0* 0* 1* Notes: 13) This bit is configurable by the MTP e-fuse. 14) By default, the slave address is 0x69, A[7:1] = 110 1001.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 35 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. I2C REGISTER MAP Add (Hex) NAME R/W D7 D6 D5 D4 D3 D2 D1 D0

00 CTL0 R/W DVS SLEW RATE FREQUENCY RESERVED

(16) PWRON_DEBOUNCE _TIMER RESERVED

01 CTL1 R/W RSTO_MODE RSTO_DELAY RSTO_PFI_THLD RESERVED

02 CTL2 R/W RESERVED RESERVED TIME_SLOT

PWR_ON_ TIME_ SLOT_ MODE PWR_OFF _TIME_ SLOT_ MODE BUCK1

04 R/W RESERVED OVPEN1 DISCHG

05 R/W ILIM1 PHASE_DELAY1 SOFTSTART1 RESERVED

06 R/W POWER_OFF_SLOT_NO_B1 POWER_ON_SLOT_NO_B1

08 R/W RESERVED OVPEN2 DISCHG

09 R/W ILIM2 PHASE_DELAY2 SOFTSTART2 RESERVED

0A R/W POWER_OFF_SLOT_NO_B2 POWER_ON_SLOT_NO_B2 BUCK3 0C R/W RESERVED OVPEN3 DISCHG EN3 MODE BUCK3 RESERVED 0D R/W ILIM3 PHASE_DELAY3 SOFTSTART3 RESERVED 0E R/W POWER_OFF_SLOT_NO_B3 POWER_ON_SLOT_NO_B3 BUCK4 R/W BUCK4_VREF: 0.4V to 3.5875V/12.5mV

10 R/W RESERVED OVPEN4 DISCHG

11 R/W ILIM4 PHASE_DELAY4 SOFTSTART4 RESERVED

12 R/W POWER_OFF_SLOT_NO_B4 POWER_ON_SLOT_NO_B4

13 RTCLD

O R/W RTCLDO_VREF: 0.65V to 3.5875V/12.5mV LDO2 R/W LDO2_VREF: 0.65V to 3.5875V/12.5mV

15 R/W RESERVED RESERVED DISCHG

EN_LDO2 I2C_SLAVE_ADDRESS

16 R/W POWER_OFF_SLOT_NO_LDO2 POWER_ON_SLOT_NO_LDO2

R/W LDO3_VREF: 0.65V to 3.5875V/12.5mV

18 R/W RESERVED RESERVED DISCHG

EN_LDO3 RESERVED RESERVED

19 R/W POWER_OFF_SLOT_NO_LDO3 POWER_ON_SLOT_NO_LDO3

R/W LDO4_VREF: 0.65V to 3.5875V/12.5mV 1B R/W RESERVED ILIM_LDO4 DISCHG EN_LDO4 RESERVED RESERVED 1C R/W POWER_OFF_SLOT_NO_LDO4 POWER_ON_SLOT_NO_LDO4 LDO5 R/W LDO5_VREF: 0.65V to 3.5875V/12.5mV 1E R/W RESERVED ILIM_LDO5 DISCHG EN_LDO5 RESERVED RESERVED 1F R/W POWER_OFF_SLOT_NO_LDO5 POWER_ON_SLOT_NO_LDO5

20 Parallel

Mode R/W PARALLEL_1 (15) PARALLEL_ 2 (15) PWRON_ MODE (15) EN_EN1_ PIN (15) RESERVED

21 Standby

1 R/W EN1_INV* EN1_POWER_RAILS_CONTROL*

22 EN R/W EN_BUCK1 EN_BUCK2 EN_

BUCK3 EN_BUCK4 EN_LDO2 EN_LDO3 EN_LDO4 EN_LDO5 MTP_ CTL R/W MTP configuration code: "0x00" means the standard MPQ7920. "0x03" means the MPQ7920-0003. 24 R/W MTP revision number: the revision number is stored here, in case the user must update the MTP.

25 R/W ENTER_

MTP_MODE PROGRAM_ MTP RESERVED

26 W MTP Program Password

27 Status1 R PGLDO4 PGLDO3 PGLDO2 PGRTC PGBUCK4 PGBUCK3 PGBUCK2 PGBUCK1

28 Status2 R OTWARNING OTEMPP CRC_

29 ID2 R VENDOR ID RESERVED PGLDO5 Current MTP Page Index

Notes:

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP MPQ7920 Rev. 1.0 www.MonolithicPower.com 36 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved 15) The I2C bits do not control the real circuitry. Only the MTP bits control those functions. The MTP value only reloads the circuitry when the PWRON pin turns off, the MTP is configured, or AVIN > UVLO threshold. 16) Reserved bits must be written to 0. Register Description Most of the register bits share the same description as the MTP table. Table 2 lists the descriptions of different register bits. The I2C register’s default value is determined by the MTP table. The I2C register can be reset to the hard coded default values under two conditions: 1. There is a CRC error while loading the MTP. 2. The MTP page is 0. Over-temperature protection ( OTP) does not reset the I2C register. Table 2: I2C Register Description Bits Name Default Description D[7] ENTER_MTP_ MODE 0 Set this bit to 1 to enter the pre-MTP configuration mode. After MTP configuration is complete, this bit auto-resets to 0. D[6] PROGRAM_ MTP 0 Set this bit to 1 to force the PMIC to execute the MTP configuration action. After MTP configuration is complete, this bit auto-resets to 0. D[X] PGx 0 Power good indicator for bucks and LDO s. PG = 1 when the output voltage exceeds 90% of the reference voltage; PG = 0 when the output voltage is below 80% of the reference voltage. During I2C-controlled dynamic voltage scaling, the PG deglitch timer blank s the possible PG glitch. These PG bits change dynamically to indicate the power good of each buck’s and LDO’s status. D[7] OTWARNING 0 Die temperature early warning bit. If this bit is high, the die temperature exceeds 120°C. This bit latches once it is triggered. Write 1 to this bit to clear it. D[6] OTEMPP 0 Over-temperature indicator. If this bit is high, the IC is in thermal shutdown . This bit latches once it is triggered. Write 1 to this bit to clear it. D[7:4] VENDOR_ID 1000 Vendor identification. D[4] CHECKSUM_ FLAG 0 D[4] = 1: The current MTP page has a CRC or checksum error D[4] = 0: The current MTP’s data passes the CRC test D[1:0] CURRENT_ MTP_PAGE_ INDEX This bit stores the current MTP page index information. The IC cannot access the MTP again when D[1:0] = 10b. The MPQ7920 only can be configured two times. 00: The default page. Two other pages can be used 01: First page 10: Second page 11: Reserved

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 37 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved.

APPLICATION INFORMATION

For most applications, u se a 0.47µH to 2.2µH inductor with a DC current rating at least 25% percent greater than the maximum load current. For highest efficiency, use an inductor with a DC resistance less than 15mΩ. For most designs, the inductance value can be calculated with Equation (1): OUT IN OUT IN L OSC V (V V )L V I f Where ∆IL is the inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be estimated with Equation (2): III L LOAD)MAX(L  (2) Use a n inductor with higher inductance to improve efficiency under light -load conditions (<100mA). Selecting the Step -Down Converter Input Capacitor The step-down converter has a discontinuous input current, and requires a capacitor to supply the AC current to the converter while maintaining the DC input voltage. Use low-ESR capacitors for the best performance. Use ceramic capacitors with X5R or X7R dielectrics because of their low ESR and small temperature coeff icients. For most applications, use a 22µF capacitor. Since C1 absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (3):   IN OUT IN OUTLOAD1C V V1V VII (3) The worst-case condition occurs at VIN = 2VOUT, estimated with Equation (4): II LOAD 1C  (4) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high-quality ceramic capacitor (e.g. 0.1μF) placed as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by the capacitance can be calculated with Equation (5): LOAD OUT OUT IN INSW IN I V VV1 f C1 V V Selecting the Step -Down Converter Output Capacitor The output capacitor for the step-down regulator maintains the DC output voltage. Use ceramic, tantalum, or low-ESR electrolytic capacitors. For best results, use low-ESR capacitors to keep the output voltage ripple low. For most applications, 22µF x 2 ceramic capacitors are recommended. The output voltage ripple can be estimated with Equation (6): OUT OUT OUT ESR SW 1 IN S VV 1V 1 R f L V 8 f C2 (6) Where L1 is the inductor value , and RESR is the equivalent series resistance (ESR) value of the output capacitor. For ceramic capacitors, the capacitance dominates the impedance at the switching frequency and causes the majority of the output voltage ripple. For simplification, the output voltage ripple can be calculated with Equation (7): OUT OUT OUT 2 SW 1 IN VVΔV1 8 f L C2 V For tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be estimated with Equation (8): OUT OUT OUT ESR INSW 1 VVΔV 1 R f L V The characteristics of the output capacitor also affect the stability of the regulation.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 38 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. Table 3 lists the recommended components for DC/DC and LDO converters. Table 3: Recommended External Components for DC/DC and LDO Converters (17) Component Value Notes VIN1 CIN 22μF 0805 size/10V ceramic capacitor VIN2 CIN 22μF 0805 size/10V ceramic capacitor VIN3 CIN 22μF 0805 size/10V ceramic capacitor VIN4 CIN 22μF 0805 size/10V ceramic capacitor VIN5 CIN 10μF 0805 size/10V ceramic capacitor AVIN CIN 0.1μF 0603 size/10V ceramic capacitor Buck 1 COUT 22μF x 0805 size/10V ceramic capacitor Buck 1 L 1μH ISAT > current limit Buck 2 COUT 22μF x 0805 size/10V ceramic capacitor Buck 2 L 1.5μH ISAT > current limit Buck 3 COUT 22μF x 0805 size/10V ceramic capacitor Buck 3 L 1μH ISAT > current limit Buck 4 COUT 22μF x 0805 size/10V ceramic capacitor Buck 4 L 1.5μH ISAT > current limit RTCLDO COUT 1μF 0603 size/6.3V ceramic capacitor LDO2 COUT 2.2μF 0603 size/6.3V ceramic capacitor LDO3 COUT 2.2μF 0603 size/6.3V ceramic capacitor LDO4 COUT 2.2μF 0603 size/6.3V ceramic capacitor LDO5 COUT 2.2μF 0603 size/6.3V ceramic capacitor RSTO pull- up resistor 100kΩ 0603 or 0402 size film resistor AVIN series resistor to VIN1 4.7Ω 0603 or 0402 size film resistor Note: 17) The recommended external components are based on Figure 16 on page 39. PCB Layout Guidelines (18) PCB layout is critical for stable operation. It is recommended to use a 4-layer board for optimal performance. For the best results, refer to Figure 16 and follow the guidelines below: 1. Connect the input ground to the GND pin using the shortest and widest trace possible. 2. Connect the input capacitor to the VIN pin using the shortest and widest trace possible. 3. Ensure FB1 through FB4 are Kelvin - connected to the buck 1 to buck 4 output capacitors. Do not directly connect FB to the inductor’s output node. 4. Route SW away from sensitive analog areas, such as FB1 through FB4. Note: 18) The recommended layout is based on Figure 17 on page 40.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 39 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. C14R1 Buck1 Buck3 Buck2 Buck4 VIN1 VIN2 VIN3 VIN4 VIN5 SW3 SW1 SW2 SW4 PGND PGND PGND PGND AGND Top layer Inner layer1 Bottom layer 3VIN1 4SW1 5GND1 6SW3 VIN2 SW2 GND2 SW4 VIN4 26 25 AVIN AGND OUT RTC OUT2/ EN1 SCL SDA OUT4 VIN5 2PWRON 2324 FB2 7 16 10 11 1312 Figure 16: Recommended PCB Layout (19) Note: 19) It is recommended to separate the buck 1 and buck 3’s PGND from buck 2 and buck 4’s PGND on the top layer.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 41 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. APPENDIX MTP E-FUSE SELECTED TABLE BY MPQ7920GRM-0000 (21) OTP Items Buck 1 Buck 2 Buck 3 Buck 4 LDOR TC LDO2 LDO3 LDO4 LDO5 Initial on/off On On On On On On On On On MODE FPWM FPWM FPWM FPWM N/A Power-on delay 1.5ms 1ms 1.5ms 0.5ms Always on 0ms 2ms 5ms 5.5ms Power-off delay 4ms 4.5ms 4ms 5ms 5.5ms 3.5ms 0.5ms 0ms Soft-start time 300μs 300μs 300μs 300μs N/A Time slot 0.5ms PWR_ON_TIME_ SLOT_MODE Time slot is a fixed number set by TIME_SLOT PWR_OFF_TIME_ SLOT_MODE Time slot is a fixed number set by TIME_SLOT Switching frequency 2.2MHz PWRON mode 0 (level trigger) PWRON_ DEBOUNCE_ TIMER 10ms RSTO mode Not monitor any power rails RSTO delay 50ms Buck 1 peak current limit 7.6A Buck 2 peak current limit 3.9A Buck 3 peak current limit 7.6A Buck 4 peak current limit 3.9A I2C slave address 0x69 MTP configuration code 0000 Note: 22) MPQ7920GRM-0000-AEC1 is the standard sample version, which can access the MTP 2 times.

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 42 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-26 (3.5mmx4.5mm)

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 43 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package 0003-AEC1–Z QFN-25 (3.5mmx4.5mm) 5000 N/A 13in 12mm 8mm Pin1 1 1 1 1 ABCD ABCD ABCD ABCD Feed Direction

MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ7920 Rev. 1.0 www.MonolithicPower.com 44 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

Revision History

Revision # Revision Date Description Pages Updated 1.0 7/13/2020 Initial Release -