MPQ6541GQKTE-AEC1 | DigiCamel IC Datasheet

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MPQ6541GQKTE-AEC1 MPS | Alldatasheet

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Technical content

MPQ6541-AEC1, MPQ6541A-AEC1 40V, 8A, Three-Phase Power Stage, AEC-Q100 Qualified MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 1 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

DESCRIPTION

The MPQ6541-AEC1 and MPQ6541A-AEC1 are three-phase brushless DC (BLDC) motor drivers with three integrated half-bridges. The three half-bridges consist of six N-channel power MOSFETs . The MPQ6541 -AEC1 and MPQ6541A-AEC1 also integrate six pre-drivers, two gate drive r power supplies, and three current-sense amplifiers. The MP Q6541-AEC1 has ENBL and PWM inputs for each half-bridge; the MPQ6541A- AEC1 has separate high-side (HS) and low-side (LS) inputs. Otherwise, these parts are identical. References to the MP Q6541-AEC1 also apply to the MPQ6541A-AEC1, unless otherwise noted. The MPQ6541-AEC1 can deliver up to 12A of peak current for 1 second, or 8A of continuous current, depending on thermal and PCB conditions. The device uses an internal charge pump to generate the gate driver supply voltage for the high -side MOSFETs (HS-FETs), and a trickle charge circuit that maintains sufficient gate drive r voltage to operate at 100% duty cycle. Internal safety features include thermal shutdown, under -voltage lo ckout (UVLO), and over-current protection (OCP). The MPQ6541-AEC1 is available in a TQFN-26 (6mmx6mm) package.

FEATURES

4.75V to 40V Operating Supply Voltage
Three Integrated Half-Bridge Drivers
8A of Continuous Output Current
MOSFET On Resistance: 15mΩ per FET
MPQ6541-AEC1: PWM and ENBL Inputs MPQ6541A-AEC1: HS and LS Inputs
Internal Charge Pump Supports 100% Duty Cycle Operation
Automatic Synchronous Rectification
Under-Voltage Lockout (UVLO) and Over- Voltage Protection (OVP)
Thermal Shutdown Protection
Over-Current Protection (OCP)
Integrated, Bidirectional Current-Sense Amplifiers
Available in a TQFN-26 (6mmx6mm) Package with Wettable Flank
Available in AEC-Q100 Grade 1

APPLICATIONS

Brushless DC (BLDC) Motor Drivers
Permanent Magnet Synchronous Motor (PMSM) Drivers All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries.

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 2 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL APPLICATION CP1 CP2 VCP VIN LSS nFAULT VIN MPQ6541-AEC1 MPQ6541A-AEC1 SC SA SB nSLEEP GND ENA/LSA ENB/LSB ENC/LSC PWMA/HSA PWMB/HSB PWMC/HSC SOA SOB SOC VREF Microcontroller (MCU) VG

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 3 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number Package Top Marking MSL Rating MPQ6541GQKTE-AEC1* TQFN-26 (6mmx6mm) See Below 1 MPQ6541AGQKTE-AEC1** TQFN-26 (6mmx6mm) See Below * For Tape & Reel, add suffix -Z (e.g. MPQ6541GQKTE-AEC1-Z). ** For Tape & Reel, add suffix -Z (e.g. MPQ6541AGQKTE-AEC1-Z). TOP MARKING (MPQ6541GQKTE-AEC1) MPS: MPS prefix YY: Year code WW: Week code MP6541-AEC1: Part number LLLLLLLLL: Lot number E: Wettable lead flank TOP MARKING (MPQ6541AGQKTE-AEC1) MPS: MPS prefix YY: Year code WW: Week code MP6541A-AEC1: Part number LLLLLLLLL: Lot number E: Wettable lead flank

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 4 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW 22 21 nFAULT nSLEEP ENA ENB ENC PWMA PWMB PWMC CP2 CP1 VCP GND SOC SOB SOA VG SA VIN SB VIN SC SA LSS SB LSS SC TOP VIEW 22 21 nFAULT nSLEEP LSA LSB LSC HSA HSB HSC CP2 CP1 VCP GND SOC SOB SOA VG SA VIN SB VIN SC SA LSS SB LSS SC MPQ6541-AEC1, TQFN-26 (6mmx6mm) MPQ6541A-AEC1, TQFN-26 (6mmx6mm)

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 5 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. PIN FUNCTIONS Pin # MPQ6541-AEC1 Pin Name MPQ6541A-AEC1 Pin Name Description 1 nFAULT Fault indication. nFAULT has an o pen-drain output that pulls to logic low under fault conditions. 2 nSLEEP Sleep mode input. Pull nSLEEP to l ogic low to enter low - power sleep mode; pull nSLEEP to logic high for normal operation. nSLEEP has an internal pull-down resistor. 3 ENA - Enable pin for phase A. - LSA Enables the low-side MOSFET (LS-FET) for phase A. 4 ENB - Enable pin for phase B. - LSB Enables the LS-FET for phase B. 5 ENC - Enable pin for phase C. - LSC Enables the LS-FET for phase C. 6 PWMA - PWM input for phase A. - HSA Enables the high-side MOSFET (HS-FET) for phase A. 7 PWMB - PWM input for phase B. - HSB Enables the HS-FET for phase B. 8 PWMC - PWM input for phase C. HSC Enables the HS-FET for phase C. 9, 26 SA Phase A output. 10, 12 LSS Low-side source connection for phases A, B, and C. These pins must be connected directly to GND. 11, 24 SB Phase B output. 13, 22 SC Phase C output. 14 VG Low-side gate drive output. Connect a 4.7 μF, 10V ceramic capacitor with X7R dielectrics from VG to ground. 15 SOA Current-sense output for phase A. 16 SOB Current-sense output for phase B. 17 SOC Current-sense output for phase C. 18 GND Ground. 19 VCP Charge pump output. Connect a 1 μF, 16V ceramic capacitor with X7R dielectrics from VCP to VIN. 20 CP1 Charge pump capacitor pins. Connect a 100nF ceramic capacitor with X7R dielectrics rated for V IN (at minimum) from CP1 to CP2. 21 CP2 23, 25 VIN Input supply voltage.

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 6 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = 25°C) (2) ESD Ratings Recommended Operating Conditions (3) Operating junction temp (TJ) .... -40°C to +125°C Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature , TJ (MAX), the junction -to- ambient thermal resistance , θJA, and the ambient temperature, TA. Exceeding the maxim um allowable power dissipation can cause excessive die temperature, and the device may go into thermal shutdown. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 7 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 24V, LSS = GND = 0V, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Power Supply Input supply voltage VIN 4.75 40 V Quiescent current IQ nSLEEP = 1, ENx = 0 4 8 mA ISLEEP nSLEEP = 0 1 µA Control Logic Input logic ‘low’ threshold VIL 0.8 V Input logic ‘high’ threshold VIH 2 V Logic input current IIN(H) VIH = 5V -20 +20 µA IIN(L) VIL = 0V -20 +20 µA Power up delay tPUD At VIN rising or nSLEEP rising 1 ms Internal pull-down resistance RPD All logic inputs 500 kΩ nFAULT pull-down RON RON(NFAULT) 10 Ω Protection Circuits UVLO threshold VUVLO VIN rising 4 4.4 4.8 V UVLO hysteresis ∆VUVLO 470 mV OVP threshold VOVP VIN rising 44.5 48 51.5 V OVP hysteresis ∆VOVP 1.3 V HS OCP threshold IOCP(HS) 10 19 A LS OCP threshold IOCP(LS) 17.5 25 A OCP deglitch time (5) tOCD 0.4 µs OCP retry time tOCR 2 ms Thermal shutdown (5) TTSD 150 °C Thermal shutdown hysteresis (5) ∆TTSD 25 °C Current-Sense Current-sense ratio A phase 1/13000 1/11600 1/10000 A/A B phase 1/13000 1/11500 1/9750 C phase 1/12500 1/11000 1/9500 Current-sense output offset current ISOx A phase current = 0A -35 -5 +25 µA B phase current = 0A -26 -3 +21 C phase current = 0A -33 -5 +26 µA Current-sense output voltage swing (5) 0 5 V Current-sense minimum load impedance (5) Pull-up 1.8 kΩ Pull-down 1 Outputs HS-FET on resistance RON(HS) IOUT = 1A, TJ = 25°C 15 18 mΩ LS-FET on resistance RON(LS) IOUT = 1A, TJ = 25°C 15 18 Output rising time (5) IOUT = 1A 0.45 V/ns Output falling time (5) IOUT = 1A 0.85 V/ns Charge pump output voltage VCP VIN + 5 V VCP switching frequency fCP 2000 kHz Note: 5) Not tested in production.

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 8 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS 4.36 4.38 4.4 4.42 4.44 4.46 -50 -20 10 40 70 100 130 UVLO RISING THRESHOLD (V) TEMPERATURE (°C) UVLO Rising Threshold vs. Temperature 47.7 47.75 47.8 47.85 47.9 47.95 48.05 48.1 -50 -20 10 40 70 100 130 OVP RISING THRESHOLD (V) TEMPERATURE ( C) OVP Rising Threshold vs. Temperature 11400 11450 11500 11550 11600 11650 11700 -50 -20 10 40 70 100 130 A PHASE CURRENT-SENSE RATIO TEMPERATURE ( C) A Phase Current-Sense Ratio vs. Temperature VIN = 24V, IOUT = 1A 11100 11150 11200 11250 11300 11350 11400 -50 -20 10 40 70 100 130 B PHASE CURRENT-SENSE RATIO TEMPERATURE ( C) B Phase Current-Sense Ratio vs. Temperature VIN = 24V, IOUT = 1A 10600 10650 10700 10750 10800 10850 10900 -50 -20 10 40 70 100 130 C PHASE CURRENT-SENSE RATIO TEMPERATURE ( C) C Phase Current-Sense Ratio vs. Temperature VIN = 24V, IOUT = 1A -50 -20 10 40 70 100 130 HS ON RESISTANCE (mΩ) TEMPERATURE ( C) HS On Resistance vs. Temperature VIN = 24V, IOUT = 1A

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 9 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) -50 -20 10 40 70 100 130 LS ON RESISTANCE (mΩ) TEMPERATURE ( C) LS On Resistance vs. Temperature VIN = 24V, IOUT = 1A 0 100 200 300 OPERATION CURRENT (mA) INPUT PWM FREQUENCY (kHz) Operation Current vs. Input PWM Frequency VIN=12V VIN=24V

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 10 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 24V, A phase switc hing with a 20kHz frequency, B phase LS on, C phase disable d, VREF = 5V, current -sense resistor divider = 5k Ω, T A = 25 °C, resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted. Steady State Duty cycle = 10% Steady State Duty cycle = 50% CH1: VPWM 5V/div. CH2: VSA 10V/div. CH4: IOUTA 200mA/div. CH3: VSOB 1V/div. CH1: VPWM 5V/div. CH2: VSA 10V/div. CH4: IOUTA 500mA/div. CH3: VSOB 1V/div. 20μs/div. 20μs/div. Steady State Duty cycle = 90% Start-Up Duty cycle = 10% CH1: VPWM 5V/div. CH2: VSA 10V/div. CH4: IOUTA 1A/div. CH3: VSOB 1V/div. CH1: VIN 10V/div. CH2: VSA 10V/div. CH4: IOUTA 200mA/div. CH3: VSOB 1V/div. 20μs/div. 400μs/div. Start-Up Duty cycle = 50% Start-Up Duty cycle = 90% CH1: VIN 10V/div. CH2: VSA 10V/div. CH4: IOUTA 500mA/div. CH3: VSOB 1V/div. CH1: VIN 10V/div. CH2: VSA 10V/div. CH4: IOUTA 1A/div. CH3: VSOB 1V/div. 400μs/div. 400μs/div.

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 11 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 24V, A phase switching with a 20kHz frequency, B phase LS on, C phase disabled, VREF = 5V, current -sense resistor divider = 5k Ω, T A = 25°C, resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted. Shutdown Duty cycle = 10% Shutdown Duty cycle = 50% CH1: VIN 10V/div. CH2: VSA 10V/div. CH4: IOUTA 200mA/div. CH3: VSOB 1V/div. CH1: VIN 10V/div. CH2: VSA 10V/div. CH4: IOUTA 500mA/div. CH3: VSOB 1V/div. 10ms/div. 10ms/div. Shutdown Duty cycle = 90% Sleep Recovery Duty cycle = 10% CH1: VIN 10V/div. CH2: VSA 10V/div. CH4: IOUTA 1A/div. CH3: VSOB 1V/div. CH1: VnSLEEP 2V/div. CH2: VSA 10V/div. CH4: IOUTA 200mA/div. CH3: VSOB 1V/div. 10ms/div. 400μs/div. Sleep Recovery Duty cycle = 50% Sleep Recovery Duty cycle = 90% CH1: VnSLEEP 2V/div. CH2: VSA 10V/div. CH4: IOUTA 500mA/div. CH3: VSOB 1V/div. CH1: VnSLEEP 2V/div. CH2: VSA 10V/div. CH4: IOUTA 1A/div. CH3: VSOB 1V/div. 400μs/div. 400μs/div.

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 12 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 24V, A phase switching with a 20kHz frequency, B phase LS on, C phase disabled, VREF = 5V, current -sense resistor divider = 5k Ω, T A = 25°C, resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted. Sleep Entry Duty cycle = 10% Sleep Entry Duty cycle = 50% CH1: VnSLEEP 2V/div. CH2: VSA 10V/div. CH4: IOUTA 200mA/div. CH3: VSOB 1V/div. CH1: VnSLEEP 5V/div. CH2: VSA 10V/div. CH4: IOUTA 500mA/div. CH3: VSOB 1V/div. 100μs/div. 100μs/div. Sleep Entry Duty cycle = 90% CH1: VnSLEEP 5V/div. CH2: VSA 10V/div. CH4: IOUTA 1A/div. CH3: VSOB 1V/div. 100μs/div.

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 13 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM Charge Pump CP1 VIN VIN CP2 VCP SA SB SC LSS G SOA SOB SOC Timing and Control Logic PWMC/HSC PWMB/HSB PWMA/HSA ENC/LSC ENB/LSB ENA/LSA HS Gate Driver LDO VG nSLEEP VREF (MCU) LS Gate Driver VG G G VCP VCP VG Current Measurement (to ADC) RTERM UVLO ComparatorFault HandlingnFAULT OCP Comparator GND VIN TSD 4.4V OC_REF OVP Comparator VIN 48V Figure 1: Functional Block Diagram

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 17 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUIT CP1 CP2 VCP VIN LSS nFAULT VIN MPQ6541-AEC1 MPQ6541A- AEC1 SC SA SB nSLEEP GND ENA/LSA ENB/LSB ENC/LSC PWMA/HSA PWMB/HSB PWMC/HSC SOA SOB SOC VREF Microcontroller (MCU) VG Figure 6: Typical Application Circuit

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 18 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

PACKAGE INFORMATION

TQFN-26 (6mmx6mm) Wettable Flank PACKAGE OUTLINE DRAWING FOR 26L FCTQFN (6X6MM)-2 MF-PO-D-0521 revision 0.0 SIDE VIEW BOTTOM VIEW NOTE: 1) THE LEAD SIDE IS WETTABLE . 2) ALL DIMENSIONS ARE IN MILLIMETERS . 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX . 4) JEDEC REFERENCE IS MO -220. 5) DRAWING IS NOT TO SCALE . PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID SECTION A -A

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 19 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. CARRIER INFORMATION Pin1 1 1 1 1 ABCD ABCD ABCD ABCD Feed Direction Part Number Package MPQ6541GQKTE-AEC1-Z TQFN-26 (6mmx6mm) 5000 N/A 13in 12mm 8mm MPQ6541AGQKTE-AEC1-Z

MPQ6541-AEC1, MPQ6541A-AEC1 – 40V, 8A, 3-PHASE POWER STAGE, AEC-Q100 Notice: The information in t his document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ6541-AEC1, MPQ6541A-AEC1 Rev. 1.11 MonolithicPower.com 20 5/23/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 10/18/2021 Initial Release - 1.1 2/24/2023 Added “-AEC1” suffix to part number All 1.11 5/23/2023 Updated the Typical Application image 2

Product Information

MPQ6541GQKTE-AEC1 specifications and overview.

Summary

40V, 8A, Three-Phase Power Stage, AEC-Q100 Qualified Rev. 1.11

Description

40V, 8A, Three-Phase Power Stage, AEC-Q100 Qualified Rev. 1.11

Source title MPQ6541GQKTE-AEC1 Datasheet(PDF) - Monolithic Power Systems

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