MPQ6523

MPQ6523 MPS | Alldatasheet

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Technical content

Triple Half-Bridge Motor Driver with Serial Input Control AEC-Q100 Qualified MPQ6523 Rev.1.01 www.MonolithicPower.com 1 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

DESCRIPTION

The MPQ6523 is a triple, half-bridge, DMOS, output driver with integrated power MOSFETs that can drive up to three different loads. The three half -bridges can be controlled separately from a standard serial data interface and have various diagnostic functions. The MPQ6523 has very low quiescent current in standby mode , making it suitable for a wide range of applications. Full protection features include short-circuit protection (SCP), under -voltage protection (UVP), and thermal shutdown. The MPQ6523 requires a minim al number of readily available , standard, external components and is available in a QFN-24 (4mmx4mm) package.

FEATURES

 Up to 0.9A Output Current  RDS(ON) (HS + LS) Typically 1.1Ω at 25°C, Maximum 2Ω at 150°C  Very Low Quiescent Current IVS < 6μA in Standby Mode Versus Total Temperature Range  Outputs Short-Circuit Protected  Over-Temperature Protection and Pre- Warning  Under-Voltage Protection (UVP)  Serial Data Interface  Various Diagnostic Functions: Shorted Output, Open-Load, Over-Temperature, and Under-Voltage  Fault Output Flag  Daisy Chaining Possible  Serial Interface Clock Frequency up to 3MHz, 5V Compatible  Available in a QFN-24 ( 4mmx4mm) Package  Available in AEC-Q100 Grade 1

APPLICATIONS

 Drive Various Loads in Automotive and Industrial Applications  DC Motors All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MPQ6523 MCU EN DO CLK DI CS FAULT VCC VCC 5V AGND OUT1 OUT2 OUT3 PGND M M VS VS Vbatt

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 2 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MPQ6523GR-AEC1 QFN-24 (4mmx4mm) See Below *For Tape & Reel, add suffix –Z (e.g. MPQ6523GR-AEC1–Z) TOP MARKING MPS: MPS prefix Y: Year code WW: Week code MP6523: Product code of MPQ6523GR-AEC1 LLLLLL: Lot number PACKAGE REFERENCE TOP VIEW QFN-24 (4mmx4mm)

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 3 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25° C) (2) ESD Susceptibility (3) Recommended Operating Conditions (4) Operating junction temp. (TJ) ... -40° C to +150°C Thermal Resistance (5) θJA θJC NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Devices are ESD -sensitive. Handling precaution is recommended. 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on JESD51-7, 4-layer PCB.

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 4 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

7V < VVS < 28V, VVCC = 5V, TJ = -40° C to +125° C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Operating supply current (VS) IVS VVS < 28V normal operation, all output stages off 2.2 6 mA VVS < 28V normal operation, all output low stages on, no load 2.65 6 VVS < 28V normal operation, all output high stages on, no load 2.7 6 Operating supply current (VCC) IVCC 4.75V < VVCC < 5.25V, normal operation 65 90 μA Quiescent current (VS) IVS VVS = 28V, VVCC = 0V or VVCC = 5V, EN = low, or VVCC = 5V, bit SE = low, output pins to VS and GND 1.5 6 μA Quiescent current (VCC) IVCC 4.75V < VVCC < 5.25V, EN or bit SE = low 23 35 μA Discharge current (VS) IVS VVS = 40V, EN = low 3 mA Internal oscillator frequency fOSC 85 120 166 kHz Power-on reset threshold VVCC 2.3 2.6 3.0 V Power-on reset delay After switching on VVCC 30 100 190 μs Under-voltage lockout threshold rising 5.5 6.5 V Under-voltage lockout threshold hysteresis 0.6 V Under-voltage lockout delay time 7 14 23 ms Output Specification HS + LS switch-on resistance RDS(ON) TJ = -40° C to +125°C 1.1 1.7 Ω Inductive shutdown energy (7) 15 mJ Over-current limit IOCP 1 1.3 1.8 A Open-load detection current Bit13 (OLD) = low, output off 1.4 1.9 2.4 mA Output switch-on/-off delay VVS = 13V, RLOAD = 50Ω 60 μs OUTx rising time VVS = 13V, 10% to 90% VOUT, RLOAD = 50Ω 2 20 50 μs OUTx falling time VVS = 13V, 10% to 90% VOUT, RLOAD = 50Ω 2 20 45 μs Dead time VVS = 13V, RLOAD = 50Ω 2 μs

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 5 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) 7V < VVS < 28V, VVCC = 5V, TJ = 25° C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units EN Input EN low-level threshold 0.8 V EN high-level threshold 3 1.7 V EN threshold hysteresis V Pull-down current of EN input VEN = VVCC 10 80 μA Thermal Shutdown and Pre-Warning (7) Thermal pre-warning threshold 120 145 170 °C Thermal pre-warning hysteresis 15 °C Thermal shutdown threshold 150 175 200 °C Thermal shutdown hysteresis 15 °C Ratio thermal shutdown/thermal pre-warning 1.05 1.2

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 6 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. SERIAL INTERFACE TIMING ELECTRICAL CHARACTERISTICS (7) 7V < VVS < 28V, VVCC = 5V, TJ = -40° C to +125° C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Logic Inputs (DI, CLK, CS) Input low-level threshold 0.3 x VVCC V Input high-level threshold 0.7 x VVCC V Pull-down current of DI, CLK VDI, VCLK = VVCC 2 50 μA Pull-up current of CS VCS = 0V 2 50 μA Logic Output (DO) Output low level 0.5 V Output high level VVCC - 0.7V V Leakage current (tri-state) 0V < VDO < VVCC, VCS = VVCC -10 10 μA Timing Characteristics DO enable after CS falling edge T1 CDO = 100pF 200 ns DO disable after CS rising edge T2 CDO = 100pF 200 ns DO falling/rising time CDO = 100pF 100 ns DO valid time T10 CDO = 100pF 200 ns CS set-up time (high to low) T4 150 ns CS set-up time (low to high) T8 150 ns CS high time T9 Bit14 (SCT) = high 0.75 ms Bit14 (SCT) = low 0.3 ms CLK high time T5 150 ns CLK low time T6 150 ns CLK period time 333 ns CLK set-up time (high to low) T7 150 ns CLK set-up time (low to high) T3 150 ns DI set-up time T11 26 ns DI hold time T12 26 ns NOTES: 6) Guaranteed by characterization, not tested in production. 7) Not subject to production test, specified by design.

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 7 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. SERIAL INTERFACE TIMING DIAGRAMS 1 2 CS CS CLK DO CLK DI DO Inputs DI, CLK, CS: High Level = 0.7 x Vcc, Low Level = 0.3 x Vcc Output DO: High Level = 0.8 x Vcc, Low Level = 0.2 x Vcc

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 8 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VVS = 13V, VVCC = 5V, TA = 25° C, unless otherwise noted.

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 9 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VVS = 13V, VVCC = 5V, TA = 25° C, unless otherwise noted.

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 10 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 OUT2 Half-bridge output 2. 2, 3, 4, 5 VS Power supply. 6, 11, 23 NC No connection. 7, 9, 10, 21, 22, 24 PGND Power ground. 8 OUT1 Half-bridge output 1. 12 EN Enable. Drive EN low for standby mode . Drive EN high for normal operation. 13 DO Serial data output. 14 VCC Logic supply voltage. 15 FAULT Fault output. A low output at FAULT indicates that the IC has detected an over-temperature or over-current condition. This output is open-drain. 16 AGND Analog ground. 17 CS Chip select input. 18 CLK Serial clock input. 19 DI Serial data input. 20 OUT3 Half-bridge output 3.

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 11 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. BLOCK DIAGRAM Charge Pump VS OUT1 OUT2 OUT3 PGND LS Gate Driver HS Gate Driver GH1 GH2 GH3 GL1 GL2 GL3 GH1 GH2 GH3 GL1 GL2 GL3 EN DO CLK DI CS VCC Power on reset Control Logic Serial interface Input register Output register SRR n. u. n. u. LS1 HS1 n. u. n. u. LS2 HS2 n. u. n. u. LS3 HS3 OLD SCT SE TP n. u. n. u. SLS1 SHS1 n. u. n. u. SLS2 SHS2 n. u. n. u. SLS3 SHS3 SCD EN PSF UVLO Comparator Fault Handling VS TSD UVLO_REF FAULT AGND Over load and short circuit protection Figure 1: Functional Block Diagram

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 12 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. OPERATION The MPQ6523 is a three, half-bridge, motor driver that can drive up to three different loads with separate control s for high-side or low -side MOSFETs from a standard serial data interface. Serial Interface Data transfer starts with the falling edge of the CS signal (see Figure 2) . Execu tion of new input data is enabled on the rising edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) must be transferred first. The output data at DO is enabled on the falling edge of CS. The output data changes state with the rising edge of CLK and remains stable until the next rising edge of CLK appears. When CS is high, DO is in a tri -state condition. LSB (bit0, TP) is transferred first. CS DI CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 2: Data Transfer Table 1: Input Data Protocol Bit Input Register Function

0 SRR Status register reset (high = reset; the bits PSF, SCD and over-temperature

shutdown in the output data register are set to low). 1 n. u. Not used. 2 n. u. Not used. 3 LS1 Controls output LS1 (high = switch output LS1 on). 4 HS1 Controls output HS1 (high = switch output HS1 on). 5 n. u. Not used. 6 n. u. Not used. 7 LS2 Controls output LS2 (high = switch output LS2 on). 8 HS2 Controls output HS2 (high = switch output HS2 on). 9 n. u. Not used. 10 n. u. Not used. 11 LS3 Controls output LS3 (high = switch output LS3 on). 12 HS3 Controls output HS3 (high = switch output HS3 on). 13 OLD Open-load detection (low = on).

14 SCT Programmable time delay for short circuit (shutdown delay high/low =

12ms/1.5ms). 15 SE Software enable. Low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered).

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 13 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Table 2: Output Data Protocol Bit Input Register Function

0 TP Temperature pre -warning: high = warning (over-temperature shutdown see

remark below). 1 n. u. Not used. 2 n. u. Not used.

3 Status LS1

Normal operation: high = output is on, low = output is off . Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off).

4 Status HS1

Normal operation: high = output is on, low = output is off . Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off). 5 n. u. Not used. 6 n. u. Not used. 7 Status LS2 See LS1. 8 Status HS2 See HS1. 9 n. u. Not used. 10 n. u. Not used. 11 Status LS3 See LS1. 12 Status HS3 See HS1. 13 SCD Short circuit detected. Set SCD high when at least one output is switched off by a short-circuit condition. 14 EN Enable. EN is controlled by software (bit S E in input register) and hardware Enable (EN). Low = standby, high = normal operation. 15 PSF Power supply fail. Under-voltage at VS detected. NOTE: Bit0 to 15 = high: over-temperature shutdown. Table 3: Status of the Input Register after Power-On Reset Bit15 (SE) Bit14 (SCT) Bit13 (OLD) Bit12 (HS3) Bit11 (LS3) Bit10 Bit9 Bit8 (HS2) Bit7 (LS2) Bit6 Bit5 Bit4 (HS1) Bit3 (LS1) Bit2 Bit1 Bit0 (SRR) H H H L L x x L L x x L L x x L

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 14 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Enable Control (EN) There are two ways to enable or disable the MPQ6523:  Controlled by software: set bit SE in the input register. Low = standby, high = normal operation.  Hardware enable (EN): low = standby, high = normal operation. In both cases, if the device is disabled, then all output stages are turned off , but the serial interface remains active. The output stages can be activated again by setting the bit SE high (when EN = high) or by switching EN back to high (when SE = high). Open-Load Detection When the open -load detection bit (OLD) is set to low, open -load detection is enabled. In this mode, a pull -down current for each low-side switch is turned on. When an open load has been detected, the corresponding output bit (LSx or HSx) in the output data register is set to high. Once the open -load is removed, the corresponding DO bit is cleared, indicating the end of the open-load event. Testing the open load of H-bridge configuration is a two -step process. First, switch off all high - side (HSx/HSy) and low -side (LSx/LSy) drivers. The voltage at both clamps in this condition is pulled down. Next, with both low-side drivers off, switch on one high -side driver (HSx or HSy). Since the DC motor has a relatively low internal resistance, the voltage of the inactive high -side output should be at the same level as the activated high -side output . In the case of an open-load, the inactive high-side output register reports a 0 if the active high -side output is 1. Conversely, if the load is connected, the inactive high-side output reports a 1. Discharge Circuit Many typical applications use an inverse - polarity protection diode (see D1 in Figure 3). However, this method involves a certain danger. During inhibit mode, the IC consumes only an extremely low current (IVS), such as 20μA maximum. Any peaks on the supply voltage charge the blocking capacitor gradually. D1 prevents the capacitor from discharging via the power supply . Due to the extremely small quiescent current, discharging via the IC can also be neglected. This means that during long periods in inhibit mode, the IC's supply voltage could increase continuously until the maximum supply voltage limit of 40V is exceeded, damaging the IC. The device features a discharger circuit that prevents such u nwanted effects. If VS exceeds a threshold value of approximately 37V, the blocking capacitor is discharged via an integrated resistor until VS falls below the threshold again. MPQ6523 VbattC1 Vpk Figure 3: Functional Principle of the Discharger Circuit Over-Current Protection (OCP) The MPQ6523 has internal overload and short - circuit protection. The currents in both the high - side and low-side MOSFETs are measured and if the current exceeds the current limit, an internal timer is started. When a permanent over-current shutdown delay time programmed by the short -circuit timer bit (SCT) is reached, the short-circuit detection bit (SCD) is set , and the shorted output is disabled. By writing a high to the SRR bit in the input register, the SCD bit is reset, and the disabled outputs are enabled.

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL MPQ6523 Rev.1.01 www.MonolithicPower.com 15 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Thermal Shutdown and Pre-Warning Thermal monitoring is also integrated into the MPQ6523. If the junction temperature rises above the thermal pre -warning threshold , the temperature pre -warning bit (TP) in the output register is set. When the temperature falls below the thermal pre-warning threshold, the bit TP is reset. The bit TP can be r ead without transferring a complete 16 -bit data word. When CS = high to low, the state of TP appears at DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature rises above the thermal shutdown threshold, all switches turn off, and all bits in the output register are set high. Operation resumes immediately when the junction temperature has fallen below th e thermal shutdown threshold and when a high has been written to the SRR bit in the input register. The thermal pre-warning and shutdown threshold have hysteresis. Note that bit0 to 15 = high indicates an over- temperature shutdown. Power-Supply Fail If at any time the voltage on VS falls below the under-voltage lockout (UVLO) threshold voltage, an internal timer is started. T he power supply fail bit (PSF) in the output register is set , and all outputs are disabled when a permanent UVLO delay time is reached. Operation resumes immediately when V S rises above the UVLO threshold. The PSF bit remains high until it is reset by the SRR bit in the input register. Fault Output The MPQ6523 includes an open -drain, active - low fault indicator output (FAULT). A fault is indicated if the current limit is tripped or thermal shutdown is tripped. A fault on any channel causes FAULT to be pulled low. The FAULT value is maintained until the fault condition is removed and normal operation resumes. Do not apply more than 6V to FAULT.

MPQ6523 – TRIPLE HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ6523 Rev.1.01 www.MonolithicPower.com 16 9/5/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-24 (4mmx4mm) SIDE VIEW TOP VIEW 2419 12 7 BOTTOM VIEW 3.90 4.10 2.50 2.80 3.90 4.10 2.50 2.80 0.50 BSC 0.18 0.30 0.80 1.00 0.00 0.05

0.20 REF

2.70 0.25 RECOMMENDED LAND PATTERN

3.90 NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) DRAWING CONFIRMS TO JEDEC MO-220, VARIATION VGGD. 5) DRAWING IS NOT TO SCALE. PIN 1 ID SEE DETAIL A PIN 1 ID OPTION A 0.30x45º TYP. PIN 1 ID OPTION B R0.25 TYP. DETAIL A PIN 1 ID INDEX AREA 0.70 0.35 0.45 0.50