MPQ5850

MPQ5850 MPS | Alldatasheet

Document overview

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Technical content

36V, Smart Diode Controller with Reverse Protection, AEC-Q100 Qualified MPQ5850 Rev. 1.1 MonolithicPower.com 1 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

DESCRIPTION

The MP Q5850 is a smart diode controller that can drive an external N -channel MOSFET to replace a Schottk y diode for reverse input protection. The device’s 20mV ultra-low dropout minimizes power loss and enables a low minimum input voltage, which makes the MPQ5850 well -suited for cold-crank conditions in automotive applications . The 4μA shutdown current also makes the device ideal for battery- powered applications. The ultra -fast transient response meets stringent ISO16750 requirements. The MPQ5850 integrates an internal boost to provide a boost voltage that turns on the external N-channel MOSFET, even at a low input voltage (VIN). An open-drain, power good signal indicates when the external N-channel MOSFET is fully on. The MPQ5850 is available in a TSOT23-8 (2mmx3mm) package.

FEATURES

Built to Handle Tough Automotive Transients: o -36V Blocking Voltage o Load Dump Up to 42V o Cold Crank Down to 0V o Rectifies AC Frequency Up to 100kHz o Strong Gate Drive Ability: 170mA Pull- Up and 430mA Pull-Down
Extended Vehicle Battery Life: o Low Quiescent Current in Standby Mode (4μA) o Low Quiescent Current in Steady State (30μA)
Reduced Board Size: o Available in a TSOT23-8 (2mmx3mm) Package
Additional Features: o 20mV Ultra-Low Dropout o Integrates a Boost Converter o Power Good (PG) Indication for RES Out of Regulation, Fast Pull-Up, and Part Disabling o Available in AEC-Q100 Grade 1

APPLICATIONS

Automotive System Protection
Automotive ADAS Systems (Cameras)
Automotive Infotainment Systems, Including Digital Clusters and Head Units
Battery-Powered Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries.

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 2 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL APPLICATION GATE SOURCE DRAIN RES SW EN/UVLO PG GND MPQ5850 VIN Enable Power Good OFF ON VOUT CH2: VOUT CH3: VIN CH1: VGATE CH4: IOUT Negative Pulse IOUT = 5A

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 3 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL Rating** MPQ5850GJ TSOT23-8 (2mmx3mm) See Below Level 1 MPQ5850GJ-AEC1 * For Tape & Reel, add suffix -Z (e.g. MPQ5850GJ-Z). ** Moisture Sensitivity Level Rating TOP MARKING (MPQ5850GJ & MPQ5850GJ-AEC1) BNN: Product code of MPQ5850GJ and MPQ5850GJ-AEC1 Y: Year code PACKAGE REFERENCE TOP VIEW 4 5 8EN/UVLO PG GND SW RES DRAIN GATE SOURCE TSOT23-8 (2mmx3mm)

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 4 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description

1 EN/UVLO

Enable pin. Pull EN below the specified threshold (1V) to shut down the chip. Pull EN above the threshold (1.2V) to enable the chip. A resistor divider connected between EN/UVLO and SOURCE can be used to raise the under-voltage lockout (UVLO) threshold. Do not float the EN/UVLO pin, and connect it to DRAIN if the shutdown feature not used. 2 PG Open-drain power good pin. The PG pin asserts low if the device is disabled, the reservoir supply is out of regulation, or if the fast pull-up path is active for longer than 17μs. Float PG or connect it to GND if it is not used. 3 GND Ground connection of the device. Connect GND to the ground plane of the board. 4 SW Switch node of internal boost regulator. Connect an inductor between the SW and DRAIN pins. 5 RES Reservoir supply. RES is the power supply for the external N -channel MOSFET gate driver. Connect a minimum 1μF ceramic capacitor between the RES and DRAIN pins.

6 DRAIN

Drain connection. Connect the DRAIN pin to the drain of the external power MOSFET. DRAIN is the power supply of th e internal circuitry, and also controls the MOSFET’s gate voltage. Connect a minimum 4.7μF capacitor from DRAIN to ground, and place this capacitor as close as possible to the device. 7 GATE Gate connection. Connect the GATE pin to the gate of the external power MOSFET.

8 SOURCE

Source connection. Connect the SOURCE pin to the source of the external power MOSFET. The voltage sensed on this pin works with the DRAIN voltage to control the MOSFET gate. ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = 25°C) (2) Electrostatic Discharge (ESD) Ratings Recommended Operating Conditions Operating junction temp (TJ) .... -40°C to +150°C Thermal Resistance θJA θJC TSOT23-8 (2mmx3mm) Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature , TJ (MAX), the junction -to- ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - TA)/ θJA. Exceeding the maximum allowable power dissipation can produce an excessive die temperature, and the device may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permane nt damage. 3) Per AEC-Q100-002. 4) Per AEC-Q100-011. 5) Measured on JESD51-7, 4-layer PCB. The values given in this table are only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51-7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 5 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VSOURCE = VEN/UVLO = 12V, VRES = 22V, TJ = -40°C to +150°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Input Voltage Drain voltage at start-up VDRAIN_UVLO 2.8 3.2 V Drain voltage UVLO falling VDRAIN_UVLO_F 2.4 2.6 2.8 V Reservoir UVLO rising VRES_UVLO 8 11 13 V Reservoir UVLO hysteresis VRES_UVLO_HYS 0.2 V Quiescent current ISHDN VEN = 0V, TJ = 25°C 4 10 μA VEN = 0V, TJ = -40°C to +150°C 20 μA IQ VEN = 2V, in regulation, system input current, TJ = 25°C 30 50 μA VEN = 2V, in regulation, system input current, TJ = -40°C to +125°C (6) 100 μA VEN = 2V, in regulation, system input current, TJ = 125°C to 150°C 200 μA Rectifier Source to drain regulation voltage VSD 10 20 30 mV Source to drain fast pull- up threshold VSD_FPU 50 75 100 mV Source to drain fast pull- down threshold VSD_FPD -15 -4 0 mV Drain current ID Gate driver in regulation 50 μA Source current IS_R VSOURCE = -36V -1 mA Fast pull up current IFPU VGATE-RES = -7V 170 mA Fast pull down current IFPD VGATE-SOURCE = 5V 430 mA Reverse biased gate- source voltage VGS_RB VSOURCE = -5V, IGATE = 1mA 0.01 0.3 V VSOURCE = -36V, IGATE = 1mA 0.01 0.3 V Gate turn-on delay time tON Step (VSOURCE - VDRAIN) from -100mV to +3V, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF 1.2 2 μs Gate turn-off delay time tOFF Step (VSOURCE - VDRAIN) from 3V to -100mV, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF 1 2 μs Gate rising time tRISING (6) Step (VSOURCE - VDRAIN) from -100mV to +3V, VRES-DRAIN = 13V, CGATE-SOURCE = 10nF 300 ns Gate falling time tFALLING (6) Step (VSOURCE - VDRAIN) from 3V to -100mV, VRES-DRAIN = 13V, CGATE- SOURCE = 10nF 100 ns Maximum rectification frequency (6) fMAX VPP = 6V, CGATE-SOURCE = 15nF 50 kHz VPP = 2V, CGATE-SOURCE = 15nF 100

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 6 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VSOURCE = VEN/UVLO = 12V, VRES = 22V, TJ = -40°C to +150°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Boost Converter Reservoir regulation voltage VREG 10 12 14 V Reservoir regulation UVLO hysteresis VREG_UVLO_HYS VREG - VRES_UVLO - VRES_UVLO_HYS 1.2 V Boost current limit IBOOST 160 220 280 mA SW leakage ISW 1 μA Boost power switch on resistance RSW 1.5 3.5 Ω Boost rectifier diode voltage drop VDIODE IDIODE = 220mA 0.9 V Enable Pin Enable threshold rising VEN 1.0 1.2 1.4 V Enable threshold falling VEN_F 0.8 1 1.2 V Enable hysteresis VEN_H 200 mV Enable leakage IEN VEN = 3V 1 μA Power Good Flag PG output voltage low VPG_LOW ISINK = 1mA 0.1 0.3 V Thermal shutdown (6) TSD 175 °C Thermal shutdown hysteresis (6) TSD_HYS 25 °C Note: 6) Derived from bench characterization. Not tested in production.

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 7 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VIN = 12V, L = 68µH, TJ = -40°C to +150°C, unless otherwise noted. 100 -50 -25 0 25 50 75 100 125 150 IQ (µA) TEMPERATURE ( C) IQ vs. Temperature 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 -50 -25 0 25 50 75 100 125 150 ISHDN (µA) TEMPERATURE ( C) ISHDN vs. Temperature 2.55 2.60 2.65 2.70 2.75 2.80 2.85 -50 -25 0 25 50 75 100 125 150 DRAIN UVLO THRESHOLD (V) TEMPERATURE ( C) Drain UVLO Threshold vs. Temperature DRAIN UVLO Rising DRAIN UVLO Falling 10.4 10.6 10.8 11.0 11.2 -50 -25 0 25 50 75 100 125 150 RESERVIOR UVLO THRESHOLD (V) TEMPERATURE ( C) Reservoir UVLO Threshold vs. Temperature Reservoir UVLO Rising Reservoir UVLO Falling 19.8 20.0 20.2 20.4 20.6 20.8 -50 -25 0 25 50 75 100 125 150 VSD (mV) TEMPERATURE ( C) Source to Drain Regulation Voltage vs. Temperature 74.2 74.4 74.6 74.8 75.0 75.2 75.4 75.6 75.8 -50 -25 0 25 50 75 100 125 150 VSD_ FPU (mV) TEMPERATURE ( C) Source to Drain Fast Pull-Up Threshold vs. Temperature

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 8 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN = 12V, L = 68µH, TJ = -40°C to +150°C, unless otherwise noted. -4.02 -4.00 -3.98 -3.96 -3.94 -3.92 -3.90 -3.88 -3.86 -50 -25 0 25 50 75 100 125 150 VSD_FPD (mV) TEMPERATURE (°C) Source to Drain Fast Pull- Down Threshold vs. Temperature 217 218 219 220 221 222 223 -50 -25 0 25 50 75 100 125 150 IBOOST (mA) TEMPERATURE ( C) Boost Current Limit vs. Temperature 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 -50 -25 0 25 50 75 100 125 150 tON (µs) TEMPERATURE ( C) Gate Turn-On Delay Time vs. Temperature 0.94 0.96 0.98 1.00 1.02 1.04 -50 -25 0 25 50 75 100 125 150 tOFF (µs) TEMPERATURE ( C) Gate Turn-Off Delay Time vs. Temperature 11.80 11.85 11.90 11.95 12.00 12.05 12.10 12.15 -50 -25 0 25 50 75 100 125 150 VRES (V) TEMPERATURE ( C) Reservoir Regulation Voltage vs. Temperature 1.15 1.20 1.25 1.30 1.35 1.40 -50 -25 0 25 50 75 100 125 150 VRES_UVLO_HYS (V) TEMPERATURE ( C) Reservoir Regulation UVLO Hysteresis vs. Temperature

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 9 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN = 12V, L = 68µH, TJ = -40°C to +150°C, unless otherwise noted. 0.95 1.00 1.05 1.10 1.15 1.20 1.25 -50 -25 0 25 50 75 100 125 150 EN UVLO THRESHOLD (V) TEMPERATURE ( C) EN UVLO Threshold vs. Temperature EN UVLO Rising EN UVLO Falling

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 10 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. 100 200 300 400 500 2 3 4 5 6 7 8 9 10 GATE RISING TIME (ns) CGATE-SOURCE (nF) Gate Rising Time vs. Gate Capacitance VGATE-SOURCE=5V VGATE-SOURCE=10V 100 120 2 3 4 5 6 7 8 9 10 GATE FALLING TIME (ns) CGATE-SOURCE (nF) Gate Falling Time vs. Gate Capacitance VGATE-SOURCE=5V VGATE-SOURCE=10V

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 11 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, COUT = 470µF, TA = 25°C, unless otherwise noted. (7) CISPR25 Class 5 Peak Conducted Emissions 150kHz to 108MHz CISPR25 Class 5 Average Conducted Emissions 150kHz to 108MHz CISPR25 Class 5 Peak Radiated Emissions 150kHz to 30MHz CISPR25 Class 5 Average Radiated Emissions 150kHz to 30MHz CISPR25 Class 5 Peak Radiated Emissions Horizontal, 30MHz to 200MHz CISPR25 Class 5 Average Radiated Emissions Horizontal, 30MHz to 200MHz -20 -15 -10 0.1 10 PEAK CONDUCTED EMI (dBµV) Frequency (MHz)1 CISPR25 CLASS 5 LIMITS PK NOISE FLOOR 108 -20 -15 -10 0.1 10 AVERAGE CONDUCTED EMI (dBµV) Frequency (MHz)1 CISPR25 CLASS 5 LIMITS AVG NOISE FLOOR 108 -10 0.1 10 PEAK RADIATED EMI (dBµV/m) Frequency (MHz)1 CISPR25 CLASS 5 LIMITS PK NOISE FLOOR -10 0.1 10 AVERAGE RADIATED EMI (dBµV/m) Frequency (MHz)1 CISPR25 CLASS 5 LIMITS AVG NOISE FLOOR 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 PEAK RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS PK NOISE FLOOR HORIZONTAL POLARIZATION 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 AVERAGE RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS AVG NOISE FLOOR HORIZONTAL POLARIZATION

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 12 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, COUT = 470uF, TA = 25°C, unless otherwise noted. (7) CISPR25 Class 5 Peak Radiated Emissions Vertical, 30MHz to 200MHz CISPR25 Class 5 Average Radiated Emissions Vertical, 30MHz to 200MHz CISPR25 Class 5 Peak Radiated Emissions Horizontal, 200MHz to 1GHz CISPR25 Class 5 Average Radiated Emissions Horizontal, 200MHz to 1GHz CISPR25 Class 5 Peak Radiated Emissions Vertical, 200MHz to 1GHz CISPR25 Class 5 Average Radiated Emissions Vertical, 200MHz to 1GHz Note: 7) The EMC test results are based on the application circuit, and tested on the EVQ5850-J-00A (see Figure 4 on page 26). 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 PEAK RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS PK NOISE FLOOR VERTICAL POLARIZATION 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 AVERAGE RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS AVG NOISE FLOOR VERTICAL POLARIZATION 200 300 400 500 600 700 800 900 1000 PEAK RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS PK NOISE FLOOR HORIZONTAL POLARIZATION 200 300 400 500 600 700 800 900 1000 AVERAGE RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS AVG NOISE FLOOR HORIZONTAL POLARIZATION 200 300 400 500 600 700 800 900 1000 PEAK RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS PK NOISE FLOOR VERTICAL POLARIZATION 200 300 400 500 600 700 800 900 1000 AVERAGE RADIATED EMI (dBµV/m) Frequency (MHz) CISPR25 CLASS 5 LIMITS AVG NOISE FLOOR VERTICAL POLARIZATION

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 13 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. Steady State (for Internal Boost) IOUT = 0A Steady State (for Smart Diode) IOUT = 0A CH3: VOUT CH2: VRES CH1: VSW CH4: IL CH3: VIN CH2: VOUT MATH: VGS CH1: VGATE CH4: IOUT Steady State (for Internal Boost) IOUT = 5A Steady State (for Smart Diode) IOUT = 5A CH3: VOUT CH2: VRES CH1: VSW CH4: IL CH3: VIN CH2: VOUT MATH: VGS CH1: VGATE CH4: IOUT Start-Up through VIN (for Internal Boost) IOUT = 0A Start-Up through VIN (for Smart Diode) IOUT = 0A CH3: VIN CH2: VRES CH1: VSW CH4: IL CH3: VIN CH2: VOUT CH1: VGATE MATH: VGS CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 14 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. Start-Up through VIN (for Internal Boost) IOUT = 5A Start-Up through VIN (for Smart Diode) IOUT = 5A CH3: VIN CH2: VRES CH1: VSW CH4: IL CH3: VIN CH2: VOUT CH1: VGATE MATH: VGS CH4: IOUT Shutdown through VIN (for Internal Boost) IOUT = 0A Shutdown through VIN (for Smart Diode) IOUT = 0A CH3: VIN CH2: VRES CH1: VSW CH4: IL CH3: VIN CH1: VGATE CH2: VOUT MATH: VGS CH4: IOUT Shutdown through VIN (for Internal Boost) IOUT = 5A Shutdown through VIN (for Smart Diode) IOUT = 5A CH3: VIN CH2: VRES CH1: VSW CH4: IL CH3: VIN CH2: VOUT CH1: VGATE MATH: VGS CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 15 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. Start-Up through EN (for Internal Boost) IOUT = 0A Start-Up through EN (for Smart Diode) IOUT = 0A CH3: VEN CH2: VRES CH1: VSW CH4: IL CH3: VEN CH2: VOUT CH1: VGATE MATH: VGS CH4: IOUT Start-Up through EN (for Internal Boost) IOUT = 5A Start-Up through EN (for Smart Diode) IOUT = 5A CH3: VEN CH2: VRES CH1: VSW CH4: IL CH3: VEN CH2: VOUT CH1: VGATE MATH: VGS CH4: IOUT Shutdown through EN (for Internal Boost) IOUT = 0A Shutdown through EN (for Smart Diode) IOUT = 0A CH3: VEN CH2: VRES CH1: VSW CH4: IL CH3: VEN CH2: VOUT MATH: VGS CH1: VGATE CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 16 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. Shutdown through EN (for Internal Boost) IOUT = 5A Shutdown through EN (for Smart Diode) IOUT = 5A CH3: VEN CH2: VRES CH1: VSW CH4: IL CH3: VEN CH2: VOUT MATH: VGS CH1: VGATE CH4: IOUT Load Transient IOUT = 0A to 5A, 6A/μs PG Start-Up through VIN IOUT = 0A CH3: VIN CH2: VOUT CH1: VGATE MATH: VGS CH4: IOUT CH3: VRES CH2: VOUT CH1: VPG CH4: IOUT PG Start-Up through VIN IOUT = 5A PG Shutdown through VIN IOUT = 0A CH3: VRES CH2: VOUT CH1: VPG CH4: IOUT CH3: VRES CH2: VOUT CH1: VPG CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 17 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. PG Shutdown through VIN IOUT = 5A PG Start-Up through EN IOUT = 0A CH3: VRES CH2: VOUT CH1: VPG CH4: IOUT CH3: VEN CH2: VRES CH1: VPG CH4: IOUT PG Start-Up through EN IOUT = 5A PG Shutdown through EN IOUT = 0A CH3: VEN CH2: VRES CH1: VPG CH4: IOUT CH3: VEN CH2: VRES CH1: VPG CH4: IOUT PG Shutdown through EN IOUT = 5A Negative Pulse IOUT = 0A CH3: VEN CH2: VRES CH1: VPG CH4: IOUT CH2: VOUT CH3: VIN CH1: VGATE CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 18 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. Negative Pulse IOUT = 5A Load Dump IOUT = 5A CH2: VOUT CH3: VIN CH1: VGATE CH4: IOUT CH3: VIN CH2: VOUT CH1: VGATE CH4: IOUT Cold Crank IOUT = 0A Cold Crank IOUT = 5A CH1: VIN CH3: VGATE CH2: VOUT CH4: VSW CH3: VIN CH2: VOUT CH1: VGATE CH4: IOUT Supply Voltage Ramps Up and Down Slowly IOUT = 0A Supply Voltage Ramps Up and Down Slowly IOUT = 5A CH3: VIN CH2: VOUT CH1: VGATE CH4: IOUT CH3: VIN CH2: VOUT CH1: VGATE CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 19 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. Supply Voltage Ramps Up Quickly and Down Slowly IOUT = 0A Supply Voltage Ramps Up Quickly and Down Slowly IOUT = 5A CH3: VIN CH2: VOUT CH1: VGATE CH4: IOUT CH3: VIN CH2: VOUT CH1: VGATE CH4: IOUT Simultaneous Input VPP = 6V, f = 15Hz, IOUT = 0A Simultaneous Input VPP = 6V, f = 1kHz, IOUT = 0A CH3: VIN MATH: VGS CH1: VGATE CH2: VOUT CH4: IOUT CH3: VIN CH1: VGATE CH2: VOUT MATH: VGS CH4: IOUT Simultaneous Input VPP = 6V, f = 1kHz, IOUT = 0A Simultaneous Input VPP = 6V, f = 1kHz, IOUT = 3A CH3: VIN MATH: VGS CH1: VGATE CH2: VOUT CH4: IOUT CH3: VIN CH2: VOUT MATH: VGS CH1: VGATE CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 20 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, IOUT = 5A, L = 68µH, TA = 25°C, unless otherwise noted. Start Pulses IOUT = 5A CH3: VIN CH2: VOUT CH1: VGATE CH4: IOUT

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 21 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM PG SW RES VCC Control Logic DRAINGATE Regulation -Fast On -Fast Off DRAIN +20mV DRAIN +75mV DRAIN -4mV SOURCE PG Indicator Part Disabled RES < RES_UV Fast On Time >17µs EN/UVLO VCC Regulator VCC GND - 220mA N-Channel MOSFET Driver Figure 1: Functional Block Diagram

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 22 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. OPERATION The MPQ5850 is an 8-pin smart diode controller that drives an external N -channel MOSFET to minimize power loss, including DC forward loss and AC rectification loss. Smart Diode Operation During normal operation, when VSOURCE > VDRAIN, the MPQ5850 modulates the gate of the external N-channel MOSFET to regulate the source-to- drain voltage to about 20mV. This min imizes power loss and allows small negative currents to be easily detected. Generally, the source-to-drain voltage is regulated to about 20mV. When the load current rises, the GATE voltage rises until the MOSFET is fully on. If the load current drops, the GATE amplifier drives the MOSFET ’s gate lower to maintain a 20mV drop. If the drain-to-source voltage exceeds 20mV, a large current modifies the GATE pin’s voltage to regulate the drain -to-source voltage . If a negative cur rent flows through the external N - channel MOSFET, the device detects a source- to-drain negative voltage drop. If the drop exceeds -4mV, the MPQ5850 pulls down the GATE pin to turn off the external N -channel MOSFET quickly. If a forward current flows through the external N-channel MOSFET (either the body or channel), the device detects a source-to-drain forward voltage drop. If the drop exceeds 75mV, the MPQ5850 pulls up the GATE pin to quickly turn on the external N -channel MOSFET. This allows high -frequency AC waveforms (up to 100kHz) to be rectified with minimal system and N-channel MOSFET power loss. Boost Converter The integrated boost converter uses fixed peak current mode control. When the reservoir floating supply is below 12V, the boost conve rter requests another turn-on pulse. This pulse terminates when the inductor current reaches 220mA. The inductor current should reach 0mA before the next on cycle begins. This sets a maximum frequency (fMAX) depending on VDRAIN. fMAX can be calculated with Equation (1): MAX ON OFF 1f tt= + (1) Where tON is the on time and tOFF is the off time. tON can be estimated with Equation (2): PEAK ON PEAK DRAIN SW ILt IVR 2 − (2) tOFF can be calculated with Equation (3): PEAK OFF RES DIODE ILt VV = + (3) Start-Up and Low-Voltage Operation The MPQ5850 starts in the off state. In this state, the gate is passively pulled to SOURCE, and the boost converter is di sabled. Once VDRAIN exceeds the under-voltage lockout ( UVLO) threshold, the device enters the disabled stat e. The device is enabled when it enters a logic high state. In the disabled state, the gate is passively pulled to source, the boost converter is disabled, and the PG pin is pulled low. Once the EN/UVLO pin is pulled high, the device enters the start-up state, which causes the boost converter to turn on. When the reservoir cap acitor exceeds the reservoir UVLO threshold, normal operation begins. During normal operation, t he gate is actively modulated based on VSOURCE and VDRAIN, and the PG pin is high when the source-to-drain voltage is regulated. The DRAIN pin is the power supply of the internal circuitry . DRAIN also controls the MOSFET’s gate voltage. If VDRAIN exceeds its UVLO threshold, then the MPQ5850 operates normally, even in cold-crank conditions down to 0V. A large electrolytic output capacitor is required under these conditions. If VDRAIN drops below the UVLO threshold, the device pulls down the GATE pin to SOURCE until the voltage on the reservoir capacitor discharges below VRES_UVLO. This allows the device to minimize forward voltage drops during temporary low voltage transients, such as under cold-crank conditions.

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 23 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. Power Good (PG) The power good (PG) pin is an open-drain pin designed to indicate the status of the MPQ5850. PG asserts low when the fast pull-up current is active for longer than 17µs, the reservoir capacitor is out of regulation , or the device is disabled. Otherwise, PG de-asserts, and the pin is pulled up to the external source through a pull- up resistor.

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 24 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

APPLICATION INFORMATION

Selecting the Power MOSFET The power MOSFET must support the maximum steady current during forward operation , and withstand the worst-case battery transients during reverse blocking operation. The steady state power dissipation is based on the RDS(ON) of the power MOSFET and the load current. If the load is light (ILOAD x RDS(ON) < VSD), the forward drop is regulated to V SD (typically 20mV). The power loss be calculated with Equation (4): CONDUCTION SD LOADP V I = (4) Under heavy load s, the MOSFET is fully enhanced, so power dissipation depends on the RDS(ON) of the MOSFET. The power loss can be estimated with Equation (5): CONDUCTION LOAD DS(ON)P I R = (5) As the high -amplitude ripple on the input is rectified, a MOSFET with the smallest total gate charge (QGTOT) is required. A MOSFET with smaller QGTOT not only reduces reverse current during the turn-off delay but it also lowers driver loss. The operating MOSFET’s drain-to-source voltage must be able to support the worst-case conditions, such as when there is a voltage step or the battery voltage goes from a positive to negative voltage. The worst-case condition occurs when V IN is in reverse and V OUT is not discharged to low. VDSS must meet the condition calculated with Equation (6): DSS OUT INV V V+ (6) The gate-to-source voltage should be rated to be ±15V or greater. Selecting the Boost Inductor The value of the inductor affects the driver’s maximum current capability. There is a blanking time in the boost converter, and the inductor current is not detected during the blanking time. The relationship between the blanking time and temperature is shown in Figure 2. To ensure that the i nductor current does not exceed 22 0mA during the blanking time, the inductor value (L) should meet the condition estimated with Equation (7): Figure 2: Blanking Time vs. Temperature DRAIN ON _ BLANKING PEAK VtL I (7) Where VDRAIN is the DRAIN pin ’s voltage (in V), and IPEAK is the integrated boost converter ’s current limit (typically 220mA). Based on the special application to select the required inductor, if VDRAIN is 36V, the inductor should be greater than 49µH in 25 oC temp . Consider the derating of the inductance at different temperatures and currents . It is recommended to select a minimum 68µH inductor with a saturation current exceeding 220mA and a RMS current greater than 80mA. Small-chip inductors (e.g. the LQH2MPZ series from Murata) are recommended. The LQH3NPN series inductors are also suitable. Selecting the Reservoir Capacitor Connect a minimum 1µF capacitor , with a minimum 25V rating, from the RES pin to the DRAIN pin. A larger-value capacitor can support the IC if the DRAIN voltage is below its UVLO threshold. Calculate the min imum reservoir capacitance with Equation (8): GATE S ON RES RES _ UVLO _ HYS I (t t )C V − (8) Selecting the Electrolytic Capacitor and Ripple Voltage During rectification, the electrolytic capacitor (CLOAD) reduces the load’s ripple voltage. The load ripple voltage (VR) is determined by CLOAD, the source ripple frequency, the ripple amplitude, and the load current. The voltage drops with the 200 250 300 350 400 450 500 -50 -25 0 25 50 75 100 125 150 175 BLANKING TIME (ns) TEMPERATURE ( C) Blanking Time vs.Temperature

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 25 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. frequency. CLOAD can be estimated with Equation (9): AC R LOAD LOAD AC R

4 V VCI 4 V f V

Where VAC is the SOURCE voltage ripple amplitude (in V), f is the ripple frequency (in Hz), CLOAD is the capacitance of the electrolytic capacitor (in F), and ILOAD is the load current (in A). If the ripple voltage (VR) is below 2V, f is 5kHz, VAC is 3V (6VPP), and I LOAD is 5A, then C LOAD is 417μF. Selecting the TVS Diode The MPQ5850 can be damaged by the negative pulse on the SOURCE pin, since the voltage of the SOURCE pin is limit ed to -36V. Connect a TVS diode between S OURCE and GND to protect the part. The SMBJ24CA is recommended, as it can protect the MPQ5850 from negative pulses and over -voltage conditions. PCB Layout Guidelines (8) An optimized PCB layout is very important for proper operation. A four-layer layout is strongly recommended to improve thermal performance. For the best results, refer to Figure 3 and follow the guidelines below: 1. Place SW close to the device with short, direct, and wide traces. 2. Use large copper areas to minimize conduction loss and thermal stress. 3. Place the ceramic input capacitors as close to the IN and GND pins as possible to minimize high-frequency noise. 4. Route SW away from sensitive analog areas. 5. Use multiple vias to connect the power planes to internal layer. Note: 8) The recommended PCB layout is based on the circuit in Figure 4 on page 26. Top Silk and Top Layer Mid-Layer 1 Mid-Layer 2 Bottom Layer and Bottom Silk Figure 3: Recommended PCB Layout

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 26 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUIT 470µF R2 1µF 68µH GND SOURCE EN/UVLO1 GATE DRAIN RES SW PG GND MPQ5850 10nF GND100kΩ 4.7µF GND VIN 100kΩ EN VOUT PG SMBJ24CA GND GND IOUT = 5A 0603 0603 50V 0603 0805 25V 1206 50V 0603 35V 1V 1.2V Figure 4: Typical Application Circuit of a 12V Automotive Battery with a 5A Load

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 27 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

PACKAGE INFORMATION

TSOT23-8 (2mmx3mm) FRONT VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION, OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-193, VARIATION BA. 6) DRAWING IS NOT TO SCALE. 7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) TOP VIEW RECOMMENDED LAND PATTERN SEATING PLANE SIDE VIEW DETAIL ''A'' SEE DETAIL ''A'' IAAAA PIN 1 ID See note 7 EXAMPLE TOP MARK

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 MPQ5850 Rev. 1.1 MonolithicPower.com 28 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package MPQ5850GJ-Z TSOT23-8 3000 N/A 7in 8mm 4mm MPQ5850GJ-AEC1-Z Pin1 1 1 1 1 ABCDABCDABCDABCD Feed Direction

MPQ5850 – 36V, SMART DIODE CONTROLLER W/ REVERSE PROTECTION, AEC-Q100 Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ5850 Rev. 1.1 MonolithicPower.com 29 2/9/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 08/27/2021 Initial Release - 1.1 2/3/2022 Updated the supported cold crank value from “3V” to “0V” in the Features section 1 Updated the SW pin number to “4” and the RES pin number to “5” in the Pin Functions section 4 Updated the reservoir UVLO rising min value from “9V” to “8V” 5 Updated the reservoir regulation UVLO hysteresis conditions from “VREG - VRES_UVLO” to “VREG - VRES_UVLO - VRES_UVLO_HYS” 6 Added the Cold Crank waveform where IOUT = 0A to the Typical Performance Characteristics section 18 Added the updated cold crank description in the Start-Up and Low-Voltage Operation section 22 Updated the Selecting the Boost Inductor section: added the Blanking Time vs. Temperature curve as Figure 2 ; added more detailed information ; updated the recommended inductor information Grammar and formatting updates; updated figure numbers All

Summary

36V, Smart Diode Controller with Reverse Protection, AEC-Q100 Qualified 2/9/2022 Rev. 1.1

Description