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MPQ4487 36V, 6A, Step-Down Converter with Programmable Frequency and Spread Spectrum Option, Dual USB Charging Ports Supporting EN, Fault Indication, and Type-C 5V@ 3A DFP Mode for Automotive, AEC-Q100 Qualified MPQ4487 Rev.1.0 www.MonolithicPower.com 1 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. The Future of Analog IC Technology
DESCRIPTION
The MPQ4487 integrates a monolithic, step- down, switch-mode converter with two USB current-limit switches and Type-C 5V @ 3A mode configuration channels for each port. The MPQ4487 achieves 6A of output current with excellent load and line regulation over a wide input supply range. The output of each USB switch is current- limited. Both USB ports support USB Type-C 5V @ 3A DFP mode, eliminating the need for outside user interaction. Full protection features include hiccup current limiting, output over-voltage protection (OVP), and thermal shutdown. The MPQ4487 requires a minimal number of readily available, standard, external components and is available in a QFN-26 (5mmx5mm) package.
FEATURES
Wide 6V to 36V Operating Input Voltage Range Selectable Output Voltage Line Drop Compensation Accurate USB1/USB2 Output Current Limit 18m Ω/15mΩ Low R DS(ON) Internal Buck Power MOSFETs 18m Ω/18mΩ Low R DS(ON) Internal USB1/USB2 Power MOSFETs Frequency Adjustable (250kHz to 2.2MHz) Frequency Spread Spectrum for MPQ4487GU-FD-AEC1 Forced Continuous Conduction Mode (CCM) Operation Load Shedding Versus Temperature Hiccup Current Limit for both Buck and USB EN Control for USB1 and USB2 Fault Indication for USB1 and USB2 Supports USB Type-C 5V @ 3A Mode ±8kV HBM ESD Rating for USB1 and USB2 Available in a QFN-26 (5mmx5mm) Package Available in AEC-Q100 Grade 1
Applications
USB Hubs USB Type-C Charging Ports All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks o f Monolithic Power Systems, Inc.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 2 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL APPLICATION 100 01234567
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 3 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking MPQ4487GU-AEC1 QFN-26 (5mmx5mm) See Below MPQ4487GU-FD-AEC1 * For Tape & Reel, add suffix –Z (e.g. MPQ4487GU-AEC1–Z, MPQ4487GU-FD-AEC1–Z) DEVICE COMPARISON INFORMATION Part Number Frequency Spread Spectrum MPQ4487GU-AEC1 No MPQ4487GU-FD-AEC1 Yes TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP4487: Part number LLLLLLL: Lot number PACKAGE REFERENCE TOP VIEW QFN-26 (5mmx5mm)
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 4 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) to V IN + 0.3V (43V for <10ns) Continuous power dissipation (TA = +25°C) (3) Recommended Operating Conditions (4) Operating junction temp. (T Thermal Resistance θJA θJC QFN-26 (5mmx5mm) NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) For details on EN’s ABS max rating, please refer to the EN Control section on page 13. 3) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Measured on a 4-layer PCB (50mmx50mm). 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on JESD51-7, 4-layer PCB.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 5 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 5V, CC1 to ground with a 5.1k Ω resistor, CC3 to ground with a 5.1k Ω resistor, TJ = -40°C to +125°C (6), typical value is tested at TJ = +25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Supply current (shutdown) I IN V EN = 0V 3 10 μA Supply current (quiescent) IQ1 No switching 1 2 mA IQ2 CC floating, no switching, TJ = +25°C 400 550 μA EN rising threshold V EN Risin g -3% 1.235 +3% V EN hysteresis V EN HYS 230 mV EN pull-down resistor R EN 2 M Ω Thermal shutdown (7) T TSD 165 C Thermal hysteresis (7) T TSD_HYS 20 C VCC regulator V CC 4.3 4.6 4.9 V VCC load regulation V CC LOG I CC = 50mA 1 3 % Step-Down Converter VIN under-voltage lockout threshold rising VIN_UVLO 4.6 5.0 5.4 V VIN under-voltage lockout threshold hysteresis VUVLO_HYS 700 mV HS switch on resistance R DSON HS 18 40 m Ω LS switch on resistance R DSON LS 15 30 m Ω Output voltage V OUT OUT_SEL = low -2% 5.10 +2% V OUT_SEL = float, TJ = +25°C -1% 5.17 +1% OUT_SEL = float, TJ = -40°C OUT_SEL = high -2% 5.30 +2% Output over-voltage protection VOVP_R 5.45 5.85 6.25 V Output OVP recovery V OVP F 5.3 5.7 6.1 V Output to ground resistance R FB EN = 0V, T J = +25°C 100 160 220 k Ω Low-side current limit I LS LIMIT -2 A Switch leakage SW LKG VEN = 0V, VSW = 36V, TJ = +25°C 1 μA VEN = 0V, VSW = 36V, TJ = -40°C to +125°C 5 High-side current limit I LIMIT V OUT = 0V 8 12 16 A Oscillator frequency FSW1 Pull R FREQ to GND 185 250 315 kHz FSW2 R FREQ = 66.5kΩ 250 350 450 FSW3 RFREQ = 9.53kΩ, refer to application note 1800 2200 2600 FSW4 R FREQ = float 360 450 540 Frequency spread spectrum span (MPQ4487GU-FD-AEC1) FSS RFREQ = float, based on 450kHz ±10 %
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 6 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VEN = 5V, CC1 to ground with a 5.1k Ω resistor, CC3 to ground with a 5.1k Ω resistor, TJ = -40°C to +125°C (6), typical value is tested at TJ = +25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Maximum duty cycle D MAX FREQ = 450kHz 91 95 99 % Minimum off time T OFF MIN 110 ns Minimum on time (7) TON_MIN 130 ns Soft-start time T SS Output from 10% to 90% 1 2 3.4 ms USB Switch (USB1 and USB2) Under-voltage lockout threshold rising VUSB_UVR 3.7 4 4.3 V Under-voltage lockout threshold hysteresis VUSB_UVHYS 200 mV Switch on resistance R DSON SW 18 35 m Ω Output to ground resistance R DIS_USB Apply 5V voltage on USB output, float CC 250 500 750 k Ω USB OVP clamp V USB OV 5.3 5.6 5.9 V Current limit ILimit1 VOUT drops 10%, Type-C mode, TJ = +25°C -6% 3.55 6% A ILimit2 VOUT drops 10%, Type-A mode, TJ = +25°C 2.6 2.75 2.9 A Line drop compensation V DROP COM At 2.4A load, V OUT = 5.17V 40 90 140 mV VBUS soft-start time T SS Output from 10% to 90% 1 2 3 ms Hiccup mode on time T HICP_ON2 OC, VOUT drops 10%, TJ = +25°C 3.5 5 6.5 ms OC, VOUT drops 10%, TJ = -40°C to +125°C 3 5 7 Hiccup mode off time T HICP OFF V OUT connected to GND 1 2 3 s EN1, EN2 logic high input V ENSW H 1.2 V EN1, EN2 logic low input V ENSW L 0.8 V FLT1, FLT2 output low voltage VFLT_Low Fault condition, sink 1mA 150 mV FLT1, FLT2 leakage I FLT LKG V FAULT = 5V 1 μA FLT1, FLT2 deglitch time T FLT DEG Over-current 3 5 7 ms
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 7 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VEN = 5V, CC1 to ground with a 5.1k Ω resistor, CC3 to ground with a 5.1k Ω resistor, TJ = -40°C to +125°C (6), typical value is tested at TJ = +25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units USB Type-C 5V @ 3A Mode – CC1, CC2, CC3, and CC4 CC resistor to disable Type- C mode RA CC1 and CC3 pins. For Type-C mode applications, add a 1nF capacitor on CC1 and CC3. 70 90 k Ω CC voltage to enable VCONN VRa 0.75 V CC voltage to enable VBUS V Rd 0.9 2.45 V CC detach threshold V OPEN 2.75 V CC voltage falling debounce timer TCC_debounce V BUS enable deglitch 100 144 200 ms CC voltage rising debounce timer TPD_debounce V BUS disable deglitch 10 15 20 ms VCONN output power P VCONN VCONN comes from the buck output with some series resistance, for applications without SuperSpeed data. 100 mW NOTES: 6) All min/max parameters are tested at T J = 25°C. Limits over temperature are guaranteed by design, characterization, and correlation. 7) Guaranteed by design and characterization test.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 8 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 5.17V, L = 4.7µH, TA = 25°C, unless otherwise noted.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 9 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5.17V, L = 4.7µH, TA = 25°C, unless otherwise noted.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 10 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5.17V, L = 4.7µH, TA = 25°C, unless otherwise noted. 100 01234567 100 0 0.5 1 1.5 2 2.5 3
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 11 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PIN FUNCTIONS QFN 5x5 Pin # Name Description
1 CC1
Configuration channel. CC1 is used to detect connections and configure the interface across the USB1 Type-C cables and connect ors. Once a connection is established, CC1 or CC2 is reassigned to provide power over the VCONN pin of the plug. 2 USB1 USB1 output. 3, 15, 25 OUT Buck output. OUT is the power input for USB1 and USB2. 4, 14 IN Supply voltage. IN is the drain of the internal power device and provides power to the entire chip. The MPQ4487 operates from a 6V to 36V input voltage. A capacitor (C IN) prevents large voltage spikes at the input. Place CIN as close to the IC as possible. 5, 13 PGND Power ground. PGND is the reference ground of the regulated output voltage. PGND requires careful consideration during the PCB layout. Connect PGND with copper traces and vias. 6 AGND Analog ground. Connect AGND to PGND. 7 VCC Internal 4.6V LDO regulator output. Decouple VCC with a 1µF capacitor. 8, 9, 26 SW Switch output. Use a wide PCB trace to make the connection. 10 BST Bootstrap. A 0.22µF capacitor is connected between SW and BST to form a floating supply across the high-side switch driver. 11 OUT_SEL Buck output voltage set. By setting OUT_SEL to low, float, or high, three different output voltages can be achieved: 5.1V, 5.17V, or 5.3V.
12 FREQ
Switching frequency program input. For the MPQ4487GU-AEC1, connect a resistor from FREQ to GND to set the switching frequency. Float FREQ or connect FREQ to VCC for the default 450kHz frequency. Connect FREQ to ground for a 250kHz internal frequency. For the MPQ4487GU-FD-AEC1, float FREQ or connect FREQ to VCC to achieve a ±10% frequency spread spectrum based on 45 0kHz. Connect a resistor from FREQ to GND or pull FREQ to GND to set the switching frequency without a frequency spread spectrum. 16 USB2 USB2 output.
17 CC4
Configuration channel. CC4 is used to detect connections and configure the interface across the USB2 Type-C cables and connect ors. Once a connection is established, CC3 or CC4 is reassigned to provide power over the VCONN pin of the plug.
18 CC3
Configuration channel. CC3 is used to detect connections and configure the interface across the USB2 Type-C cables and connect ors. Once a connection is established, CC3 or CC4 is reassigned to provide power over the VCONN pin of the plug. 19 FLT2 USB2 fault indication. FLT2 indicates over-current or over-temperature conditions. FLT2 is an open drain in normal conditions. Pull FLT2 low during fault conditions. 20 EN2 USB2 on/off control input. By default, EN2 is pulled low by an internal 1MΩ resistor. 21 EN On/off control of the entire chip. Pull EN down to ground internally with a 2M Ω resistor. 22 EN1 USB1 on/off control input. By default, EN1 is pulled low by an internal 1MΩ resistor. 23 FLT1 USB1 fault indication. FLT1 indicates over-current or over-temperature conditions. FLT1 is an open drain in normal conditions. Pull FLT1 low during fault conditions.
24 CC2
Configuration channel. CC2 is used to detect connections and configure the interface across the USB1 Type-C cables and connect ors. Once a connection is established, CC1 or CC2 is reassigned to provide power over the VCONN pin of the plug.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 12 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. BLOCK DIAGRAM Σ Bootstrap Regulator HS Driver LS Driver VCCControl Logic Oscillator VCC Regulator Reference Line Drop Compensation IN VCC OUT AGND BST Current Sense Amplifier Current Limit Comparator PWM Comparator OVP Comparator Error Amplifier SW PGND Curent Sense Curent SenseCharge Pump Control Logic Thermal Sense UVLO Discharge Discharge USB1 USB2 FREQ Current Limit SS CC1 CC2 CC3 CC4 Vconn from Buck output5V Type-C Control OUT_SEL EN2 Fault FLT1 5ms Deglitch EN1 Fault 5ms Deglitch FLT2 EN 2MΩ Rd1 Rd2 R2 FB Rd3 Rd4 USB2 Type-A Mode Detect USB1 Type-A Mode Detect Figure 1: Functional Block Diagram
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 18 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Disable Type-C Mode (Type-A Mode) During the MPQ4487 initial start-up, the IC sources 10 μA for 20 μs on CC1. If the CC1 voltage falls into a 400mV to 1.2V range, USB1 latches in Type-A mode unless the part is re- enabled. Type-C mode is disabled, so CC1's attach and detach logic is disabled, and V BUS is always enabled. The current limit changes to a Type-A spec. The same logic is implemented on CC3 for USB2. To trigger Type-A mode, the external pull-down resistor should be 70 - 90k Ω. Do not connect extra capacitors on CC1 and CC3. In normal Type-C mode applications, a 1nF capacitor should be added on CC1 and CC3 to avoid falsely triggering Type-A mode. If two Ra resistors pull down CC1 and CC2, or two Rd resistors pull down CC1 and CC2, there is no action inside the IC (V BUS is not enabled). Load Shedding vs. Temperature The MPQ4487 monitors the die temperature and changes its output current capability dynamically. If the die temperature is higher than 125°C, the USB port's CC pin pull-up resistance (Rp) changes to 22k Ω to indicate that its source capability has changed to 1.5A. Meanwhile, V BUS changes to 4.77V. If the die temperature recovery is lower than 100°C for 16 seconds, V BUS reverts back to the normal voltage set by OUT_SEL. Meanwhile, the USB Type-C current capability changes back to 3A (Rp = 10k Ω). The current limit threshold remains at 3.55A during this period. Thermal Shutdown Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die temperature exceeds 165°C, the entire chip shuts down. When the temperature falls below its lower threshold (typically 145°C), the chip is enabled.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 19 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Table 2: CC Logic Truth Table EN EN1 EN2 CC of USB1 (8) CC of USB2 (8) Buck VCONN (USB1) USB1 VCONN (USB2) USB2
0 X X X X Disabled Disabled Disabled Disabled Disabled
1 0 0 X X Enabled Disabled Disabled Disabled Disabled 1 1 0 AUDIO X Enabled Disabled Disabled Disabled Disabled DEBUG X Enabled Disabled Disabled Disabled Disabled “A” (9) X Enabled Disabled Enabled Disabled Disabled Rd, Ra X Enabled Enabled Enabled Disabled Disabled Open X Enabled Disabled Disabled Disabled Disabled 1 0 1 X AUDIO Enabled Disabled Disabled Disabled Disabled X DEBUG Enabled Disabled Disabled Disabled Disabled X “A” Enabled Disabled Disabled Disabled Enabled X Rd, Ra Enabled Disabled Disabled Enabled Enabled X Open Enabled Disabled Disabled Disabled Disabled 1 1 1 AUDIO X Enabled Disabled Disabled X X DEBUG X Enabled Disabled Disabled X X “A” X Enabled Disabled Enabled X X Rd, Ra X Enabled Enabled Enabled X X Open X Enabled Disabled Disabled X X X AUDIO Enabled X X Disabled Disabled X DEBUG Enabled X X Disabled Disabled X “A” Enabled X X Disabled Enabled X Rd, Ra Enabled X X Enabled Enabled X Open Enabled X X Disabled Disabled 1 1 1 AUDIO Rd, Ra Enabled Disabled Disabled Enabled Enabled DEBUG Enabled Disabled Disabled Enabled Enabled “A” Enabled Disabled Enabled Enabled Enabled Open Enabled Disabled Disabled Enabled Enabled Rd, Ra AUDIO Enabled Enabled Enabled Disabled Disabled DEBUG Enabled Enabled Enabled Disabled Disabled “A” Enabled Enabled Enabled Disabled Enabled Rd, Ra Enabled Enabled Enabled Enabled Enabled Open Enabled Enabled Enabled Disabled Disabled “A” “A” Enabled Disabled Enabled Disabled Enabled Open “A” Enabled Disabled Disabled Disabled Enabled “A” Open Enabled Disabled Enabled Disabled Disabled Open Open Enabled Disabled Disabled Disabled Disabled NOTES: 8) USB1 and USB2 are symmetric to each other. 9) "A" means Type-A mode. CC1 (CC3 for USB2) is requested to be pulled down by a 80.6k Ω resistor to enter this mode.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 20 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
APPLICATION INFORMATION
For most applications, use an inductor with a DC current rating at least 25% higher than the maximum load current. Select an inductor with a small DC resistance for optimum efficiency. For most designs, the inductor value can be derived with Equation (2): OUT IN OUT IN L OSC V( V V )L VI f Where ∆IL is the inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (3): III L LOAD)MAX(L (3) Selecting the Buck Input Capacitor The input current to the step-down converter is discontinuous and therefore requires a capacitor to supply AC current while maintaining the DC input voltage. Use low ESR capacitors for optimum performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. 100µF electrolytic and 50µF ceramic capacitors are recommended in automotive applications at a 450kHz switching frequency. Since the input capacitor (C1) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (4): IN OUT IN OUTLOAD1C V V1V VII (4) The worst-case condition occurs at V IN = 2VOUT, shown in Equation (5): II LOAD 1C (5) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using an electrolytic capacitor, place two additional high-quality ceramic capacitors as close to IN as possible. Estimate the input voltage ripple caused by the capacitance with Equation (6): LOAD OUT OUT IN INSI N IV VV1 fC 1V V Selecting the Buck Output Capacitor The device requires an output capacitor (C2) to maintain the DC output voltage. Estimate the output voltage ripple with Equation (7): OUT OUT OUT ESR S1 I N S VV 1V1 R fL V 8 fC 2 Where L1 is the inductor value, and R ESR is the equivalent series resistance (ESR) value of the output capacitor. For an electrolytic capacitor, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (8): OUT OUT OUT ESR INS1 VV∆V1 R fL V A 100 - 270 μF capacitor with an ESR less than 50mΩ (e.g.: polymer or tantalum capacitors) and three 10 μF ceramic capacitors are recommended in the application (see Table 3). Table 3: Recommended External Components Switching Frequency Inductor Input Cap Buck Output Capacitor 250kHz 8 μH 50µF ceramic cap + 100µF E- cap 30µF ceramic cap + 270µF Polymer cap 450kHz 4.7 μH 50µF ceramic cap + 100µF E- cap 30µF ceramic cap + 270µF Polymer cap
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 21 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. ESD Protection for I/O Pins Higher ESD levels should be considered for all USB I/O pins. The MPQ4487 features high ESD protection up to ±8kV human body model on USB1 and USB2, and ±6kV human body model on CC1 through CC4. The ESD structures can withstand high ESD both in normal operation and when the device is powered off. To further extend CC's ESD level for covering complicated application environments, additional ESD diodes can be added on CC. Figure 11: Recommended CC Pins ESD Enhancing PCB Layout Guidelines (10) Efficient PCB layout is critical for stable operation and thermal dissipation. For best results, refer to Figure 12 and follow the guidelines below. 1. Use short, direct, and wide traces to connect OUT. 2. Add vias under the IC. 3. Route the OUT trace on both PCB layers. 4. Place the buck output ceramic capacitor C2A and C2B on the left side and C2C on the right side. 5. Add a large copper plane for PGND. 6. Add multiple vias to improve thermal dissipation. 7. Connect AGND to PGND. 8. Place a large copper plane for SW, USB, and USB2. 9. Route the USB1 and USB2 traces on both PCB layers. 10. Add multiple vias. 11. Place two ceramic input decoupling capacitors as close to IN and PGND as possible to improve EMI performance. 12. Place the symmetric C IN capacitors on each side of the IC. 13. Place the BST capacitor close to BST and SW. 14. Place the VCC decoupling capacitor as close to VCC as possible. NOTE: 10) The recommended layout is based on the Typical Application Circuits in Figure 13 to Figure 15.
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 MPQ4487 Rev.1.0 www.MonolithicPower.com 22 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. USB1 GND VOUT VIN USB2 C2C Place C2C at the right side Top Layer SW GND VIN Middle Layer 1 GND Middle Layer 2 USB1 GND VIN USB2 Bottom Layer Figure 12: Recommended Layout
MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100 NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4487 Rev.1.0 www.MonolithicPower.com 24 10/17/2017 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
PACKAGE INFORMATION
QFN-26 (5mmx5mm)