MPQ4480

MPQ4480 MPSIND | Alldatasheet

Document overview

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Technical content

MPQ4480 6A, 36V, Step-Down Converter for Automotive, AEC-Q100 Qualified MPQ4480 Rev. 1.0 www.MonolithicPower.com 1 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

DESCRIPTION

The MPQ4480 is a high-frequency, synchronous rectified, step-down, switch-mode converter. It achieves 6A output current over a wide input-supply range with excellent load and line regulation over a wide input supply range. The MPQ4480 has synchronous mode operation for higher efficiency over the output load range. Fault condition protection includes hiccup current limiting, OVP, and thermal shutdown (TSD). The MPQ4480 requires a minimal number of readily available, standard external components. The MPQ4480 is available in a QFN-25 (4mmx5mm) package.

FEATURES

 4.2V to 36V Operating Input Voltage Range  6A Output Current  Internal Auto EN Pull-Up  20mΩ/15mΩ Low RDS(ON) Internal Buck Power MOSFETs  Integrated 4mΩ Ground Sensing Resistor  Frequency Adjustable (235kHz to 2.2MHz)  CC Output Current Limit, 3-Level Adjustable, 2.75A/3.75A/7.5A  Forced PWM Mode  Frequency SYNC from 300kHz to 2.1MHz  (Recommend: <25% of SYNC Duty Cycle)  Spread Spectrum Option with 450kHz fSW  EN Shutdown Discharge  Low Dropout Mode  Battery Short to Ground Protect Driver  Output Over-Voltage Protection  Adjustable Line Drop Compensation  Support 1V to 20V Output Adjustable  Available in a QFN-25 (4mmx5mm) Package with Wettable Flanks  Available in AEC-Q100 Grade 1

APPLICATIONS

 Automotive Infotainment System  Automotive USB Hub  Wireless Charging All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are registered trademarks o f Monolithic Power Systems, Inc. or its subsidiaries.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 2 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL APPLICATION PGND EN IN AGND SW FB VIN 12V 4.7µH VCC BST C4 22 0nF C2A 10µF+ C1 100µF C1A 22µF ILIM RGNDFREQ/SYNC GATE VDROP USB_GND 1µF VOUT MPQ4480 10 0µF Polymer Cap NC VOUT = 1V to VIN * Dmax (ESR < 50mΩ) Efficiency vs. Output Current VOUT = 5V, fSW = 440kHz, L = 4.7µH, DCR = 7mΩ 100 01234567 EFFICI ENCY (%) OUTPUT CURRENT (A) Vin=6V Vin=12V Vin=36V

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 3 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MPQ4480GV-AEC1* QFN-25 (4mmx5mm) See Below MPQ4480GV-FD-AEC1** QFN-25 (4mmx5mm) See Below * For Tape & Reel, add suffix –Z (e.g. MPQ4480GV-AEC1–Z) ** For Tape & Reel, add suffix –Z (e.g. MPQ4480GV-FD-AEC1-Z) DEVICE COMPARISON INFORMATION Part Number Frequency Spread Spectrum MPQ4480GV-AEC1 No MPQ4480GV-FD-AEC1 Yes TOP MARKING MPS: MPS prefix Y: Year code WW: Week code MP4480: Part number LLLLLL: Lot number PACKAGE REFERENCE TOP VIEW QFN-25 (4mmx5mm)

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 4 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1, 5, 13, 17 PGND Power ground. Reference ground of the regulated output voltage. PGND requires extra care during PCB layout. Connect to GND with copper traces and vias. All PGND pins must be connected together. 2, 16 RGND Remote power ground. There is an internal 4m Ω current-sensing resistor from RGND to PGND (pin 17 and pin 1). 3,15 IN Supply voltage. The MPQ4480 operates from a 4.2V to 36V input voltage. C IN prevents large voltage spikes at the input. Place C IN as close to the IC as possible. IN is the drain of the internal power device, and provides the power supply for the entire chip. 4, 8, 9, 14 SW Switch output. These pins must be connected together by a PCB trace. Use a wide PCB trace to make the connection. 6 AGND Analog ground. Connect AGND to PGND. 7 VCC Internal 5.05V LDO regulator output. Decouple with a 1µF capacitor. 10 BST Bootstrap. A 0.22µF capacitor is connected between SW and BST to form a floating supply across the high-side switch driver. 11 EN On/off control input. The enable pin is an inte rnal auto pull-up with a 7 µA current source. EN has two stage thresholds: when EN is higher than ~1V, the VCC and bias circuitry will be enabled; when EN is higher than 2V, the buck switcher starts to work.

12 FREQ/SYNC

Switching frequency program input. Connect a resistor from FREQ to GND to set the switching frequency. This pin also serves as a frequency-synchronous clock input. 18, 19, 20, 21 NC No connection. These pins should be left floating. 22 VDROP Line drop amplitude selection. Three levels can be programmable by pulling VDROP to GND or VCC, or floating. 23 ILIM Output CC current limit set pin. Pull ILIM to VCC, GND, or float to set three different current limit levels.

24 GATE

Gate drive for external, low-side, N-channel power MOSFET. Open-drain structure. The GATE pin is pulled low to turn off the power MOSFET when the secondary current RGND-to-PGND limit is triggered. 25 FB Feedback. Connect to the tap of an external resistor divider from the output to GND to set the output voltage.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 5 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) -0.3V (-5V for <10ns) to V IN + 0.3V (43V for <10ns) V Continuous power dissipation (TA = 25°C) (3) (5) Recommended Operating Conditions (4) Operating junction temp…….. .. -40°C to +125°C Thermal Resistance θJA θJC QFN-25 (4mmx5mm) Notes: 1) Exceeding these ratings may damage the device. 2) About the details of EN pin’s ABS Max rating, see the EN control section on page 14. 3) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - T A) / θJA. Exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on EVQ4480-V-00A, 4-layer PCB, 50mmx50mm. 6) Measured on JESD51-7, 4-layer PCB. The value of θ JA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51-7 and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 6 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 12V, VEN = 5V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Supply current (shutdown) I IN V EN = 0V, TJ = -40°C to +125°C 15 25 μA Supply current (quiescent) I Q2 No switching 1 2 mA EN rising threshold V EN_Rising 1.96 2.06 2.16 V EN hysteresis V EN_HYS 200 mV EN pull-up current I EN V EN = 3V 3 7 11 μA Thermal shutdown (7) T STD 165 C Thermal hysteresis (7) T STD_HYS 20 C VCC regulator V CC 4.65 5.05 5.45 V VCC load regulation V CC_LOG I CC = 50mA 1 3 % Step-Down Converter VIN under-voltage lockout threshold rising VIN_UVLO 3.7 3.95 4.2 V VIN under-voltage lockout threshold hysteresis VUVLO_HYS 500 mV HS switch on resistance R DSON_HS 20 40 m Ω LS switch on resistance R DSON_LS 15 35 m Ω Feedback voltage V FB 0.985 1 1.015 V Low-side current limit (7) I LS_LIMIT -2 A Switch leakage SW LKG VEN = 0V, VSW = 36V, TJ = 25°C 1 μA VEN = 0V, VSW = 36V, TJ = -40°C to +125°C 5 High-side current limit I LIMIT1 ILIM = GND 8 17 27 A ILIM = VCC 12 22 35 Output CC current limit I LIMIT2 ILIM = VCC (for 6A continuous), TJ = 25°C 6.6 7.5 8.4 A ILIM = float (for 3A continuous), TJ = 25°C 3.3 3.75 4.2 ILIM = GND (for 2.4A continuous), TJ = 25°C 2.5 2.75 3 Oscillator frequency fSW1 R FREQ = 97.6kΩ 170 235 300 kHzfSW2 R FREQ = 9.53kΩ 1800 2200 2600 fSW3 R FREQ = 52.3kΩ 350 440 530 Frequency spread spectrum (7) (MPQ4480GV-FD-AEC1) fSS R FREQ = float, based on 450kHz 10 % Sync frequency range FREQ SYNC_IN 300 2100 kHz Maximum on time t ON_MAX Dropout mode, max duty cycle DMAX = tON_MAX / (tON_MAX + tOFF_MIN) 6 10 μs Minimum off time t OFF_MIN 120 ns Minimum on time (7) tON_MIN 130 ns

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 7 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VEN = 5V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted. Soft-start time t SS 10% to 90% V OUT 0.4 1.1 1.8 ms Line drop compensation gain (from IRTN to IFB) Gain1 VDROP pin = GND, T J = 25°C 0.1 0.6 1.1 μA/A Gain2 VDROP pin = float, T J = 25°C 1.5 3.25 5 μA/A Gain3 VDROP pin = VCC, T J = 25°C 4 6.75 9.5 μA/A OVP OVP rising threshold VOVP1_RISE 110% 115% 120% V REF OVP falling threshold V OVP_FALL 105% V REF OVP delay (7) t OVPDEL 2 μs RGND Current Limit RGND to PGND resistor R SENSE 4 12 m Ω Second current limit threshold VSENSE_TH 12 A GATE pull-low resistance R GATE_L 85 180 Ω Second current limit off time t EXT_CUR_RES 1 2 3 s Note: 7) Guaranteed by engineering sample characterization.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 8 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 440kHz, TA = 25°C, unless otherwise noted. Efficiency vs. Output Current VOUT = 5V, fSW = 440kHz, L = 4.7µH Efficiency vs. Output Current VOUT = 5V, fSW = 2.2MHz, L = 2.2µH 100 01234567 EFFICI ENC Y (%) OUTPUT CURRENT (A) Vin=6V Vin=12V Vin=36V 100 01234567 EFFICI ENC Y (%) OUTPUT CURRENT (A) Vin=6V Vin=12V Vin=36V Line Drop Compensation R1 = 40.2kΩ Case Temperature Rise vs. IOUT 4-layers, 5cmx5cm 200 400 600 800 1000 1200 1400 1600 1800 2000 0246 LINE DROP COMPENSATION (mV) OUTPUT CURRENT (A) VDROP=GND VDROP=Float VDROP=VCC 02468 CASE TEMPERATURE RISE (°C ) OUTPUT CURRENT (A)

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 9 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 440kHz, TA = 25°C, unless otherwise noted. All waveforms are tested based on bypassing the external MOSFET except Short Battery to Ground. Output Ripple fSW = 440kHz, L = 4.7µH, IOUT = 0A Output Ripple fSW = 440kHz, L = 4.7µH, IOUT = 6A CH1: VOUT/AC 50mV/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT/AC 50mV/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 5A/div. 2µs/div. 2µs/div. Output Ripple fSW = 2.2MHz, L = 2.2µH, IOUT = 0A Output Ripple fSW = 2.2MHz, L = 2.2µH, IOUT = 6A CH1: VOUT/AC 50mV/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT/AC 50mV/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 5A/div. 1µs/div. 1µs/div. Power Start-Up IOUT = 0A Power Start-Up IOUT = 6A CH1: VOUT 5V/div. CH2: VIN 5V/div. CH3: VSW 10V/div. CH4: IL 2A/div. CH1: VOUT 5V/div. CH2: VIN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. 5ms/div. 5ms/div.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 10 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 440kHz, TA = 25°C, unless otherwise noted. All waveforms are tested based on bypassing the external MOSFET except Short Battery to Ground. Power Shutdown IOUT = 0A Power Shutdown IOUT = 6A CH1: VOUT 2V/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH3: VSW 10V/div. CH2: VIN 10V/div. CH4: IL 5A/div. 20ms/div. 10ms/div. EN Start-Up IOUT = 0A EN Start-Up IOUT = 6A CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: VSW 10V/div.CH 4: IL 5A/div. 1ms/div. 1ms/div. EN Shutdown IOUT = 0A EN Shutdown IOUT = 6A CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. 1ms/div. 1ms/div.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 11 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 440kHz, TA = 25°C, unless otherwise noted. All waveforms are tested based on bypassing the external MOSFET except Short Battery to Ground. VOUT Short to USB_GND Entry IOUT = 0A VOUT Short to USB_GND Steady State IOUT = 0A CH1: VOUT 5V/div. CH2: VGATE 5V/div. CH3: VSW 10V/div. CH4: IL 10A/div. CH1: VOUT 5V/div. CH2: VGATE 5V/div. CH3: VSW 10V/div. CH4: IL 10A/div. 20µs/div. 1s/div. VOUT Short to USB_GND Recovery IOUT = 0A USB_GND Short to Battery Entry and Recovery IOUT = 0A CH1: VOUT 5V/div. CH2: VGATE 5V/div. CH3: VSW 10V/div. CH4: IL 10A/div. CH1: VOUT- USB_GND 5V/div. CH2: VGATE 5V/div. CH3: VSW 10V/div. CH4: ISHORT 20A/div. 1ms/div. 500ms/div. Sync Function fSW = 300kHz, L = 4.7µH, IOUT = 6A Sync Function fSW = 2.1MHz, L = 2.2µH, IOUT = 6A CH1: VOUT 2V/div. CH2: VSYNC 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH2: VSYNC 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. 5μs/div. 1μs/div.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 12 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 440kHz, TA = 25°C, unless otherwise noted. All waveforms are tested based on bypassing the external MOSFET except Short Battery to Ground. CC Mode Over-Current Protection Steady State Low Dropout Mode VIN = 5V, VOUT = 4.93V, IOUT = 0A CH1: VOUT 2V/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH2: VIN 2V/div. CH3: VSW 2V/div. CH4: IL 200mA/div. 5μs/div. 20μs/div. Load Transient IOUT = 0 to 3A, 2.5A/µs, VDROP = GND, line drop compensation = 73mV @ 3A CH1: VOUT/AC 200mV/div. CH3: VSW 10V/div. CH4: IOUT 2A/div. 200μs/div.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 13 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM Σ Bootstrap Regulator HS Driver LS Driver VCCControl Logic Oscillator VCC Regulator Reference IN EN VCC AGND BST Current Sense Amplifier Current Limit Comparator PWM Comparator Error Amplifier SW PGND FREQ/SYNC SS FB ILIM GATEPGND RGND VCC USB_GND CC Current Limit >12A, Turn On Q3 for 2s, Restart K VDROP NCRSE NSE 4mΩ Figure 1: Functional Block Diagram

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 15 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. Frequency Spread Spectrum The MPQ4480-FD is the switching frequency spread spectrum version of the MPQ4480. The purpose of spread spectrum is to minimize the peak emissions at a specific frequency. The MPQ4480-FD uses a 4kHz triangle wave (rising 125µs, falling 125µs) to modulate the internal oscillator (see Figure 4). The frequency span of spread spectrum operation is ±10%. t250μs fSW = 450kHz fSW = 495kHz fSW = 405kHz Fundamental Frequency Figure 4: Frequency Spread Spectrum The MPQ4480-FD frequency is only determined by internal trimming. It has no relationship with the FREQ pin’s status. Frequency Synchronizing The MPQ4480 can be synchronized to an external clock with a range from 300kHz to 2.1MHz through the SYNC pin, in series with a 10pF capacitor. The internal clock rising edge is synchronized to the external clock rising edge. A typical SYNC input signal should have a <25% duty cycle. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The UVLO comparator monitors the input voltage. The UVLO rising threshold is 3.95V; its falling threshold is 3.45V. Internal Soft Start (SS) The soft start (SS) prevents the converter output voltage from overshooting during start- up. When the chip starts up, the internal circuitry generates a SS voltage that ramps up from 0V to 5.05V. When V SS is lower than V REF, the error amplifier uses V SS as the reference. When V SS is higher than V REF, the error amplifier uses V REF as the reference. The SS time is internally set to 1.1ms. If the output of the MPQ4480 is pre-biased to a certain voltage during start-up, the IC disables the switching of both the high-side and low-side switches until the voltage on the internal SS capacitor exceeds the internal feedback voltage. EN Shutdown Discharge When EN is pulled low, the MPQ4480 enters output discharge mode. Meanwhile, the internal soft-start capacitor starts to discharge. The part remains in discharge mode until the soft-start capacitor discharges to very low. In this mode, the low-side switch remains on until the low-side current reaches -2A, then turns on again after a clock cycle. CC Mode Over-Current Protection The MPQ4480 senses the ground current and uses this information to limit output current below a certain threshold. If I OUT exceeds the set current-limit threshold, the MPQ4480 enters constant current limit mode (CC mode). In this mode, the current amplitude is limited. As the load resistance reduces, the output voltage drops until the feedback voltage falls below the under-voltage (UV) threshold (typically 30% below the reference). Once UV triggers, the MPQ4480 enters hiccup mode to periodically restart the part. This protection mode is especially useful when the output is dead-shorted to ground. This greatly reduces the average short-circuit current, alleviates thermal issues, and protects the regulator. The MPQ4480 exits hiccup mode once the over-current condition is removed. In addition to the ground current limit, the MPQ4480 also has a high-side peak current limit. Pulling the ILIM pin to GND, to VCC, or floating it can set three different CC current-limit thresholds. Over-Voltage Protection (OVP) The MPQ4480 monitors a resistor-divided feedback voltage to detect over-voltage. When the feedback voltage (V FB) exceeds 115% of the target voltage, the controller enters a dynamic regulation period. During this period, the LS- FET remains on until its current goes to -2A. This discharges the output and tries to keep it within the normal range. If the OV still exists, the LS-FET turns on again after an 800ns delay. The part exits this regulation period when V FB

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 17 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. When the silicon die temperature exceeds 165°C, it shuts down the entire chip. When the temperature falls below its lower threshold (typically 145°C), the chip is enabled.

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED MPQ4480 Rev. 1.0 www.MonolithicPower.com 19 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. For an electrolytic capacitor, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be estimated with Equation (11): OUT OUT OUT ESR INSW 1 VV∆V1 R fL V (11) For polymer capacitor designs, the ESR of output capacitor should be less than 50mΩ. PCB Layout Guidelines (8) Proper PCB layout is critical for efficient operation and thermal dissipation. For best results, refer to Figure 8 and follow the guidelines below: 1. Place the high-current paths (GND, IN, and SW) very close to the device with short, direct, and wide traces. 2. Use a large copper plane for PGND. Add multiple vias to improve thermal dissipation. 3. Connect AGND to PGND. 4. Ensure that FB is far from SW to avoid noise. 5. To improve EMI performance, place two ceramic input decoupling capacitors as close as possible to IN and PGND. 6. Place the VCC decoupling capacitor as close as possible to VCC. Note: 8) The recommended layout is based on the Typical Application Circuits on page 19. Top Layer Middle Layer 1 Middle Layer 2 Bottom Layer Figure 8: Recommend Layout VIN PGND USB_GND PGND PGND SW VOUT PGND USB_GND PGND PGND

MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED NOTICE: The information in this document is subject to change wi thout notice. Users should warrant and guarantee that third- party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4480 Rev. 1.0 www.MonolithicPower.com 22 7/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-25 (4mm x 5mm) SECTION A-A RECOMMENDED LAND PATTERN PIN 1 ID INDEX AREA TOP VIEW PIN 1 ID MARKING BOTTOM VIEW SIDE VIEW NOTE: THE LEAD SIDE IS WETTABLE. 2) LAND PATTERNS OF PIN1~5 AND 13~17 HAVE THE SAME LENGTH AND WIDTH. 3) ALL DIMENSIONS ARE IN MILLIMETERS. 4) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-220. 6) DRAWING IS NOT TO SCALE.