MPQ4430 MPS | Alldatasheet
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Technical content
36V, 3.5A, Low Quiescent Current, Synchronous, Step-Down Converter AEC-Q100 Qualified MPQ4430 Rev. 1.0 www.MonolithicPower.com 1 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
DESCRIPTION
The MPQ4430 is a frequency -programmable (350kHz to 2.5MHz), synchronous, step-down, switching regulator with integrated internal high- side and low-side power MOSFETs. It provides up to 3.5A of highly efficient output current with current mode control for fast loop response. The wide 3.3V to 36V input range accommodates a variety of step-down applications in automotive input environment s and is i deal for battery - powered applications due to its extremely low quiescent current. The MPQ4430 employs advanced asynchronous mod e (AAM), which helps achieve high efficiency in light-load condition by scaling down the switching frequency to reduce switching and gate driving losses. Standard features include sof t start (SS), external clock synchronization, enable (EN) control, and a power good (PG) indicator. High- duty cycle and low drop out mode are provided for automotive cold-crank condition. Over-current protection (OCP) with valley - current detection is employed to prevent the inductor current from running away . Hiccup mode reduces the average current in short - circuit condition greatly. Thermal shutdown provides reliable and fault-tolerant operation. The MPQ4430 is available in a QFN-16 (3mmx4mm) package.
FEATURES
Wide 3.3V to 36V Operating Input Range 3.5A Continuous Output Current 1μA Low Shutdown Mode Current 10μA Sleep Mode Quiescent Current Internal 90mΩ High-Side and 40mΩ Low- Side MOSFETs 350kHz to 2.5MHz Programmable Switching Frequency Fixed Output Options: 3.3V, 3.8V, 5V Synchronize to External Clock Selectable In-Phase or 180° Out-of-Phase Power Good (PG) Indicator Programmable Soft-Start (SS) Time 80ns Minimum On Time Selectable Forced CCM or AAM Low Dropout Mode Over-Current Protection (OCP) with Valley- Current Detection and Hiccup Available in a QFN-16 (3mmx4mm) Package Available with Wettable Flank AEC-Q100 Grade 1
APPLICATIONS
Automotive Systems Industrial Power Systems All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MPQ4430 VIN EN VIN FREQ FB BST VOUT SW GND PHASE VCC BIAS PG SS 3.3 to 36V SYNC
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 2 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking MPQ4430GL QFN-16 (3mmx4mm) See Below MPQ4430GL-AEC1 QFN-16 (3mmx4mm) See Below MPQ4430GLE-AEC1*** QFN-16 (3mmx4mm) See Below * For Tape & Reel, add suffix –Z (e.g. MPQ4430GL–Z) Under qualification * Under qualification, wettable flank TOP MARKING ( MPQ4430GL & MPQ4430GL-AEC1) MP: MPS prefix Y: Year code W: Week code 4430: First four digits of the part number LLL: Lot number TOP MARKING (MPQ4430GLE-AEC1) MP: MPS prefix Y: Year code W: Week code 4430: First four digits of the part number LLL: Lot number E: Wettable lead flank
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 3 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW PHASE VIN SW 4PGND 13141516 AGNDSSFBFREQ 5 6 7 8 EN SYNC PG BIAS PGND SW BST VCC QFN-16 (3mmx4mm) ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25°C) (2) Recommended Operating Conditions Operating junction temp. (TJ) ... -40°C to +125°C Thermal Resistance (3) θJA θJC NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction tempe rature T J(MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)- TA)/ θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Measured on JESD51-7, 4-layer PCB.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 4 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted. Typical values at TJ = +25°C. Parameter Symbol Condition Min Typ Max Units VIN quiescent current IQ VFB = 0.85V, no load, no switching, TJ = +25°C 10 18 µA VFB = 0.85V, no load, no switching 10 25 VIN shutdown current ISHDN VEN = 0V 1 5 µA VIN under-voltage lockout threshold rising INUVRISING 2.4 2.8 3.2 V VIN under-voltage lockout threshold hysteresis INUVHYS 150 mV Feedback reference voltage VREF 784 800 816 mV TJ = 25°C 792 800 808 mV Switching frequency FSW RFREQ = 180kΩ or from sync clock 400 475 550 kHz RFREQ = 82kΩ or from sync clock 850 1000 1150 kHz RFREQ = 27kΩ or from sync clock 2250 2500 2750 kHz Minimum on time (4) TON_MIN 80 ns SYNC input low voltage VSYNC_LOW 0.4 V SYNC input high voltage VSYNC_HIGH 1.8 V Current limit ILIMIT_HS Duty cycle = 40% 4.7 5.8 7.3 A ZCD current IZCD 0.1 A Reverse current limit ILIMIT_REVERSE 3 A Switch leakage current ISW_LKG 0.01 1 µA HS switch on resistance RON_HS VBST - VSW = 5V 90 155 mΩ LS switch on resistance RON_LS 40 75 mΩ Soft-start current ISS VSS = 0.8V 5 10 15 µA EN rising threshold VEN_RISING 0.9 1.05 1.2 V EN threshold hysteresis VEN_HYS 120 mV PG rising threshold (VFB/VREF) PGRISING VFB rising 85 90 95 % VFB falling 105 110 115 PG falling threshold (VFB/VREF) PGFALLING VFB falling 79 84 89 % VFB rising 113.5 118.5 123.5 % PG deglitch timer TPG_DEGLITCH PG from low to high 30 µs PG from high to low 50 µs PG output voltage low VPG_LOW ISINK = 2mA 0.2 0.4 V VCC regulator VCC 5 V VCC load regulation ICC = 5mA 3 % Thermal shutdown (4) TSD 170 C Thermal shutdown hysteresis (4) TSD_HYS 20 °C NOTE: 4) Not tested in production and guaranteed by design and characterization.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 5 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 6 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 7 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 8 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 9 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 10 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 11 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 12 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 13 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 14 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 15 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 PHASE Selectable in-phase or 180° out-of-phase of SYNC input. Drive PHASE high to be in-phase. Drive PHASE low to be 180° out-of-phase.
2 VIN
Input supply. VIN supplies power to all of the internal control circuitr ies and the power switch connected to SW. A decoupling capacitor to ground must b e placed close to VIN to minimize switching spikes. 3, 10 SW Switch node. SW is the output of the internal power switch. 4, 9 PGND Power ground. PGND is the reference ground of the power device and requires careful consideration during PCB layout. For be st results, connect PGND with copper pours and vias. 5 EN Enable. Pull EN below the specified threshold to shut the chip down. Pull EN above the specified threshold to enable the chip.
6 SYNC
Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the internal oscillator frequency to the external clock. The external clock should be at least 250kHz larger than the RFREQ set frequency. SYNC can also be used to select forced continuous conduction mode (CCM) or advanced asynchronous mode ( AAM). Drive SYNC high before the chip starts up to choose forced CCM. Drive SYNC low or leave SYNC floating to choose AAM. 7 PG Power good indicator. The output of PG is an open drain and goes high if the output voltage is within ±10% of the nominal voltage.
8 BIAS
External power supply for the internal regulator. Connect BIAS to an external power supply (5V ≤ VBIAS ≤ 18V) to reduce power dissipation and increase efficiency. Float BIAS or connect BIAS to ground if not used. 11 BST Bootstrap. BST is the positive power supply of the high-side MOSFET driver connected to SW. Connect a bypass capacitor between BST and SW. 12 VCC Internal b ias supply. VCC supplies power to the internal control circuit and gate drivers. A ≥1µF decoupling capacitor to ground is required close to VCC. 13 AGND Analog ground. AGND is the reference ground of the logic circuit. 14 SS Soft-start input. Place an external capacitor from SS to AGND to set the soft -start period. The MPQ4430 sources 10µA from SS to the soft -start capacitor during start- up. As the SS voltage rises, the feedback threshold voltage increases to limit inrush current during start-up. 15 FB Feedback input. Connect FB to the tap of an external resistor divider from the output to AGND to set the output voltage. The feedback threshold voltage is 0.8V . Place the resistor divider as close to FB as possible. Avoid placing vias on the FB traces. 16 FREQ Switching frequency program. Connect a resistor from FREQ to ground to set the switching frequency.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 16 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. BLOCK DIAGRAM Oscillator PLL Reference Error Amplifier Control Logic, OCP, OTP, BST Refresh FB PGND SW BST VIN EN PG 90%xVREF ISW SS Vref VCCVFB VFB VCC VCC VCC Regulator Ireverse BIAS FREQ SYNC PHASE AGND VC 460kΩ 52pF 0.2pF VCC VREF VFB 110%xVREF Logic Figure 1: Functional Block Diagram
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 17 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TIMING SEQUENCE VIN VCC T h r e s h o l d E N V o P G S W VCC E N T h r e s h o l d S S 3 0 µ s 3 0 µ s Start-Up OCP OC Release 50% R E F O V I L I L = I L i m i t 118.5% Vref 5 0 µ s N o r m a l N o r m a l N o r m a l EN Shutdown 90% Vref 50 µs 110% Vref 3 0 µ s 84% Vref Figure 2: Time Sequence
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 19 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Error Amplifier (EA) The error amplifier compares VFB with VREF and outputs a current proportional to the difference between the two. This output current then charges or discharges the internal compensation network to form VCOMP, which controls the power MOSFET current. The optimized internal compensation network minimizes the external component count and simplifies the control loop design. Internal Regulator and BIAS Most of the internal circuitry is powered on by the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN exceeds 5V, the output of the regulator is in full regulation . When VIN falls below 5V, the ou tput decreases following VIN. A decoupling ceramic capacitor is needed close to VCC. For better thermal performance, connect BIAS to an external power supply between 5V and 18V. The BIAS supply overrides VIN to power the internal regulato r. Using the BIAS supply allows VCC to be derived from a high -efficiency external source, such as VOUT. Float BIAS or connect BIAS to ground if not used. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 2.8V with a 150mV hysteresis. Enable Control (EN) EN is a digital control pin that turns the regulator on and off. When EN is pulled below its threshold voltage, the chip is put into the lowest shutdown current mode. Pulling EN above its threshold voltage turns on the part. Do not float EN. Power Good Indicator (PG) The MPQ4430 has a power good (PG) indicator. PG is the open drain of a MOSFET and should be connected to VCC or another voltage source through a resistor (e.g. : 100kΩ). In the presence of an input voltage, the MOSFET turns on so that PG is pulled low before SS is ready. When the regulator output is within ±10% of its nominal output , the PG output is pulled high after a delay, typically 30μs. When the outp ut voltage moves outside of this range with a hysteresis, the PG output is pulled low with a 50μs delay to indicate a failure output status. Programmable Frequency The oscillating frequency of the MPQ4430 can be programmed either by an external frequency resistor (RFREQ) or by a logic level synchronous clock. The frequency resistor should be located between FREQ and ground as close as to the device as possible. The value of RFREQ can be estimated with Equation (1): FREQ 1.11 SW 170000R (k Ω) f (kHz) (1) The calculated resistance may need fine -tuning during the bench test. FREQ is not allowed to be floated even if an external SYNC clock is added. SYNC and PHASE The internal oscillator frequency can be synchronized to an external clock ranging from 350kHz up to 2. 5MHz through SYNC. The external clock should be at least 25 0kHz larger than the RFREQ set frequency. Ensure that the high amplitude of the SYNC clock is higher than 1.8V, and the low amplitude is lower than 0.4V. There is no pulse width requirement , but there is always parasitic capacitance of the pad , so if the pulse width is too short, a clear rising and falling edge may not be seen due to the parasitic capac itance. A pulse longer than 100ns is recommended in application. PHASE is used when two or more MPQ4430 devices are in parallel with the same SYNC clock. Pulling PHASE high forces the device to operate in -phase of the SYNC clock. Pulling i t low forces the device to be 180° out-of-phase of the SYNC clock. By setting different voltage s for PHASE, two devices can operate 180° out- of-phase to reduce the total input current ripple so a smaller input bypass capacitor can be used (see Figure 4) . The PHASE rising threshold is about 2.5V with a 400mV hysteresis.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 20 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. SYNC CLK SW1 SW2 t SW1, 2 has a 180o phase shift SW1: Phase high SW2: Phase low Figure 4: In-Phase and 180° Out-of-Phase Soft Start (SS) Soft start (SS) is implemented to prevent the converter output voltage fro m overshooting during start -up. When the chip starts up, an internal current source begins charging the external soft-start capacitor. When the soft-start voltage ( VSS) is lower than the internal reference ( VREF), VSS overrides VREF, so the error amplifier uses VSS as the reference. When VSS is higher than VREF, the error amplifier uses VREF as the reference. The soft-start time (t SS) set by the external SS capacitor can be calculated with Equation (2): SS REF SS SS C (nF) V (V)t (ms) I ( A) (2) Where CSS is the external SS capacitor, V REF is 0.8V, and I SS is the internal 10μA SS charge current. SS can be used for tracking and sequencing. Pre-Bias Start-Up At start -up, if VFB is higher than V SS, which means the output has a pre-bias voltage , neither the HS-FET nor the LS-FET are turned on until VSS is higher than VFB. Over-Current Protection (OCP) and Hiccup The MPQ4430 has cycle-by-cycle peak current- limit protection with valley-current detection and hiccup mode. The power MOSFET current is accurately sensed via a current sense MOSFET. It is then fed to t he high -speed current comparator for current-mode control purpose s. During the HS - FET on state, if the sensed current exceeds the peak-current limit value set by the COMP high - clamp voltage, the HS -FET turns off immediately. Then the LS -FET turns o n to discharge the energy, and the inductor current decreases. The HS-FET remains off unless the inductor valley current is lower than a certain current threshold (the valley current limit), even though the internal clock pulses high. If the inductor current does not drop below the valley current limit when the internal clock pulses high, the HS-FET misses the clock, and the switching frequency decreases to half the nominal value. Both the peak and valley current limits assist in keeping the inductor curr ent from running away during an overload or short-circuit condition. When the output is shorted to ground, causing the output voltage to drop below 55% of its nominal output, the peak current limit is kicked, and the device considers this to be an output dead short and trigger s hiccup mode immediately to restart the part periodically. In hiccup mode , the MPQ4430 disables its output power stage and discharges the soft - start capacitor slowly. The MPQ4430 restarts with a full soft-start when the soft-start capacitor is fully discharged. If the short -circuit condition still remains after the soft start ends, the device repeats this operation until the fault is removed and output returns to the regulati on level. This protection mode reduces the average short circuit current greatly to alleviate thermal issues and protect the regulator. Floating Driver and Bootstrap Charging A 0.1μF to 1μF external bootstrap capacitor powers the floating power MOSFET driver. The floating driver has its own UVLO protection with a rising threshold of 2.5V and hysteresis of 200mV. The bootstrap capacitor voltage is charged to ~5V from VCC through a P MOS pass transistor when the LS-FET is on. At a high duty cycle operation or sleep mode condition, the time period available to the bootstrap charging is less , so the bootstrap capacitor may not be charged sufficiently. In case the external circuit does not have sufficient voltage or time to charge the bootstrap capacitor, extra external circuitry can be used to ensure that the bootstrap voltage is in the normal operation region.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 21 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. BST Refresh To improve drop out, the MPQ4430 is designed to operate at close to 100% duty cycle for as long as the B ST to SW voltage is greater than 2.5V. When the voltage from BST to SW drops below 2. 5V, the HS-FET is turned off using a UVLO circuit , which forces the LS-FET on to refresh the charge on the BST capacitor. Since the supply current sourced from the BST capacitor is low, the HS-FET can remain on for more switching cycles than are required to refresh the capacitor, making the effective duty cycle of the switching regulator high. The effective duty cycle during the dropout of the regulator is mainly influenced by the voltage drops across the HS-FET, LS -FET, inductor resistance, and printed circuit board resistance. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from running away thermally. When the silicon die temperature exceeds its upper threshold, the power MOSFETs shut down . When the temperature drops below its lower threshold, the chip is enabled again. Start-Up and Shutdown If both VIN and E N exceed their appropriate thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current , and then the internal regulator is enabled. The regulator provides a stable supply for the rest of the circuitries. While the internal supply rail is up, an internal timer holds the power MOSFET off for about 50µs to blank start-up glitches. When the soft - start block is enabled, it first holds its SS output low to ensure that the rest of the circuitries are ready and slowly ramps up. Three events can shut down the chip: VIN low, EN low, and thermal shutdown. During the shutdown p rocedure, the signaling path is blocked first to avoid any fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command , but its charging path is disabled.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 22 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltage The external resistor divider connected to FB sets the output voltage (see Figure 5). RFB1 VoutFB MPQ4430 RFB2 Figure 5: Feedback Network Choose RFB1 to be around 40kΩ. Then calculate RFB2 with Equation (3): 10.8V V RR OUT FB1 FB2 (3) Table 1 lists the recommended feedback resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) RFB1 (kΩ) RFB2 (kΩ) Selecting the Input Capacitor The input curr ent to the step -down converter is discontinuous and therefore requires a capacitor to supply AC current to the converter while maintaining the DC input voltage. For the best performance, use low ESR capacitors. Ceramic capacitors with X5R or X7R dielect rics are highly recommended because of their low ESR and small temperature coefficients. For most application s, use a 4.7µF to 10µF capacitor. It is strongly recommended to use another lower-value capacitor (e.g.: 0.1µF) with a small package size (060 3) to absorb high - frequency switching noise. Place the small er capacitor as close to VIN and GND as possible. Since CIN absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input c apacitor can be estimated with Equation (4): OUT OUT CIN LOAD IN IN VVI I (1 ) VV (4) The wors t-case condition occurs at VIN = 2VOUT, shown in Equation (5): LOAD CIN II 2 (5) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high -quality ceramic capacitor (e.g. : 0.1μF) as close to t he IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at the input. The input voltage ripple caused by the capacitance can be estimated with Equation (6): LOAD OUT OUT IN SW IN IN IN I V VV (1 )f C V V (6) Selecting the Output Capacitor The output capacitor maintains the DC output voltage. Use ceramic, tantalum, or low -ESR electrolytic capacitors. For best results, use low ESR capacitors to keep the output voltage ripple low. The output voltage ripple can be estimated with Equation (7): OUT OUT OUT ESR SW IN SW OUT VV 1V (1 ) (R )f L V 8f C (7) Where L is the inductor value , and RESR is the equivalent series resistance (ESR) value of the output capacitor. For ceramic capacitors, the capacitanc e dominates the impedance at the switching frequency and causes the majority of the output voltage ripple.
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 24 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PCB Layout Guidelines (6) Efficient PCB layout , especially for input capacitor placement , is critical for stable operation. A four -layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 8 and follow the guidelines below. 1. Place symmetric input capacitors as close to VIN and GND as possible. 2. Use a large ground plane to connect to PGND directly. 3. Add vias near PGND if the bottom layer is a ground plane. 4. Ensure that the high-current paths at GND and VIN have short, direct, and wide traces. 5. Place the ceramic input c apacitor, especially the small package size (0603) input bypass capacitor, as close to VIN and PGND as possible to minimize high-frequency noise. 6. Keep the connection of the input capacitor and VIN as short and wide as possible. 7. Place the VCC capacit or as close to VCC and GND as possible. 8. Route SW and BST away from sensitive analog areas, such as FB. 9. Place the feedback resistors close to the chip to ensure that the trace which connects to FB is as short as possible. 10. Use multiple vias to connect the power planes to the internal layers. NOTE: 6) The recommended PCB layout is based on Figure 9. Top Layer Inner Layer 1 Inner Layer 2 Bottom Layer Figure 8: Recommended PCB Layout
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4430 Rev. 1.0 www.MonolithicPower.com 29 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
PACKAGE INFORMATION
QFN-16 (3mmx4mm) Non-Wettable Flank SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-220. 4) DRAWING IS NOT TO SCALE. TOP VIEW RECOMMENDED LAND PATTERN PIN 1 ID MARKING PIN 1 ID INDEX AREA PIN 1 ID 0.15x45°TYP. 0.15x45°
MPQ4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4430 Rev. 1.0 www.MonolithicPower.com 30 3/2/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PACKAGE INFORMATION (continued) QFN-16 (3mmx4mm) Wettable Flank SIDE VIEW BOTTOM VIEW NOTE: 1) THE LEAD SIDE IS WETTABLE. 2) ALL DIMENSIONS ARE IN MILLIMETERS. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. TOP VIEW RECOMMENDED LAND PATTERN PIN 1 ID MARKING PIN 1 ID INDEX AREA PIN 1 ID 0.15x45°TYP. 0.15x45° SECTION A-A