MPQ4415M MPS | Alldatasheet

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Technical content

1.5A, 36V, 2.2MHz, High-Efficiency, Synchronous, Step-Down Converter AEC-Q100 Qualified MPQ4415M Rev. 1.01 www.MonolithicPower.com 1 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

DESCRIPTION

The MPQ4415M is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built -in power MOSFETs. The MPQ4415M offers a very compact solution that achieves 1.5A of continuous output current with excellent load and line regulation over a wide input supply range. The MPQ4415M uses synchronous mode operation for higher efficiency over the output current load range. Current-mode operation provides fast transient response and eases loop stabilization. Full protection features include over -current protection (OCP) and thermal shutdown. The MPQ4415M requires a minimal number of readily available, standard, external components and is available in a space -saving QFN-13 (2.5mmx3mm) package.

FEATURES

 EMI Reduction Technique  Wide 4V to 36V Operating Input Range  1.5A Continuous Load Current  90mΩ/50mΩ Low RDS(ON) Internal Power MOSFETs  High-Efficiency Synchronous Mode Operation  Default 2.2MHz Switching Frequency  450kHz to 2.2MHz Frequency Sync  Forced Continuous Conduction Mode (CCM)  Internal Soft Start (SS)  Power Good (PG) Indicator  Over-Current Protection (OCP) with Valley- Current Detection and Hiccup  Thermal Shutdown  Output Adjustable from 0.8V  Available in a QFN-13 (2.5mmx3mm) Package  CISPR25 Class 5 Compliant  Available in a Wettable Flank Package  Available in AEC-Q100 Grade 1

APPLICATIONS

 Automotive  Industrial Control Systems  Medical and Imaging Equipment  Telecom Applications  Distributed Power Systems All MPS parts are lead -free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MPQ4415M PG EN/SYNC VCC BST SW FB EN/SYNC PG VOUT 4V-36V PGND AGND

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 2 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MPQ4415MGQB QFN-13 (2.5mmx3mm) See Below MPQ4415MGQB-AEC1 MPQ4415MGQBE-AEC1** See Below * For Tape & Reel, add suffix –Z (e.g. MPQ4415MGQB–Z) ** Wettable Flank TOP MARKING (MPQ4415MGQB & MPQ4415MGQB-AEC1) ANM: Product code of MPQ4415MGQB and MPQ4415MGQB-AEC1 Y: Year code WW: Week code LLL: Lot number TOP MARKING (MPQ4415MGQBE-AEC1) AXR: Product code of MPQ4415MGQBE-AEC1 Y: Year code WW: Week code LLL: Lot number

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 3 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW 4 5 6 101213 IN EN/ SYNC VCC FB PGND PG SW NC AGND IN PGND PGND BST QFN-13 (2.5mmx3mm) ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25° C) (3) Recommended Operating Conditions Operating junction temp. (TJ). .. -40°C to +125°C Thermal Resistance (4) θJA θJC NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) For details on EN/SYNC’s ABS max rating, please refer to the Enable/SYNC section on page 13. 3) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutd own. Internal thermal shutdown circuitry protects the device from permanent damage. 4) Measured on JESD51-7, 4-layer PCB.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 4 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted, typical values are at TJ = +25°C. Parameter Symbol Condition Min Typ Max Units Supply current (shutdown) ISHDN VEN = 0V 8 μA Supply current (quiescent) IQ VEN = 2V, VFB = 1V, no switching 0.6 0.8 mA HS switch on resistance RON_HS VBST-SW = 5V 90 155 mΩ LS switch on resistance RON_LS VCC = 5V 50 105 mΩ Switch leakage ISW_LKG VEN = 0V, VSW = 12V 1 μA Current limit (5) ILIMIT 20% duty cycle 2.4 4.0 6.0 A Low-side valley current limit 1.7 2.5 3.5 A Reverse current limit 1.2 A Oscillator frequency fSW VFB = 700mV 1800 2200 2600 kHz Foldback frequency during soft start (5) fFB VFB = 200mV 0.2 fSW Maximum duty cycle DMAX VFB = 700mV 85 % Minimum on time (5) τON_MIN 46 ns Synchronous frequency range fSYNC 450 2200 kHz Feedback voltage VFB TJ = +25°C 795 807 819 mV TJ = -40°C to +125°C 790 807 824 mV Feedback current IFB VFB = 820mV 10 50 nA EN/SYNC rising threshold VEN_RISING 1.1 1.45 1.8 V EN/SYNC falling threshold VEN_FALLING 0.7 1 1.3 V EN/SYNC threshold hysteresis VEN_HYS 450 mV EN/SYNC input current IEN VEN = 2V 5 10 μA VEN = 0V 0 0.2 μA EN turn off delay 3 μs VIN under-voltage lockout threshold rising INUVRISING 3 3.5 3.8 V VIN under-voltage lockout threshold hysteresis INUVHYS 330 mV PG rising threshold PGVth_RISING As a percentage of VFB 83 88 93 % PG falling threshold PGVth_FALLING As a percentage of VFB 78 83 88 % PG threshold hysteresis PGVth_HYS As a percentage of VFB 5 % PG rising delay PGTD_RISING 30 90 160 μs PG falling delay PGTD_FALLING 30 55 95 μs PG sink current capability VPG Sink 4mA 0.4 V PG leakage current IPG_LKG 10 100 nA VCC regulator VCC ICC = 0mA 4.6 4.9 5.2 V VCC load regulation ICC = 5mA 1.5 4 % Soft-start time tSS VOUT from 10% to 90% 0.45 1.5 3 ms Thermal shutdown (5) 170 °C Thermal hysteresis (5) 30 °C NOTE: 5) Derived from bench characterization. Not tested in production.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 5 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PIN FUNCTIONS Package Pin # Name Description 1, 2 IN Supply voltage. IN supplies power for the internal MOSFET and regulator. The MPQ4415M operates from a 4V to 36V input rail. A low ESR and low -inductance capacitor is required to decouple the input rail. Place the input capacitor very close to IN and connect it with wide PCB traces and multiple vias. 3 NC No connection. Do not connect. 4 PG Power good indicator. The output of PG is an open drain and goes high if the output voltage exceeds 88% of the nominal voltage.

5 EN/SYNC

Enable/synchronize. Pull EN/SYNC high to enable the MPQ4415M. Float EN /SYNC or connect EN/SYNC to ground to disable the MPQ4415M. If an external sync clock is applied to EN/SYNC, the internal clock follows the sync frequency. 6 FB Feedback. Connect FB to the tap of an external resistor divider from the output to AGND to set the output voltage. The frequency foldback comparator lowers the oscillator frequency when the FB voltage is below 400mV to prevent current limit runaway during a short-circuit fault. Place the resistor divider as close to FB as possible. Avoid placing vias on the FB traces. 7 VCC Internal b ias supply. Decouple VCC with a 0.1μF - 0.22μF capacitor. The capacitance should be no more than 0.22μF. 8 AGND Analog ground. AGND is the reference ground of the logic circuit. AGND is connected to PGND internally. There is no need to add external connections to PGND. 9 SW Switch output. Connect SW using a wide PCB trace.

10 BST

Bootstrap. A capacitor connected between SW and BS T is required to form a floating supply across the high -side switch driver. A 20Ω resistor placed between the SW and BST capacitor is strongly recommended to reduce SW voltage spikes. 11, 12, 13 PGND Power ground. PGND is the reference ground of the power device and requires careful consideration during PCB layout. For best results, connect PGND with copper pours and vias.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 6 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 7 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued)

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 8 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 2.2µ H, FSW = 2.2MHz, TA = +25° C, unless otherwise noted.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 9 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 2.2µ H, FSW = 2.2MHz, TA = +25° C, unless otherwise noted.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 10 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 2.2µ H, FSW = 2.2MHz, TA = +25° C, unless otherwise noted.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 11 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, Vout = 3.3V, IOUT = 1.5A, L = 2.2 μH, FSW = 2.2MHz, with EMI filters , TA = +25°C, unless otherwise noted.(6) CISPR25 Class 5 Peak Radiated Emissions CISPR25 Class 5 Average Radiated Emissions (150kHz - 30MHz) (150kHz - 30MHz) -15 -10 Frequency (MHz) Amplitude (dBuV/m) Data Class 5 Peak Class 5 Avg -15 -10 Frequency (MHz) Amplitude (dBuV/m) Data Class 5 Peak Class 5 Avg CISPR25 Class 5 Peak Radiated Emissions CISPR25 Class 5 Average Radiated Emissions (Vertical, 30MHz - 1GHz) (Vertical, 30MHz - 1GHz) -15 -10 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) Amplitude (dBuV/m) Data Class 5 Peak Class 5 Avg -15 -10 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) Amplitude (dBuV/m) Data Class 5 Peak Class 5 Avg CISPR25 Class 5 Peak Radiated Emissions CISPR25 Class 5 Average Radiated Emissions (Horizontal, 30MHz - 1GHz) (Horizontal, 30MHz - 1GHz) -15 -10 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) Amplitude (dBuV/m) Data Class 5 Peak Class 5 Avg -15 -10 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) Amplitude (dBuV/m) Data Class 5 Peak Class 5 Avg NOTE: 6) The EMC test results are based on the application circuit with EMI filters (see Figure 10 ).

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 12 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. BLOCK DIAGRAM Figure 1: Functional Block Diagram

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 13 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. OPERATION The MPQ4415M is a high -frequency, synchronous, rectified, step-down, switch-mode converter with built -in power MOSFETs. The MPQ4415M offers a very compact solution that achieves 1.5A of continuous output current with excellent load and line regulation over a 4V to 36V input supply range. The MPQ4415M operates in a fixed -frequency, peak-current-control mode to regulate the output voltage. An internal clock initiates a pulse-width modulation ( PWM) cycle. The integrated high-side power MOSFET (HS-FET) turns on and remains on until the current reaches the value set by the COMP voltage (VCOMP). When the power switch is off, it remains off until the next clock cycle begins. If the current in the power MOSFET does not reach the value set by VCOMP within 85% of one PWM period, the power MOSFET is forced off. Internal Regulator A 4.9V internal regu lator power most of the internal circuitries. This regulator takes V IN as the input and operates in the full V IN range. When V IN exceeds 4.9V, the output of the regulator is in full regulation . When VIN falls below 4.9V, the output decreases following VIN. A 0.1 µF decoupling ceramic capacitor is required at VCC. Continuous Conduction Mode ( CCM) Operation The MPQ4415M uses continuous conduction modulation (CCM) mode to ensure that the part works with a fixed frequency from a no-load to a full-load range. The advantage of CCM is the controllable frequency and lower output ripple at light load. Frequency Foldback The MPQ4415M enters frequency foldback when the input voltage is higher than about 21V. The frequency decreases to half the nominal value and changes to 1.1MHz. Frequency foldback also occurs during soft start and short-circuit protection. Error Amplifier (EA) The error amplifier (EA) compares the FB voltage to the internal 0.8 07V reference ( VREF) and outputs a current proportional to the difference between the two. This output current then charges or discharges the internal compensation network to form VCOMP, which controls the power MOSFET current. The optimized internal compensation network minimizes the exter nal component count and simplifies the control loop design. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The UVLO comparator monitors the output voltage of the internal regula tor (VCC). The UVLO rising threshold is about 3.5V with a 330mV hysteresis. Enable/SYNC EN/SYNC is a control pin that turns the regulator on and off. Drive EN /SYNC high to turn on the regulator ; drive EN/SYNC low to turn off the regulator. An internal 500kΩ resistor from EN/SYNC to GND allows EN /SYNC to be floated to shut down the chip. EN/SYNC is clamped internally using a 6.5V series Zener diode (see Figure 2). Connecting the EN/SYNC input through a pull-up resistor to the voltage on V IN limits the EN input current to less than 100µ A. For example, with 12V connected to V IN, R PULLUP ≥ (12V - 6.5V) ÷ 100µA = 55kΩ. Connecting EN/SYNC to a voltage source directly without a pull-up resistor requires limiting the amplitude of the voltage source to ≤6V to prevent damage to the Zener diode. Figure 2: 6.5V Zener Diode Connection Connect an external clock with a range of 450kHz to 2.2MHz to synchronize the internal clock rising edge to the external clock rising edge. The pulse width of the external clock signal should be below 350ns; the off time of the external clock signal should be below 1.9µs.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 14 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Internal Soft Start (SS) Soft start (SS) prevents the converter output voltage from overshooting during start -up. When the chip starts up, the inte rnal circuitry generates a soft -start voltage ( VSS). When VSS is lower than the internal reference (VREF), VSS overrides VREF, so the error amplifier uses VSS as the reference. When VSS exceeds VREF, the error amplifier uses VREF as the reference. The SS time is set to 1.5ms internally. Power Good (PG) The MPQ4415M has a power good (PG) indicator. PG is the open drain of a MOSFET and should be connected to VCC or another voltage source through a resistor (e.g.: 100kΩ). In the presence of an input voltage, the MOSFET turns on, and PG is pulled low before SS is ready. After V FB reaches 88% x VREF, PG is pulled high after a typical 90μs delay. When VFB drops to 8 3% x VREF, PG is pulled low. PG is also pulled low if thermal shutdown occurs or EN/SYNC is pulled low. Over-Current Protection (OCP) and Hiccup The MP Q4415M has cycle-by-cycle peak current-limit protection and valley -current detection protection. The inductor current is monitored during the HS -FET on -state. If the inductor current exceeds the current-limit value set by the COMP high -clamp voltage, the HS- FET turns off immediately. Then the low -side MOSFET (LS -FET) turns on to discharge the energy, and the inductor current decreases. The HS -FET remains off unless the inductor valley current is lower than a certain current threshold (the valley current limit), even though the internal clock pulses hi gh. If the inductor current does not drop below the valley current limit when the internal clock pulses high, the HS-FET miss es the clock, and the switching frequency decreases to half the nominal value. Both the peak and valley current limits assist in keeping the inductor current from running away during an overload or short-circuit condition. If the output voltage drops below the under - voltage (UV) threshold (typically 50% below the reference), the peak current limit is kicked simultaneously, then the MP Q4415M enters hiccup mode to restart the part periodically. This protection mode is useful when the output is dead -shorted to ground and reduces the average short-circuit current greatly to alleviate thermal issues and protect the regulator. The MPQ4415M exits hiccup mode once the over- current condition is removed. Thermal Shutdown Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the die temperature exceed s 170° C, the entire chip shuts down . When the temperature drops below its lower threshold ( typically 140° C), the chip is enabled again. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating power MOSFET driver. The floating driver has its own UVLO protection with a rising threshold of 2.2V and hysteresis of 150mV. A dedicated internal regulator charges and regulates the bootstrap capacitor voltage to ~5V (see Figure 3). When the voltage between the BST and SW nodes drops below regulation, a PMOS pass trans istor connected from V IN to BST turns on. The charging current path is from VIN to BST and then to SW. The external circuit should provide enough voltage headroom to facilitate charging. As long as V IN is higher than SW significantly, the bootstrap capacitor remains charged. When the HS-FET is on, VIN ≈ VSW, so the bootstrap capacitor cannot be charged. When the LS -FET is on, V IN - VSW reaches its maximum for fast charging. When there is no inductor current, V SW = VOUT, so the difference between VIN and VOUT can charge the bootstrap capacitor. A 20Ω resistor placed between the SW and BST cap acitor is strongly recommended to reduce SW voltage spikes. Figure 3: Internal Bootstrap Charging Circuit

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 15 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Start-Up and Shutdown If both V IN and EN /SYNC exceed their thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current , and then t he internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: V IN low, EN/SYNC low, and thermal shutdown. During the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command.

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 16 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

APPLICATION INFORMATION

Setting the Output Voltage The external resistor divider connected to FB sets the output voltage (see Figure 4). The feedback resistor (R1) also sets the feedback loop bandwidth with the internal compensation capacitor. Choose R FB1 to be around 40kΩ when VOUT  1V. RFB2 can then be calculated with Equation (1): 10.807V V RR OUT FB1 FB2  (1) The T -type network is highly recommended when VOUT is low (see Figure 4). Figure 4: T-Type Feedback Network RT + RFB1 is used to set the loop bandwidth. The lower R T + RFB1 is, the higher the bandwidth. However, a high bandwidth may cause an insufficient phase margin, resulting in loop instability. Therefore, a proper RT value is required to make a trade -off between the bandwidth and phase margin. Table 1 lists the recommended feedback resistor and RT values for common output voltages. Table 1: Resistor Selection for Common Output VOUT (V) RFB1 (kΩ) RFB2 (kΩ) RT (kΩ) Selecting the Input Capacitor The input current to the step -down converter is discontinuous and therefore requires a capacitor to supply AC current to the converter while maintaining the DC input voltage. For the best performance , use low ESR capacitors. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, use a 4.7µF to 10 µF capacitor. It is strongly recommended to use another lower-value capacitor (e.g.: 0.1µF) with a small package size (0603) to absorb high - frequency switching noise. Place the small er capacitor as close to IN and GND as possible. Since CIN absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (2):     OUT OUT CIN LOAD IN IN VVI I (1 ) VV (2) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (3):  LOAD CIN II 2 (3) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high -quality ceramic capacitor (e.g. : 0.1μF) as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by the capacitance can be estimated with Equation (4): LOAD OUT OUT IN SW IN IN IN I V VV (1 )f C V V (4) Selecting the Output Capacitor The output capacitor maintains the DC o utput voltage. Use ceramic, tantalum, or low ESR electrolytic capacitors. For best results, use low ESR capacitors to keep the output voltage ripple low. The output voltage ripple can be estimated with Equation (5): OUT OUT OUT ESR SW IN SW OUT VV 1V (1 ) (R )f L V 8f C (5) Where L is the inductor value , and RESR is the equivalent series resistance (ESR) value of the output capacitor. R FB2 R FB1 RT FB V OUT

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 17 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. For ceramic capacitors, the capacitance dominates the impedance at the switching frequency, and the capacitance causes the majority of the output voltage ripple. For simplification, the output voltage ripple can be estimated with Equation (6): OUT OUT OUT 2 SW OUT IN VVV (1 ) 8 f L C V (6) For tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (7): OUT OUT OUT ESR SW IN VVV (1 ) Rf L V (7) The characteristics of the output capacitor also affect the stability of the regulation system. The MPQ4415M can be optimized for a wide range of capacitance and ESR values. Selecting the Inductor A 1µ H to 10µ H inductor with a DC current rating at least 25% higher than the maximum load current is recommended for most applications. For higher efficiency, choose an inductor with a lower DC resistance. A larger -value inductor results in less ripple current and a lower outpu t ripple voltage , but also has a larger physical size, higher series resistance, and lower saturation current. A good rule for determining the inductor value is to allow the inductor ripple current to be approximately 30% of the maximum load current. The i nductance value can then be calculated with Equation (8): OUT OUT SW L IN VVL (1 )f I V (8) Where ∆IL is the peak -to-peak inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (9): OUT OUT LP LOAD SW IN VVI I (1 ) 2f L V (9) VIN UVLO Setting The MPQ4415M has an internal, fixed, under- voltage lock out (UVLO) threshold . The rising threshold is 3.5V, while the falling threshold is about 3.17V. For application s that require a higher UVLO point, an external resistor divider between IN and EN/SYNC can be used to achieve a higher equivalent UVLO threshold (see Figure 5). Figure 5: Adjustable UVLO using EN Divider The UVLO threshold can be calculated with Equation (10) and Equation (11): UP RISING EN_RISING DOWN DOWN RINUV (1 ) V 500k*R 500k+R    (10) UP FALLING EN_FALLING DOWN DOWN RINUV (1 ) V 500k*R 500k+R    (11) Where VEN_RISING = 1.45V, and VEN_FALLING = 1V. When choos ing RUP, ensure that it is large enough to limit the current flow ing into EN/SYNC below 100µA. BST Resistor and External BST Diode A 20Ω resistor in series with the BST capacitor is recommended to reduce SW voltage spikes. A higher resistance is better for SW spike reduction, but also compromises efficiency. An external BST diode can enhance the efficiency of the regulator when the duty cycle is high (>65%). A power supply between 2.5V and 5V can be used to power the external bootstrap diode. VCC or V OUT is recommended for this power supply in the circuit (see Figure 6).

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 18 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Figure 6: Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the recommended BST capacitor value is 0.1µF to 1μF. PCB Layout Guidelines (7) Efficient PCB layout , especially regarding input capacitor placement , is critical for stable operation. A four -layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 7 and follow the guidelines below. 1. Use a large ground plane to connect directly to PGND. If the bottom layer is a ground plane, add vias near PGND. 2. Ensure that the high-current paths at GND and IN have short, direct, and wide traces. 3. Place the ceramic inp ut capacitor, especially the small -sized input bypass capacitor (0603), as close to IN and PGND as possible to minimize high -frequency noise. 4. Keep the connection of the input capacitor and IN as short and wide as possible. 5. Place the VCC capacitor to VCC and AGND as close as possible. 6. Route SW and BST away from sensitive analog areas such as FB. 7. Place the feedback resistors close to the chip to ensure that the trace connect ing to FB is as short as possible. 8. Use multiple vias to connect the power planes to internal layers. NOTE: 7) The recommended layout is based on Figure 8. Top Layer Inner Layer 1 Inner Layer 2 Bottom Layer Figure 7: Recommended PCB Layout C BST C OUT L BST SW External BST diode

1 N 4148

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 20 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 10μF C1A 0.1μF C1C R1 0.1μF 2.2μH 47μF 3.3V/1.5A 20k EN/SYNC VOUT 10μF C1B SW 9EN/SYNC5 IN1, 2 FB 6VCC7 BST 10 PGND 11,12,13 PG4 0.1μF 100k PG GND 13k MPQ4415M NC AGND 41.2k VIN VEMI GND 1206 FB1 2.2uH 4V-36V CIN1 1nF CIN2 10nF CIN3 1uF CIN4 10uF CIN5 10uF L3150nH 1nF Figure 10: VOUT = 3.3V, IOUT = 1.5A, with EMI Filters

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ4415M Rev. 1.01 www.MonolithicPower.com 21 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-13 (2.5mmx3mm) Non-Wettable Flank SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-220. 4) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID 0.15X45º TYP 0.15X45º

MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4415M Rev. 1.01 www.MonolithicPower.com 22 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. QFN-13 (2.5mmx3mm) Wettable Flank SIDE VIEW BOTTOM VIEW NOTE: 1) THE LEAD SIDE IS WETTABLE. 2) ALL DIMENSIONS ARE IN MILLIMETERS. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID 0.15X45º TYP 0.15X45º SECTION A-A