MPQ2420-AEC1

MPQ2420-AEC1 MPS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 22

Technical content

75V, 0.3A, Synchronous Step-Down Converter with Watchdog AEC-Q100 Qualified MPQ2420 Rev. 1.0 www.MonolithicPower.com 1 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

DESCRIPTION

The MPQ2420 is a step -down switching regulator with integrated high - and low-side, high-voltage power MOSFETs. It provides a highly efficient output of up to 0.3A. The integrated watchdog adds additional security redundancy to the system. The wide 4.5V to 75V input range accommodates a variety of step -down applications in an automotive environment. A 5μA shutdown mode quiescent current in a full temperature range is ideal for battery-powered applications. It allows for high-power conversion efficiency over a wide load range by scaling down the switching frequency under a light-load condition to reduce switching and gate driver losses. The start-up switching frequency and short circuit can also be scaled down to prevent inductor current runaway. Full protection features include under -voltage lockout (UVLO) and thermal shutdown. Thermal shutdown provides reliable, fault -tolerant operation. The MPQ2420 is available in a TSSOP-16 EP package.

FEATURES

 20μA Quiescent Current for Buck Only  Wide 4.5V to 75V Operating Input Range (80V ABS MAX)  1.2Ω/0.45Ω Internal Power MOSFETs  Programmable Soft Start  FB Tolerance: 1% at Room Temperature, 2% at Full Temperature  Adjustable Output Voltage  Integrated Window Watchdog  Power-On Reset during Power-Up  Under-Voltage Lockout and Thermal Shutdown  Programmable Short Window Mode or Long Window Mode  Low Shutdown Mode Current of 5μA  TSSOP-16 EP Package  Available in AEC-Q100 Grade 1

APPLICATIONS

 Automotive Systems  Industrial Power Systems  Distributed Power Systems  Battery-Powered Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Tec hnology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION POK VOUT VREF SS MCU VCC GNDTIMER MODE WDI WDO /DIS_WD MPQ2420 EN VIN BST SW BIAS FB EN VIN VCC

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 2 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MPQ2420GF TSSOP-16 EP See Below MPQ2420GF-AEC1 * For Tape & Reel, add suffix –Z (e.g. MPQ2420GF–Z) TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP2420: Part code of MPQ2420GF LLLLLL: Lot number PACKAGE REFERENCE TOP VIEW IN 2 15 161 FB GND BIAS BST EN SW SS GND SW IN BST BIAS SSFB EN WDI MODE /WD_DIS VCC WDO TIMER VREF VCC NCWDI WDO MODE WAKE GND TIMER POK TSSOP-16 EP

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 3 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Switch voltage (VSW) …… …….-0.3V to VIN + 1V Continuous power dissipation (TA = +25°C) (2) Storage temperature………… .. -65°C to +150C Recommended Operating Conditions (3) Output voltage (VOUT)………………1V to 0.9VIN Thermal Resistance (4) θJA θJC NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the re gulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 4 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 24V, VEN = 2V, VCC = 5V, TJ = -40C to +125C, unless otherwise noted. Parameter Condition Min Typ Max Units DC/DC Converter Supply quiescent current No load, VFB = 1.2V 20 30 µA Shutdown supply current VEN < 0.3V 2.2 5 μA VIN UVLO rising threshold 3.9 4.2 4.4 V VIN UVLO falling threshold 3.45 3.75 3.95 VIN UVLO hysteresis 0.45 V Feedback voltage VIN = 4.5V to 75V, TJ = 25°C 0.99 1.0 1.01 V VIN = 4.5V to 75V 0.98 1.02 V Feedback current VFB = 1.2V -50 2 50 nA VREF voltage VIN = 4.5V to 75V, IREF = 100µA 0.965 1 1.035 V Upper switch-on resistance VBST - VSW = 5V, TJ = 25°C 0.9 1.2 1.5 Ω VBST - VSW = 5V 0.7 2.5 Ω Lower switch-on resistance VBIAS = 5V, TJ = 25°C 0.275 0.45 0.625 Ω VBIAS = 5V 0.2 0.9 Ω Lower switch leakage VEN = 0V, VSW = 75V 1 µA Peak current limit 630 720 810 mA Minimum switch-on time(5) 120 ns Enable rising threshold 1.25 1.55 1.85 V Enable falling threshold 1.152 1.2 1.248 V Enable threshold hysteresis 0.35 V Enable current VEN = 2.4V 0.8 µA Soft-start current 4 5.5 7 µA POK upper trip threshold FB respect to the nominal value 86 90 94 % POK lower trip threshold FB respect to the nominal value 81 85 89 % POK threshold hysteresis FB respect to the nominal value 5 % POK deglitch timer 40 μs POK output voltage low ISINK = 1mA 0.4 V FB OVP rising threshold 1.05 1.1 V FB OVP hysteresis 50 mV Thermal shutdown(5) 175 C Thermal shutdown hysteresis(5) 20 C NOTE: 5) Derived from bench characterization. Not tested in production.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 5 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 24V, VEN = 2V, VCC = 5V, TJ = -40C to +125C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Watchdog Power Supply Timer voltage RTIMER = 51k 0.3 V Quiescent current IQ RTIMER = 100k 16 19 µA RTIMER = 51k 25 32 µA Power-on reset threshold VPOR-HIGH WDO goes high with rising VCC 4.4 4.6 4.8 V VPOR-LOW WDO goes low with falling VCC 4.3 4.5 4.7 V Watchdog Timing Single period T RTIMER = 51k -10% 880 +10% µs Power-on delay(6) t0 RTIMER = 51k 10 cycle Sync signal monitoring time(6) t1 RTIMER = 51k 450 cycle Watchdog window close time (short mode) (6) t2 RTIMER = 51k, mode = low 15 cycle Watchdog window open time (short mode) (6) t3 RTIMER = 51k, mode = low 10 cycle Watchdog window close time (long mode) (6) t4 RTIMER = 51k, mode = high 1500 cycle Watchdog window open time (long mode) (6) t5 RTIMER = 51k, mode = high 1000 cycle WDO reset pulse width(6) t6 RTIMER = 51k 4 cycle WDI_OK pulse width 10 5000 μs Watchdog Input and Output WDI logic high 3.2 V WDI logic low 0.8 V MODE logic high 3.2 V MODE logic low 0.8 V MODE input current MODE = 5V 0.1 1 μA MODE = 0V 5 8 μA /WD_DIS logic high 3.2 V /WD_DIS logic low 0.8 V /WD_DIS input current WD_DIS = 5V 0.1 1 μA WD_DIS = 0V 5 8 μA WDO high VCC = 5V, IWDO = 1mA VCC-0.2 V WDO low VCC = 5V, IWDO = 1mA 0.2 V VCC = 1V, IWDO = 300μA 0.1 V NOTE: 6) Guaranteed by design.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 6 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS DC/DC Converter VIN = 12V, unless otherwise noted.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 7 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) Watchdog

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 8 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS DC/DC Converter VIN = 12V, VOUT = 3.3V, L = 33µH, COUT = 2x22µF, TA = 25C, unless otherwise noted.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 9 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 33µH, COUT = 2x22µF, TA = 25C, unless otherwise noted.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 10 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description Watchdog 1 WDO Watchdog output. WDO outputs the reset signal to MCU. 2 WDI Watchdog input. WDI receives the trigger signal from MCU.

3 MODE

Mode switching. Pull MODE high to make the watchdog work in a long window mode. Pull MODE low to make the watchdog work in a short window mode. MODE has a weak internal pull-up. 4 GND Ground. Connect GND as close as possible to the output capacitor to avoid high - current switch paths. 14 VCC Power input. 15 TIMER Watchdog timer. Set the time out with an external resistor 16 /WD_DIS Watchdog disable. Pull /WD_DIS low to disable the watchdog . Pull /WD_DIS high to enable the watchdog. /WD_DIS has a weak internal pull-up. DC/DC 4 GND Ground. Same as GND in Watchdog. 5 IN Input supply. IN r equires a decoupling capacitor connected to ground to reduce switching spikes. 6 EN Enable input. Pull EN below the low threshold to shut the chip down. Pull EN above the high threshold to enable the chip. Float EN to disable the chip. 7 VREF Reference voltage output. 8 FB Feedback input to the error amplifier (QFN-10 3mmx3mm package only ). Connect FB to the tap of an external resistive divider between the output and GND. FB sets the regulation voltage when compared to the internal 1V reference. 9 SS Soft-start control input . Connect a capacitor from SS to GND to set the soft -start period. 10 POK Open-drain power -good output . A high output indicates that VOUT is higher than 90% of the reference. POK is pulled down during shutdown.

11 BIAS

Controller bias input. BIAS supplies current to the internal circuit when VBIAS > 2.9V and provides a feedback input for the SOIC8E package, which has a fixed output only. 12 BST Bootstrap. BST provides a p ositive power supply for the internal floating high -side MOSFET driver. Connect a bypass capacitor between BST and SW. 13 SW Switch node. Exposed Pad Connect exposed pad to GND plane for optimal thermal performance.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 11 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM REF Regulator ZCD SS FB GND RS S R COMP ICOMP SS SW BST VIN POK ILIMIT POK EN EN Control BIAS FB Power On Reset Oscillator, State Machine VCC WDGND MODE WDI WDO TIMER/WD_DIS VREF Figure 1: Functional Block Diagram

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 12 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. DC/DC OPERATION The MPQ2420 is a 75V, 0.3A, synchronous, step-down, switching regulator with integrated high-side and low -side, high-voltage power MOSFETs (HS-FET and LS-FET, respectively). It provides a highly efficient 0.3A output and features a wide input voltage range, external soft- start control, and precision current limit. It has a very low operational q uiescent current, making it suitable for battery-powered applications. Control Scheme The ILIM comparator , FB comparator , and zero current detector (ZCD) block control of the PWM (see Figure 2) . If VFB is below the 1V reference and the inductor current dro ps to zero, the HS- FET turns on , and t he ILIM comparator begins sensing the HS-FET current. When the HS-FET current reaches its limit, the HS-FET turns off , and the LS-FET and the ZCD block turn on. The ILIM comparator turns off to reduce the quiescent current. The LS-FET and the ZCD block turn off after the inductor current drops to zero. If V FB is below the 1V reference, the HS-FET turns on and begins another cycle. If V FB remains higher than the 1V reference, the HS-FET remains off until VFB drops below 1V. VSW VFB IL Ipeak Io VREF Io increase Figure 2: Control Scheme Internal Regulator and BIAS The 2.6V internal regulator powers most of the internal circuitry. This regulator takes V IN and operates in the full VIN range. When VIN is greater than 3.0V, the output of the regulator is in full regulation. Lower values of V IN result in lower output voltages. When V BIAS > 2.9V, the BIAS supply overrides the input voltage and supplies power to the internal regulator. When V BIAS > 4.5V, BIAS powers the LS-FET driver. Using BIAS to power the internal regulator s improves efficiency. It is recommended to connect BIAS to the regulated output voltage when it is in the 2.9V to 5.5V range. When the output voltage is out of this range, BIAS can be powered using an external supply of >2.9V to >4.5V. Enable Control (EN) The MPQ2420 has a dedicated enable control (EN). W hen V IN goes high, EN enables and disables the chip (high logic). Its falling threshold is a consistent 1.2V , and its rising threshold is about 350mV. When floating, EN is pulled down internally to GND to disable the chip. When EN = 0V, the chip enters the lowest shutdown current mode. When EN is higher than zero, but lower than its rising threshold, the chip remains in shutdown mode with a slightly larger shutdown current. A Zener diode is connected internally from EN to GND. The typical clamping voltage of the Zener diode is 6.5V. V IN can be connected to EN through a high ohm (Ω) resistor if the system does not have another logic input acting as an EN signal. The resistor must be designed to limit the EN sink current to less than 1 50μA. Since there is an internal 3M resistor from EN to GND, the external pull -up resistor should be smaller than 1.55V 3M1.55V]-[V (MIN)IN  to ensure that EN can turn on at the lowest operational VIN.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 13 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating below the operational supply voltage range. The UVLO rising t hreshold is about 4 .2V while its falling threshold is about 3.75V. Soft Start (SS) The MPQ2420 employs a soft-start (SS) mechanism to prevent the converter output voltage from overshooting during start -up. When the chip starts, the internal circuitry gene rates a constant current to charge an external soft-start capacitor. The SS voltage ramps up slowly from 0V at a slow pace set by the SS time. When VSS is less than V REF, VSS overrides VREF, and the FB comparator uses VSS as the reference instead of VREF. When V SS is higher than V REF, V REF resumes control. VSS can be much smaller than VFB, but it can only barely exceed V FB. If V FB drops, V SS tracks V FB. This function prevents an output voltage overshoot during short-circuit recovery. When the short circuit is removed, a new SS process ramps up. Thermal Shutdown Thermal shutdown prevents the chip from operating a t exceedingly high temperatures . When the silicon die reaches temperatures that exceed its upper threshold, the entire chip shuts down. When the temperature falls below its lower threshold, the chip is enabled again. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating HS-FET driver. This floating driver has its own UVLO protection . This UVLO’s rising threshold is about 2.4V with a hysteresis of about 300mV. During the UVLO, the SS voltage resets to zero. When the UVLO is disabled, the regulator follows the soft-start process. The dedicated internal bootstrap regulator charges and regulates the bootstrap capacitor to about 5V. When the voltage difference between BST and SW falls below its working parameters, a PMOS pass transistor connected from V IN to BST turns on to charge the bootstrap capacitor. The current path runs from V IN to BST to SW. The external circuit must have enough voltage headroom to accommodate charging. If VIN is sufficiently higher than SW, the bootstrap capacitor charges. When the HS-FET is on, VIN is about equal to SW , and the bootstrap capacitor cannot charge. The optimal charging period occurs when the LS-FET is on and VIN - VSW is at its largest. VSW is equal to VOUT when there is no current in the inductor . The difference between VIN and VOUT charges the bootstrap capacitor. If the internal circuit does not have sufficient voltage and time t o charge the bootstrap capacitor, extra external circuitry can be used to ensure that the bootstrap voltage operates in its normal region. Start-Up and Shutdown If both V IN and V EN are higher than their appropriate thresholds, the chip starts up . The reference block starts first, generating stable reference voltage s and currents , and then the internal regulator is enabled . The regulator provides a stable supply for the remaining circuitries. If the internal supply rail is high, an internal timer keeps the power MOSFET off for about 50µs to clear any start-up glitches. When the soft -start block is enabled, the SS output is held low and ramps up slowly. Three events can shut down the chip: V EN low, VIN low, and thermal shutdown. During the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. The internal supply rail is then pulled down. The floating driver is not subject to this shutdown command, but its charging path is disabled. Power OK (POK) POK is an open -drain power good output. A high output indicates that VOUT is higher than 90% of its nominal value . POK is pulled down in shutdown mode. Reference Voltage Output (VREF) VREF has an output reference voltage of 1V. It has up to 500µA of source current capability.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 14 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. WATCHDOG OPERATION Supply Voltage A supply voltage of VCC = 5V +/ -10% is recommended for normal operation. WDO is pulled low when V CC rises to 1V or higher. When VCC rises to 4.65V, WDO remains at a low level for t0 to reset the MCU. Timer Calculate Period T (µs) with Equation (1): (1) Calculate RTIMER (k) with Equation (2): (2) For example, if RTIMER=51kΩ, then T0.88ms. Monitor MCU Synchronization Signal When the watchdog is in a sync signal monitoring state, the watchdog IC receiv es a WDI_OK signal from the MCU within t 1, the timer reset s and the watchdog enters normal operation (WDI remains low for 10µs to 5ms). If the watchdog does not receive the WDI_OK signal from the MCU during t 1, it generate s a reset signal and enters the sync signal monitoring state again. Short Window Mode When the MCU and watchdog are synchronized correctly and MODE is low, the watchdog operates in short window mode if WDI_OK is received in a window close state (t 2). The watchdog then outputs a reset signal and enters the sync signal monitoring state. If WDI_OK is received in a window open state (t3), the watchdog enters a window close state. The MCU is in normal operation in this situation. If WDI_OK is not received in t2+t3, the watchdog outputs a reset signal and enters the sync signal monitoring state. MODE is pulled high during the short window mode, and the watchdog enters a long window mode. Long Window Mode When the MCU and watchdog are synchronized correctly and MO DE is high, the watchdog works in a long window mode if WDI_OK is received in a window close state (t 4). The watchdog then outputs a reset signal and enters the sync signal monitoring state. If WDI_OK is received in a window open state (t5), the watchdog enters a window close state. The MCU is in normal operation in this situation. If WDI_OK is not received in t4+t5, the watchdog then outputs a reset signal and enters the sync signal monitoring state. MODE is pulled low during a long window mode, and the watchdog then enters a short window mode. Watchdog Disable Pull /WD_DIS low to disable the watchdog . Pull /WD_DIS high to enable the watchdog. It has a weak internal pull-up so leaving /WD_DIS open enables the watchdog. WDI Error The WDI signal remaining at a low level for longer than the max WDI_OK pulse width is regarded as an error. When this error occurs, WDO is pulled down until WDI rises to a high level again.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 15 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TIMING DIAGRAM Power-On Reset and No-Sync Signal VCC VCC=1V VCC=90% WDO Floating WDI MODE Synchronized by WDI and Triggered in Open Window (MODE=0, Short Window Mode) VCC WDO WDI WDI_OK t2 t3 WDI_OK MODE 0 Synchronized by WDI and No-Trigger Signal (MODE=0, Short Window Mode) VCC WDO WDI WDI_OK t2 t3 MODE 0

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 16 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Synchronized by WDI and Triggered in Closed Window (MODE=0, Short Window Mode) VCC WDO WDI WDI_OK MODE 0 WDI_OK NOTE: When the WDI_OK rising edge approaches WDO when it is low, the t6 timer resets. In the above situation, the WDO reset signal keeps a t6+WDI_OK time. Synchronized by WDI and Triggered in Open Window (MODE=1, Long Window Mode) VCC WDO WDI WDI_OK t4 t5 WDI_OK MODE 0 Synchronized by WDI and No-Trigger Signal (MODE=1, Long Window Mode) VCC WDO WDI WDI_OK t4 t5 MODE 0

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 17 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Synchronized by WDI and Triggered in Closed Window (MODE=1, Long Window Mode) VCC WDO WDI WDI_OK MODE 0 WDI_OK NOTE: When the WDI_OK rising edge approaches WDO when it is low, the t6 timer resets. In the above situation, the WDO reset signal keeps a t6+WDI_OK time.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 18 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. STATE DIAGRAM WDO reset state Sync signal monitoring state time-out t0 Short window close state Long window close state Short window open state Long window open state WDI_OK & MODE=0 time-out t2 WDI_OK WDI_OK time-out t4 MODE=1 MODE=1 MODE=0 MODE=0 WDO reset pulse state time-out t3 time-out t5 time-out t6 WDI=0 time-out t1 WDI=0 WDI_OK & MODE=1 NOTE: The above state diagram does not show a WDI error situation.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 19 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

APPLICATION INFORMATION

The Ipeak is fixed, and the inductor value can be determined with Equation (3):   speakIN OUTINOUT fIV V-VVL  (3) Where f S is the switching frequency at the maximum output current. A larger inductor value results in a lower switching frequency and higher efficiency. However, the larger value inductor has a larger physical size, a higher series resistance, a lower saturation current , and/or a slow load transient dynamic performance. The inductor value has a lower limit, which is determined by the minimum on time. To keep the inductor functioning properly, choose an inductor value that is higher than LMIN, which is derived from Equation (4): peak ON(MIN)MAXIN MIN I tV L (4) Where VIN(MAX) is the maximum value of the input voltage, and tON(MIN) is the 115ns minimum switch on time. Switching Frequency The s witching frequency can be estimated with Equation (5):   LVI V-VVIo2f IN peak OUTINOUT s  (5) A l arger inductor can produce a lower f S. f S increases as Io increas es. When Io increases to its maxim um value I peak/2, f S also reaches its highest value . The maximum f S value can be estimated with Equation (6):   LVI V-VVf INpeak OUTINOUT s(max) (6) Setting the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB. To achieve the desired output voltage, select a resistor divider using Equation (7): 1-V V REF OUT (7) Where VREF is the FB reference voltage 1V. The current flowing into the resistor divider increases the supply current, especially at no - load and light -load condition s. The V IN supply current caused by the feedback resistors can be calculated with Equation (8): η V V R2R1 VI IN OUTOUT (8) Where ƞ is the efficiency of the regulator. To reduce this current, resistors in the MΩ range are recommended. The recommende d value of the feedback resistors are shown in Table 1. Table 1: Resistor Selection for Common Output Voltages VOUT (V) R1 (kΩ) R2 (kΩ) 3.3 1200 523 5 1200 300 Under-Voltage Lockout Point Setting The MPQ2420 has an internal fix ed under- voltage lockout (UVLO) threshold . The rising threshold is about 4.2V while the falling threshold is about 3. 75V. An e xternal resistor divider between EN and V IN can be used to obtain a higher equivalent UVLO threshold (see Figure 3). VIN EN IN 3MR5 Figure 3: Adjustable UVLO Using EN The UVLO threshold can be calculated with Equation (9) and Equation (10): TH_RisingTH_Rising EN3M//R5 R4(1UVLO  ) (9) TH_FallingTH_Falling EN3M//R5 R4(1UVLO  ) (10)

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 20 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Soft-Start Capacitor The soft -start time is the duration of an internal 5μA current source charging the SS capacitor from 0 to the FB reference voltage (1V). The SS capacitor value can be determined with Equation (11): F)μ(tC SSSS 5 (11) Feed-Forward Capacitor The HS-FET turns on when FB drops below the reference voltage, producing good load transient performance. However, this also causes the HS- FET to be sensitive to the FB voltage during turn- on. The HS-FET is easily affected by FB noise at turn-on, which can trigger a Fsw jitter. Fsw jitter occurs most often when the Vo ripple is very small. To improve jitter performance, it is recommended to use a small feed -forward capacitor of about 39pF between Vo and FB.

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG MPQ2420 Rev. 1.0 www.MonolithicPower.com 21 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUITS 0.1uF C1A NS 100K 10nF 0.1uF 0.1uF 33uH 4.5V-75V 47uF C2B 10V 10R3 3.3V/300mA 510K 1.2MR1 39pF 0.1uF C2A 10V VIN GND EN VOUT GND POK 1uF 10uF C1B 100V VCC MODE WDI WDO /WD_DIS SW 13 EN6 VREF 7 POK 10 VIN5 FB 8 BIAS 11 BST 12 GND4 SS 9 TIMER15 VCC14 MODE3 WDI2 WDO1 /WD_DIS16 51K 100V MPQ2420 Figure 4: 3.3V Output Typical Application Circuit

MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG NOTICE: The information in this document is subject to change without notice. Please conta ct MPS for current specifications. Users should warrant and guarantee that third party I ntellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ2420 Rev. 1.0 www.MonolithicPower.com 22 5/24/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

PACKAGE INFORMATION

DETAIL "A" NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WITDH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION ABT. 6) DRAWING IS NOT TO SCALE. PIN 1 ID TOP VIEW RECOMMENDED LAND PATTERN SEE DETAIL "A"