MPQ2325 MPS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
24V, 3A, 500kHz, High-Efficiency, Synchronous, Step-Down Converter MPQ2325 Rev. 1.0 www.MonolithicPower.com 1 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
DESCRIPTION
The MPQ2325 is a high -frequency, synchronous, rectified, step-down, switch-mode converter with built -in, internal power MOSFETs. It offers a very compact solution that achieves 3A of continuous output current with excellent load and line regulation over a wide input supply range . The MPQ2325 uses synchronous mode operation for higher efficiency over the output current load range. Current mode operation provides a fast transient response and eases loop stabilization. Full protection features include over-current protection (OCP) and thermal shutdown. The MPQ2325 requires a minim al number of readily available , standard, external components and is available in a space -saving, 8-pin, TSOT23 package.
FEATURES
Wide 4.5V to 24V Operating Input Range 90mΩ/40mΩ Low RDS(ON) Internal Power MOSFETs Low Quiescent Current High-Efficiency Synchronous Mode Operation Fixed 500kHz Switching Frequency Frequency Sync from 200kHz to 2MHz External Clock Power-Save Mode at Light Load Internal Soft Start Power Good Indicator Over-Current Protection (OCP) and Hiccup Thermal Shutdown Output Adjustable from 0.8V Available in a TSOT23-8 Package
APPLICATIONS
Notebook Systems and I/O Power Digital Set-Top Boxes Flat-Panel Televisions and Monitors All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION IN EN / SYNC VCC GND FB SW BSTVIN EN/ SYNC 0.1µF 40.2k 12.7k 4.9µH 44µF 0.1µFC1 22µF 3.3V/3A Rt 33k VOUT MPQ2325 PG 100k
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 2 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking MPQ2325GJ TSOT23-8 See Below * For Tape & Reel, add suffix –Z (e.g. MPQ2325GJ–Z) TOP MARKING AKE: Product code of MPQ2325GJ Y: Year code PACKAGE REFERENCE TSOT23-8 ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25°C) (2) Recommended Operating Conditions Operating junction temp (TJ). ... -40°C to +125°C Thermal Resistance (3) θJA θJC NOTES: 1) The absolute maximum is rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. E xceeding the maximum allowable power dissipation produces an excessive die temperature, causing the device to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Measured on JESD51-7, 4-layer PCB.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 3 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C. Parameter Symbol Condition Min Typ Max Units Supply current (shutdown) IIN VEN = 0V TJ = 25°C 5.5 μA TJ = -40°C to +125°C 20 Supply current (quiescent) Iq VEN = 2V, VFB = 1V 130 180 240 μA HS switch on resistance HSRDS-ON VBST-SW = 5V 90 mΩ LS switch on resistance LSRDS-ON VCC = 5V 40 mΩ Switch leakage SWLKG VEN = 0V, VSW = 12V 1 μA Current limit (5) ILIMIT Duty cycle = 40% 4.5 6 A Oscillator frequency fSW VFB = 750mV TJ = 25°C 420 500 620 kHz TJ = -40°C to +125°C 380 620 Foldback frequency fFB VFB = 200mV 0.5 fSW Maximum duty cycle DMAX VFB = 750mV 90 95 % Minimum on time (5) TON_MIN 60 ns Sync frequency range fSYNC 0.2 2 MHz Feedback voltage VFB TJ = 25°C 779 791 803 mV TJ = -40°C to +125°C 775 807 Feedback current IFB VFB = 820mV 10 50 nA EN hysteresis VEN_HYS 150 mV EN input current IEN VEN = 2V TJ = 25°C 1.8 2.3 2.8 μA TJ = -40°C to +125°C 1.6 3 VEN = 0 TJ = 25°C 50 nA TJ = -40°C to +125°C 100 EN turn-off delay ENTd-off 6 10 14 μs Power good rising threshold PGVTH-Hi 0.9 VFB Power good falling threshold PGVTH-LO 0.85 VFB Power good delay PGTd 40 μs Power good sink current capability VPG Sink 1mA 0.4 V Power good leakage current IPG-LEAK 1 μA VIN under-voltage lockout VIN under-voltage lockout threshold hysteresis INUVHYS 650 mV VCC load regulation ICC = 5mA 1 3 %
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 4 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C. Parameter Symbol Condition Min Typ Max Units Soft-start period TSS TJ = 25°C 0.8 1.6 2.4 ms TJ = -40°C to +125°C 0.5 2.7 Thermal shutdown(4) 150 °C Thermal hysteresis(4) 20 °C NOTES: 4) Derived from bench characterization. 5) Guaranteed by design.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 5 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 4.9μH, TA = 25°C, unless otherwise noted.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 6 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 4.9μH, TA = 25°C, unless otherwise noted.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 7 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 4.9µH, TA = 25°C, unless otherwise noted.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 8 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. PIN FUNCTIONS Package Pin # Name Description 1 PG Power good output . The output of PG is an open drain . PG is pulled up to VCC by an external resistor when the output voltage exceeds 90% of the normal voltage. There is a 40µs delay between the time when FB becomes greater than or equal to 90% and PG rises high. 2 IN Supply voltage. IN supplies power for the internal MOSFET and regulator. The MPQ2325 operates from a +4.5V to + 24V input rail. IN requires a low ESR and low inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to IN, and connect it with wide PCB traces and multiple vias. 3 SW Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to VIN by the high -side switch during the PWM duty cycle on time. The inductor current drives SW negative during the off time. The on resistance of the low -side switch and the internal body diode fixes the negative voltage. Connect SW using wide PCB traces and multiple vias.
4 GND
System ground. GND is the reference ground of the regulated output voltage. GND requires special consideration during PCB layout. For best results, connect GND with copper traces and vias. 5 BST Bootstrap. A capacitor and a 20Ω resistor connected between SW and BST are required to form a floating supply across the high-side switch driver.
6 EN/SYNC
Enable/sync. Set EN/SYNC = 1 to enable the MPQ2325. An external clock can be applied to EN /SYNC to change the switching frequency. For automatic start -up, connect EN/SYNC to VIN with a 100kΩ resistor. 7 VCC Bias supply. Decouple VCC with a 0.1μF - 0.22μF cap acitor. The capacitance should not exceed 0.22μF. 8 FB Feedback. An external resistor divider from the output to GND tapped to FB sets the output voltage. To prevent current limit run away during a short -circuit fault condition , the frequency fold back comparator lowers the oscillator frequency when the F B voltage is below 400mV.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 9 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. BLOCK DIAGRAM Figure 1: Functional Block Diagram
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 11 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. The chip can be synchronize d to the external clock range from 2 00kHz up to 2MHz through EN/SYNC about 2ms after the output voltage is set with the internal clock r ising edge synchronized to the external clock rising edge. The EN/SYNC synchronized logic high voltage should be higher than 2V. The EN/SYNC synchronized logic low voltage should be lower than 400mV. The EN/SYNC logic high pulse width must be less than 1.6 µs; otherwise, the internal clock may turn on the high-side MOSFET. The EN/SYNC logic low pulse width must be less than 6 µs; otherwise, the MPQ2325 may enter EN/SYNC shutdown. Power Good (PG) Indicator The MPQ2325 has an open-drain pin for power good indicat ion (PG). When FB is higher than 90% of the regulation voltage, PG is pulled up to VCC by an external resistor. If the FB voltage drops down to 8 5% of the regulation voltage, PG is pulled down to gro und by an internal MOSFET. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the MPQ2325 from operating at an insufficient supply voltage. The MPQ2325 UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 3.9V, while its falling threshold is a consistent 3.25V. Internal Soft Start (SS) Soft start (SS) is implemented to prevent the converter output voltage from overshooting during start -up. When the chip starts up, the internal circuitry generates a soft -start voltage that ramps up from 0V. The soft -start period lasts until the voltage on the soft -start capacitor exceeds the reference voltage of 0.8V. At this point, the reference voltage take s over. The soft-start time is set to around 1.5ms internally. Over-Current Protection (OCP) and Hiccup The MPQ2325 uses a cycle-by-cycle over - current limit when the inductor current peak value exceeds the set current limit thresh old. Meanwhile, the output voltage begins dropping until FB is below the under-voltage (UV) threshold, typically 50% below the reference. Once UV is triggered, the MPQ2325 enters hiccup mode to restart the part periodically. This protection mode is especially useful when the output is dead shorted to ground. The average short-circuit current is reduced greatly to alleviate thermal issue s and protect the regulator. The MPQ2325 exits hiccup mode once the over-current condition is removed. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, the entire chip shuts down. When the temperature is lower than its lower threshold (typically 130°C ), the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by V IN through D1, R5, C5, L1, and C2 ( see Figure 4). If VIN - VSW is more than 5V, U1 regulates M1 to maintain a 5V BST voltage across C5. Figure 4: Internal Bootstrap Charging Circuit Start-Up and Shutdown If both V IN and EN/SYNC are higher than their appropriate thresholds, the chip starts up. The reference block star ts first, generating a stable reference voltage and current , and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: EN/SYNC low, VIN low, and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 12 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltage The external resistor divider is used to set the output voltage (see the Typical Application on page 1). The feedback resistor (R1) also sets the feedback loop band width with the internal compensation capacitor. R2 can be calculated with Equation (1): OUT V 0.8V (1) The T -type network is highly recommended (see Figure 5). Figure 5: T-Type Network Table 1 lists the recommended T -type resistors values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) R1 (kΩ) R2 (kΩ) Rt (kΩ) L (µH) Cf (pF) 1 20.5 76.8 100 1.8 15 1.2 20.5 39.2 100 1.8 15 1.8 40.2 31.6 56 3.3 15 2.5 40.2 18.7 56 3.3 15 3.3 40.2 12.7 33 4.9 15 5 40.2 7.5 33 4.9 15 Selecting the Inductor A 1µH to 22µH inductor with a DC current rating at least 25% higher than the maximum load current is recommended for most applications. For the highest efficiency, the inductor DC resistance should be less than 15mΩ. For most designs, the inductance value can be derived from Equation (2): OUT IN OUT IN L OSC V (V V )L V I f Where ∆IL is the inductor ripple current. Choose the inductor current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (3): III L LOAD)M AX(L (3) Under light -load conditions below 100mA, a larger inductance is recommended for improved efficiency. Selecting the Input Capacitor The input current to the step -down converter is discontinuous and therefore requires a capacitor to supply AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 22µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (4): IN OUT IN OUTLOAD1C V V1V VII (4) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (5): II LOAD 1C (5) For simplification, choose the input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, a small, high -quality, ceramic capacitor (i.e.: 0.1μF) should be placed as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at the input. The input voltage ripple caused by the capacitance can be estimated with Equation (6): LOAD OUT OUT IN INS IN I V VV1 f C1 V V
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 13 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Selecting the Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are recommended to keep the output voltage ripple low. The output voltage ripple can be estimated with Equation (7): OUT OUT OUT ESR S 1 IN S VV 1V 1 R f L V 8 f C2 Where L1 is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated with Equation (8): OUT OUT OUT 2 INS1 VVΔV 1 V8 f L C2 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (9): OUT OUT OUT ESR INS1 VVΔV 1 Rf L V The characteristics of the output cap acitor also affect the stability of the regulation system. The MPQ2325 can be optimized for a wide range of capacitance and ESR values. External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator . The applicable conditions of the external BST diode are: VOUT is 5V or 3.3V Duty cycle is high: D = IN OUT V V > 65% In these cases, an external BST diode is recommended from VCC to BST (see Figure 6). RBST MPQ2325 Figure 6: Optional External BST Diode Added Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the recommended BST cap is 0.1μF - 1μF. PCB Layout Guidelines (6) Efficient PCB layout is critical for stable operation. For best results, refer to Figure 7 and follow the guidelines below. 1. Keep the connection of the input ground and GND as short and wide as possible. 2. Keep the connection of the input capacitor and IN as short and wide as possible. 3. Ensure that all feedback connections are short and direct. 4. Place the feedback re sistors and compensation components as close to the chip as possible. 5. Route SW away from sensitive analog areas such as FB. NOTE: 6) The recommended layout is based on Figure 8 in the Typical Application Circuit section on page 15.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MPQ2325 Rev. 1.0 www.MonolithicPower.com 14 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. C1A R4 R2 Vin GND Vout SW GND GND SW BST GND VOUT EN/SYNC VCC C2A Figure 7: Sample Board Layout Design Example Table 2 is a design example following the application guidelines for the specifications below. Table 2: Design Example VIN 19V VOUT 5V IO 3A The detailed application sc hematics are shown in Figure 8 through Figure 13. The typical performance and circuit waveforms are shown in the Typical Performance Characteristics section. For more device applications, please refer to the related evaluation board datasheets.
MPQ2325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating M PS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ2325 Rev. 1.0 www.MonolithicPower.com 17 7/25/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
PACKAGE INFORMATION
PACKAGE OUTLINE DRAWING FOR 8L TSOT23 MF-PO-D-0105 revision 3.0 FRONT VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-193, VARIATION BA. 6) DRAWING IS NOT TO SCALE. 7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) TOP VIEW RECOMMENDED LAND PATTERN SEATING PLANE SIDE VIEW DETAIL ''A'' SEE DETAIL ''A'' IAAAA PIN 1 ID See note 7 EXAMPLE TOP MARK