MPQ1924 MPS | Alldatasheet
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Technical content
100V, 4A, High Frequency Half-Bridge Gate Driver MPQ1924 Rev. 1.0 www.MonolithicPower.com 1 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
DESCRIPTION
The MPQ1924 is a high -frequency, 100V, half- bridge, N-channel, power MOSFET driver. Its low-side and high -side driver channels are independently controlled and matched with less than 5ns in time delay. Under -voltage lockout on both high -side an d low -side supplies force their outputs low in case of insufficient supply. The integrated bootstrap diode reduces external component count.
FEATURES
Drives an N-Channel MOSFET Half Bridge 118V VBST Voltage Range On-Chip Bootstrap Diode Typical Propagation Delay of 20ns Gate Drive Matching of Less than 5ns Drives a 2.2nF Load with 15ns Rise Time and 12ns Fall Time at 12V VDD TTL-Compatible Input Quiescent Current of Less than 150A UVLO for Both High Side and Low Side SOIC-8 Package
APPLICATIONS
Motor Drivers Telecom Half-Bridge Power Supplies Avionics DC-DC Converters Two-Switch Forward Converters Active-Clamp Forward Converters All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION M VDC DRVH DRVL SW BST VSS VSS VDD VDD DRVH DRVL SW BST INH INL INH INL MOTOR DRIVER 12V
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 2 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number Package Top Marking MPQ1924HS* SOIC-8 See Below * For Tape & Reel, add suffix –Z (e.g. MPQ1924HS–Z) For RoHS compliant packaging, add suffix –LF (e.g. MPQ1924HS–LF–Z) TOP MARKING MP1924: product code of MPQ1924HS; LLLLLLLL: lot number; MPS: MPS prefix; Y: year code; WW: week code; PACKAGE REFERENCE SOIC-8
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 3 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Continuous Power Dissipation (TA = 25° C) (2) Recommended Operating Conditions (3) Operating Junction Temp. (TJ) ... -40C to 125C Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temper ature T J(MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)- TA)/ θJA. Exceeding the maximum allowable power d issipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 4 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VDD = VBST-VSW = 12V, VSS = VSW = 0V, No load at DRVH and DRVL, TA = +25C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Supply Currents VDD quiescent current IDDQ INL = INH = 0 100 150 µA VDD operating current IDDO fsw = 500kHz 9 mA Floating driver quiescent current IBSTQ INL = INH = 0 60 90 µA Floating driver operating current IBSTO fsw = 500kHz 7.5 mA Leakage current ILK BST = SW = 100V 0.05 1 A Inputs INL/INH High 2 2.4 V INL/INH Low 1 1.4 V INL/INH internal pull -down resistance RIN 185 k Under Voltage Protection VDD rising threshold VDDR 8.1 8.4 8.8 V VDD hysteresis VDDH 0.5 V (BST-SW) rising threshold VBSTR 6.9 7.3 7.7 V (BST-SW) hysteresis VBSTH 0.55 V Bootstrap Diode Bootstrap diode VF @ 100μA VF1 0.5 V Bootstrap diode VF @ 100mA VF2 0.95 V Bootstrap diode dynamic R RD @ 100mA 2 Low Side Gate Driver Low level output voltage VOLL IO = 100mA 0.08 V High level output voltage to rail VOHL IO = -100mA 0.23 V Source Current(5) IOHL VDRVL = 0V, VDD = 12V 3 A VDRVL = 0V, VDD = 16V 4.7 A Sink Current(5) IOLL VDRVL = VDD = 12V 4.5 A VDRVL = VDD = 16V 6 A Floating Gate Driver Low level output voltage VOLH IO = 100mA 0.08 V High level output voltage to rail VOHH IO = -100mA 0.23 V Source Current(5) IOHH VDRVH = 0V, VDD = 12V 2.6 A VDRVH = 0V, VDD = 16V 4 A Sink Current(5) IOLH VDRVH = VDD = 12V 4.5 A VDRVH = VDD = 16V 5.9 A
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 5 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD = VBST-VSW = 12V, VSS = VSW = 0V, No load at DRVH and DRVL, TA = +25C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Switching Spec. --- Low Side Gate Driver Turn-off propagation delay INL falling to DRVL falling TDLFF 20 ns Turn-on propagation delay INL rising to DRVL rising TDLRR 20 DRVL rise time CL = 2.2nF 15 ns DRVL fall time CL = 2.2nF 9 ns Switching Spec. --- Floating Gate Driver Turn-off propagation delay INH falling to DRVH falling TDHFF 20 ns Turn-on propagation delay INH rising to DRVH rising TDHRR 20 ns DRVH rise time CL = 2.2nF 15 ns DRVH fall time CL = 2.2nF 12 ns Switching Spec. --- Matching Floating driver turn -off to low side drive turn-on(5) TMON 1 5 ns Low side driver turn-off to floating driver turn-on(5) TMOFF 1 5 ns Minimum input pulse width that changes the output(5) TPW 50 ns Bootstrap diode turn -on or turn - off time(5) TBS 10 ns Thermal shutdown 150 C Thermal shutdown hysteresis 25 C Note: 5) Guaranteed by design. INPUT (INH, INL) OUTPUT (DRVH, DRVL) TDHRR, TDLRR TDHFF, TDLFF INPUT (INH, INL) OUTPUT (DRVH, DRVL) TDHRR, TDLRR TDHFF, TDLFF INL INH DRVL DRVH TMON TMOFF Figure 1: Timing Diagram
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 6 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. PIN FUNCTIONS SOIC-8 Pin # Name Description 1 VDD Supply input. This pin supplies power to all the internal circuitry. Place a decoupling capacitor to ground close to this pin to ensure stable and clean supply. 2 BST Bootstrap. This is the positive power supply for the internal floating high -side MOSFET driver. Connect a bypass capacitor between this pin and SW pin. 3 DRVH Floating driver output. 4 SW Switching node. NC No connection. 5 INH Control signal input for the floating driver. 6 INL Control signal input for the low side driver.
7 VSS,
exposed pad Chip ground. Connect exposed pad to VSS for proper thermal operation. 8 DRVL Low side driver output.
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 7 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VDD =12V, VSS = VSW = 0V, TA = +25C, unless otherwise noted.
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 8 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD =12V, VSS = VSW = 0V, TA = +25C, unless otherwise noted.
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 9 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD =12V, VSS = VSW = 0V, TA = +25C, unless otherwise noted.
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 10 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. BLOCK DIAGRAM Figure 2: Function Block Diagram
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 11 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. APPLICATION The input signals of INH and INL can be controlled independently. If both INH and INL control the high -side MOSFET and low-side MOSFET of the same bridge, then users must avoid shoot through by setting sufficient dead time between INH and INL low, and vice versa. See Figure 3 below . Dead time is defined as the time interval between INH low and INL low. Figure 3: Shoot-Through Timing Diagram
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER MPQ1924 Rev. 1.0 www.MonolithicPower.com 13 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Active-Clamp Forward Converter In active -clamp forward converter topology, the MPQ1924 drives the MOSFETs with alternating signals. The high -side MOSFET, in conjunction with Creset, is used to reset the power transformer in a lossless manner. This topology lends itself well to run at duty cycles exceeding 50%. The device may not be able to run at 100V under this topology. Figure 6 Active-Clamp Forward Converter
MPQ1924―100V, 4A HIGH FREQUENCY HALF-BRIDGE GATE DRIVER NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ1924 Rev. 1.0 www.MonolithicPower.com 14 12/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
PACKAGE INFORMATION
PACKAGE OUTLINE DRAWING FOR 8-SOIC MF-PO-D-0001, revision 3.0 0.016(0.41) 0.050(1.27)0o-8o DETAIL "A" 0.010(0.25) 0.020(0.50) x 45o SEE DETAIL "A" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00)PIN 1 ID 0.050(1.27) BSC 0.013(0.33) 0.020(0.51) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) TOP VIEW FRONT VIEW 0.228(5.80) 0.244(6.20) SIDE VIEW 1 4 8 5 RECOMMENDED LAND PATTERN 0.213(5.40) 0.063(1.60) NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA. 6) DRAWING IS NOT TO SCALE. 0.010(0.25) BSC GAUGE PLANE