MPQ1923GRE-AEC1

MPQ1923-AEC1 MPSIND | Alldatasheet

Document overview

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Technical content

100V, 8A, High-Frequency, Half-Bridge Gate Driver, AEC-Q100 Qualified MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 1 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

DESCRIPTION

The MPQ1923-AEC1 is a high -frequency, N - channel MOSFET, half -bridge gate driver. The device’s low-side MOSFET (LS -FET) and high - side MOSFET (HS -FET) driver channels are controlled independently, and are matched with <5ns in time delay. In the case of an insufficient supply, the device’s HS-FET and LS -FET under -voltage lockout (UVLO) protection forces the outputs low. The MPQ1923-AEC1 also features an integrated bootstrap (BST) diode to reduce the external component count. The MPQ1923-AEC1 is available in QFN -10 (4mmx4mm) and QFN-8 (4mmx4mm) packages.

FEATURES

• Drives an N-Channel MOSFET Half-Bridge
• Low Dropout with 4.5V Under-Voltage Lockout (UVLO) Falling Threshold
• 120V Bootstrap Voltage (VBST) Range
• On-Chip Bootstrap Diode
• 20ns Typical Propagation Delay
• 8A Sink Current, 7A Source Current at 12V VDD
• <5ns Gate Driver Matching Time Delay
• Drives a 1nF Load with 7.2ns Rise Time (tRISE) and 5.5ns Fall Time (tFALL) at 12V VDD
• TTL-Compatible Input
• <300µA Quiescent Current (IQ)
• UVLO Protection for the HS-FET and LS-FET Gate Drivers
• Available in QFN-10 (4mmx4mm) and QFN-8 (4mmx4mm) Packages
• Available in AEC-Q100 Grade 1

APPLICATIONS

• Motor Drivers
• Telecom Half-Bridge Power Supplies
• Avionics DC/DC Converters
• Two-Switch Forward Converters
• Active-Clamp Forward Converters All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION M VDC DRVH DRVL SW BST VSS VSS VDD VDD DRVH DRVL SW BST INH INL INH INL MOTOR DRIVER 12V MPQ1923- AEC1

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 2 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL Rating MPQ1923GRE-AEC1 QFN-10 (4mmx4mm) See Below 1 MPQ1923GR-AEC1 QFN-8 (4mmx4mm) See Below 1 * For Tape & Reel, add suffix -Z (e.g. MPQ1923GRE-AEC1-Z). TOP MARKING MPS: MPS prefix Y: Year code WW: Week code MP1923: Part number LLLLLL: Lot number E: MPQ1923GRE-AEC1 TOP MARKING MPS: MPS prefix Y: Year code WW: Week code MP1923: Part number LLLLLL: Lot number

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 3 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. PACKAGE REFERENCE (MPQ1923GRE-AEC1) TOP VIEW QFN-10 (4mmx4mm) PACKAGE REFERENCE (MPQ1923GR-AEC1) TOP VIEW 2 7 3 6 VDD BST DRVH SW DRVL VSS INL INH QFN-8 (4mmx4mm) 5 6 TOP VIEW EXPOSED PAD ON BACKSIDE VDD DRVH SW NC DRVL VSS INL INH NC BST 2

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 4 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description QFN-10 QFN-8 1 1 VDD Supply voltage. The VDD pin supplies power to the internal circuitry. Connect a decoupling capacitor between VDD and ground to ensure a stable and clean supply. 2 2 BST Bootstrap. The BST pin is the positive power supply for the internal floating high-side MOSFET (HS-FET) driver. Connect a bypass capacitor between the BST and SW pins. 3 3 DRVH Floating HS-FET driver output. 4 4 SW Switching node. 5, 6 NC Not connected. 7 5 INH Control signal input for the floating HS-FET driver. 8 6 INL Control signal input for the LS-FET driver. 9 7 VSS Chip ground. 10 8 DRVL LS-FET driver output. Pad Pad Exposed pad Exposed pad. Connect the exposed pad to the VSS pin to improve thermal operation. ABSOLUTE MAXIMUM RATINGS (1) ESD Ratings Recommended Operating Conditions (3) Operating junction temp (TJ) .... -40°C to +125°C Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can produce an excessive die temperature, which may cause the device to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 5 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VDD = VBST - VSW = 12V, V SS = VSW = 0V, no load at DRVH and DRVL, TA = -40°C to 125°C , unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Supply Currents VDD quiescent current IDD_Q VINL = VINH = 0V 130 300 µA VDD operating current IDD_OP fSW = 500kHz, CLOAD = 0nF 2.6 6 mA Floating driver quiescent current IBST_Q VINL = VINH = 0V 60 150 µA Floating driver operating current IBST_OP fsw = 500kHz, CLOAD = 0nF 2.6 6 mA BST to VSS quiescent current IBST-SS_Q VBST = VSW = 115V 0.05 1 µA BST to VSS operating current IBST-SS_OP fSW = 500kHz, CLOAD = 0nF 2.3 5.5 mA Leakage current ILKG VBST = VSW = 100V 0.05 1 µA Inputs INL and INH high voltage 2 2.4 V INL and INH low voltage 0.8 1.2 V Input voltage hysteresis 600 mV INL and INH internal pull-down resistance RINL 155 kΩ RINH 155 kΩ Under-Voltage Protection (UVLO) Protection VDD rising threshold VDD_RISING 4.6 5 5.4 V VDD falling threshold VDD_FALLING 4.1 4.5 4.9 V (BST - SW) rising threshold VBST_RISING 1.6 3.7 4.9 V (BST - SW) falling threshold VBST_FALLING 1.4 3.2 4.6 V Bootstrap Diode Bootstrap diode VF at 100μA VF1 0.5 0.9 V Bootstrap diode VF at 100mA VF2 1 1.2 V Bootstrap diode dynamic R RD IVDD-BST = 100mA and 80mA 3.1 6.5 Ω Low-Side MOSFET (LS-FET) Gate Driver Low-level output voltage VOLL IOUT = 100mA 0.02 0.07 0.2 V High-level output voltage to rail VOHL IOUT = -100mA 0.02 0.07 0.3 V Source current (5) IOHL VDRVL = 0V, VDD = 12V 7 A VDRVL = 0V, VDD = 16V 9 A Sink current (5) IOLL VDRVL = VDD = 12V 8 A VDRVL = VDD = 16V 10 A Floating High-Side MOSFET (HS-FET) Gate Driver Low level output voltage VOLH IOUT = 100mA 0.02 0.07 0.2 V High level output voltage to rail VOHH IOUT = -100mA 0.02 0.07 0.3 V Source current (5) IOHH VDRVH = 0V, VDD = 12V 7 A VDRVH = 0V, VDD = 16V 9 A Sink current (5) IOLH VDRVH = VDD = 12V 8 A VDRVH = VDD = 16V 10 A Switching Specifications (LS-FET Gate Driver) Turn-off propagation delay tDLFF CLOAD = 0nF, INL falling to DRVL falling 5 20 50 ns Turn-on propagation delay tDLRR CLOAD = 0nF, INL rising to DRVL rising 5 20 50 ns DRVL rise time tRISE_LS CLOAD = 1nF, from 10% to 90% 7.2 ns CLOAD = 0.1μF, from 3V to 9V 0.2 0.6 μs

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 6 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD = VBST - VSW = 12V, V SS = VSW = 0V, no load at DRVH and DRVL, TA = -40°C to 125°C , unless otherwise noted. Parameter Symbol Condition Min Typ Max Units DRVL fall time tFALL_LS CLOAD = 1nF, from 90% to 10% 5.5 ns CLOAD = 0.1μF, from 9V to 3V 0.15 0.4 μs Switching Specifications (Floating HS-FET Gate Driver) Turn-off propagation delay tDHFF CLOAD = 0nF, INH falling to DRVH falling 5 20 50 ns Turn-on propagation delay tDHRR CLOAD = 0nF, INH rising to DRVH rising 5 20 50 ns DRVH rise time tRISE_HS CLOAD = 1nF, from 10% to 90% 7.2 ns CLOAD = 0.1μF, (3V to 9V) 0.2 0.6 μs DRVH fall time tFALL_HS CLOAD = 1nF, from 90% to 10% 5.5 ns CLOAD = 0.1μF, (9V to 3V) 0.15 0.4 μs Switching Specifications (Matching) HS-FET driver turn-off to LS- FET driver turn-on time (5) tMON 1 5 ns LS-FET driver turn-off to HS- FET driver turn-on time (5) tMOFF 1 5 ns Minimum input pulse width to change the output (5) tPW 50 ns Bootstrap (BST) diode turn-on or turn-off time (5) tBST 10 ns Thermal shutdown 165 °C Thermal shutdown hysteresis 25 °C Note: 5) Guaranteed by design. TIMING DIAGRAM Figure 1: Timing Diagram INPUT (INH, INL) OUTPUT (DRVH, DRVL) TDHRR, TDLRR TDHFF, TDLFF INPUT (INH, INL) OUTPUT (DRVH, DRVL) TDHRR, TDLRR TDHFF, TDLFF INL INH DRVL DRVH TMON TMOFF tMOFF tMON tDHRR, tDLRR tDHFF, tDLFF

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 7 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VDD = 12V, VSS = VSW = 0V, TA = 25°C, unless otherwise noted. High-Level Output Voltage vs. Temperature Low-Level Output Voltage vs. Temperature UVLO Threshold vs. Temperature UVLO Hysteresis vs. Temperature Quiescent Current vs. Voltage Propagation Delay vs. Temperature 0.02 0.04 0.06 0.08 0.1 0.12 -50 0 50 100 150 HIGH-LEVEL OUTPUT VOLTAGE (V) TEMPERATURE (°C) VOHH VOHL 0.02 0.04 0.06 0.08 0.1 0.12 -50 0 50 100 150 LOW-LEVEL OUTPUT VOLTAGE (V) TEMPERATURE (°C) VOLH VOLL 3.5 4.5 5.5 -50 0 50 100 150 UVLO THRESHOLD (V) TEMPERATURE (°C) VDD_RISING VBST_RISING 350 400 450 500 550 -50 0 50 100 150 UVLO HYSTERISIS (mV) TEMPERATURE (°C) VDD_HYS VBST_HYS 100 120 140 160 4 6 8 10 12 14 16 18 QUIESCENT CURRENT (μA) VOLTAGE (V) IDD_Q vs. VDD IBST_Q vs. VBST -50 0 50 100 150 PROPAGATION DELAY (ns) TEMPERATURE (°C) tDHRR tDHFF tDLRR tDLFF

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 8 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VDD = 12V, VSS = VSW = 0V, TA = 25°C, unless otherwise noted. Peak Current vs. VDD Driver Current vs. Output Voltage 5 7 9 11 13 15 17 19 PEAK CURRENT (A) VDD (V) Source Current Sink Current 0 2 4 6 8 10 12 14 DRIVER CURRENT (A) VOUT (V) Source Current Sink Current

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 9 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VDD = 5V, VSS = VSW = 0V, TA = 25°C, unless otherwise noted. High-Level Output Voltage vs. Temperature Low-Level Output Voltage vs. Temperature Propagation Delay vs. Temperature 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 -50 0 50 100 150 HIGH-LEVEL OUTPUT VOLTAGE (V) TEMPERATURE (°C) VOHH VOHL 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 -50 0 50 100 150 LOW-LEVLE OUTPUT VOLTAGE (V) TEMPERATURE (°C) VOLH VOLL -50 0 50 100 150 PROPAGATION DELAY (ns) TEMPERATURE (°C) tDHRR tDHFF tDLRR tDLFF

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 10 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VDD = 12V, VSS = VSW = 0V, TA = 25°C, unless otherwise noted. Turn-On Propagation Delay CLOAD = 0nF, SW is connected to ground Turn-Off Propagation Delay CLOAD = 0nF, SW is connected to ground CH1: VINH/VINL CH2: VDRVH CH3: VDRVL CH1: VINH/VINL CH2: VDRVH CH3: VDRVL Gate Driver Matching (tMON) CLOAD = 0nF, SW is connected to ground Gate Driver Matching (tMOFF) CLOAD = 0nF, SW is connected to ground CH1: VINH CH2: VINL CH3: VDRVH CH4: VDRVL CH1: VINH CH2: VINL CH3: VDRVH CH4: VDRVL Gate Driver Rise Time CLOAD = 1nF, SW is connected to ground Gate Driver Fall Time CLOAD = 1nF, SW is connected to ground CH1: VINH/VINL CH2: VDRVH CH3: VDRVL CH1: VINH/VINL CH2: VDRVH CH3: VDRVL

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 11 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD = 5V, VSS = VSW = 0V, TA = 25°C, unless otherwise noted. Turn-On Propagation Delay CLOAD = 0nF, SW is connected to ground Turn-Off Propagation Delay CLOAD = 0nF, SW is connected to ground CH1: VINH/VINL CH2: VDRVH CH3: VDRVL CH1: VINH/VINL CH2: VDRVH CH3: VDRVL Gate Driver Matching (tMON) CLOAD = 0nF, SW is connected to ground Gate Driver Matching (tMOFF) CLOAD = 0nF, SW is connected to ground CH1: VINH CH2: VINL CH3: VDRVH CH4: VDRVL CH1: VINH CH2: VINL CH3: VDRVH CH4: VDRVL Gate Driver Rise Time CLOAD = 1nF, SW is connected to ground Gate Driver Fall Time CLOAD = 1nF, SW is connected to ground CH1: VINH/VINL CH2: VDRVH CH3: VDRVL CH1: VINH/VINL CH2: VDRVH CH3: VDRVL

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 12 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM Figure 2: Functional Block Diagram

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 14 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

APPLICATION INFORMATION

The INH and INL input signals can be controlled independently. If both INH and I NL control the HS-FET and LS -FET of the same bridge, set a sufficient DT between the low INH and INL signals (and vice versa) to avoid shoot -through. DT is the time interval between low INH and low INL. Figure 3 shows the shoot -through timing diagram. PCB Mounting To comply with IPC-2221 or IPC-9592 standards, conformal coating is required after mounting the device on the PCB. Figure 3: Shoot-Through Timing Diagram

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 15 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. PCB Layout Guidelines Efficient PCB layout is critical for stable operation. The MPQ1923-AEC1 is designed to accommodate negative undershoot ; however, excessive undershoot can lead to unpredictable operation or damage to the IC. For the best results, refer to Figure 4 and follow the guidelines below: 1. Connect the HS-FET source and the LS-FET drain using a short and direct trace to avoid negative undershoot on the phase node due to parasitic inductance. 2. Use surface -mount N -channel MOSFETs that allow for a very short conn ection between the HS-FETs and LS-FETs. 3. Place the bootstrap capacitor (C3) and the supply bypass capacitor (C2) as close to the IC as possible. 4. Connect the ground side of C3 and C2 to both the GND pin and the exposed pad using multiple vias. The ground sid e of the capacitors are connected to a solid ground plane. 5. Route the high-current ground path between the input supply, the input bulk capacitor (C6), and the MOSFETs. Route this path away from the IC. Figure 4: Recommended PCB Layout

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 17 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-10 (4mmx4mm) SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID SEE DETAIL A PIN 1 ID OPTION A 0.30x45° TYP. PIN 1 ID OPTION B R0.25 TYP. DETAIL A

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 18 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. PACKAGE INFORMATION (continued) QFN-8 (4mmx4mm) PACKAGE OUTLINE DRAWING FOR 8L QFN (4X4MM) -2 MF-PO-D-0374 revision 0.0 SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID 0.30X45° TYP

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 19 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved. CARRIER INFORMATION QFN-10 and QFN-8 Part Number Package AEC1-Z QFN-10 (4mmx4mm) 5000 N/A 13in 12mm 8mm MPQ1923GR- AEC1-Z QFN-8 (4mmx4mm) 5000 N/A 13in 12mm 8mm Pin1 1 1 1 1 ABCD ABCD ABCD ABCD Feed Direction

MPQ1923-AEC1 – 100V, 8A, HIGH-FREQUENCY, HALF-BRIDGE DRIVER, AEC-Q100 Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ1923-AEC1 Rev. 1.1 MonolithicPower.com 20 7/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2023 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 8/19/2022 Initial Release - 1.1 7/18/2023 Updated all headers with AEC-Q100; formatting updates All Updated footers with MPQ1923-AEC1 All Updated all mentions of MPQ1923 to MPQ1923-AEC1 All

• Updated the Ordering Information section
• Updated the Top Marking section 2 Updated the Carrier Information section 19

Click to View Pricing, Inventory, Delivery & Lifecycle Information: Monolithic Power Systems (MPS): MPQ1923GR-AEC1-P MPQ1923GR-AEC1-Z MPQ1923GRE-AEC1-P MPQ1923GRE-AEC1-Z