MPQ1530 MPS | Alldatasheet
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Technical content
Plus Linear Regulators for TFT Bias AEC-Q100 Qualified MPQ1530 Rev. 1.02 www.MonolithicPower.com 1 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
DESCRIPTION
The MPQ1530 combines a triple output step-up converter with linear regulators to provide a complete DC/DC solution. It is designed to power TFT LCD panels from a regulated 3.3V or 5V supply. This device integrates a 1.4MHz fixed-frequency step -up converter with positive and negative linear regulators. The step -up converter switch node drives two charge pumps, which supply powers to their respective linear regulators. The positive and negative linear regulator inputs can withstand up to 38V and down to -20V, respectively. A single on/off control enables all 3 outputs. The outputs are internally sequenced at startup for ease of use. An internal soft -start prevents input overload at startup. Cycle-by-cycle current limiting reduces component stress. The MPQ1530 is available in a tiny 3x3mm, 16 - pin QFN package.
FEATURES
Guaranteed Industrial/Automotive Temp Range Limits 2.7 to 5.5V Operating Input Range 2.8A Switch Current Limit 3 Outputs In a Single Package Step-Up Converter up to 22V Positive 20mA Linear Regulator Negative 20mA Linear Regulator 250mΩ Internal Power MOSFET Switch Up to 95% Efficiency 1.4MHz Fixed Frequency Internal Power-On Sequencing Adjustable Soft-Start/Fault Timer Cycle-by-Cycle Over Current Protection Under Voltage Lockout Ready Flag 16-Pin QFN (3x3mm) Package Available in AEC-Q100 Qualified Grade 1
APPLICATIONS
TFT LCD Displays Portable DVD Players Tablet PCs Car Navigation Displays All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 2 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number Package Top Marking MPQ1530DQ* QFN16 (3x3mm) B8 MPQ1530DQ-AEC1** * For Tape & Reel, add suffix -Z (e.g. MPQ1530DQ-Z). For RoHS Compliant Packaging, add suffix -LF (e.g. MPQ1530DQ-LF-Z) ** For Tape & Reel, add suffix -Z (e.g. MPQ1530DQ-AEC1-Z). For RoHS Compliant Packaging, add suffix -LF (e.g. MPQ1530DQ-AEC1-LF-Z) PACKAGE REFERENCE QFN16 ABSOLUTE MAXIMUM RATINGS (1) Continuous Power Dissipation (TA = +25° C) (2) ESD Susceptibility (3) HBM (Human Body Mode)
- IN3: CLASS 1A;
- GH: CLASS 1B;
- GL: CLASS 1C;
- Other Pins: CLASS 2; CDM (Charged Device Mode)
- All Pins: CLASS IV; Recommended Operating Conditions (4) Operating Junction Temp. (TJ). -40°C to +125°C Thermal Resistance (5) θJA θJC Notes: 1) Absolute maximum are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Devices are ESD sensitive. Handle with precaution. 4) The device is not guaranteed to f unction outside of its operating conditions. 5) Measured on approximately 1” square of 1 oz copper.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 3 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (6) VIN = 5V, TJ = -40C to +125C, Typical value are at TJ = +25C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Input Voltage Range VIN 2.7 5.5 V IN Undervoltage Lockout Threshold VUVLO IN Rising 2.25 2.65 V IN Undervoltage Lockout Hysteresis 100 mV IN Shutdown Current VEN 0.3V 0.5 1 μA IN Quiescent Current VEN > 2V, VFB1 = 1.4V 1.3 1.6 mA EN Input High Voltage VEN HIGH EN Rising 1.6 V EN Input Low Voltage 0.3 V EN Hysteresis 250 mV EN Input Bias Current 1 μA Oscillator Switching Frequency fSW 1 1.4 MHz Maximum Duty Cycle DM 85 90 % Soft Start Period CCT = 10nF 6 ms Regulator #2 Turn-On/Turn-Off Delay 3 μs CCT = 10nF 6 ms Error Amplifier Error Amplifier Voltage Gain(6) AvEA 400 V/V Error Amplifier Transconductance GmEA 1000 μA/V COMP Maximum Output Current ± 100 μA FB1, FB3 Regulation Voltage 1.22 1.25 1.28 V FB2 Regulation Voltage –25 0 +25 mV FB1, FB3 Input Bias Current VFB1 = VFB3 = 1.25V ± 100 nA FB2 Input Bias Current VFB2 = 0V ± 100 nA Reference (REF) REF Regulation Voltage IREF = 50μA 1.22 1.25 1.28 V REF Load Regulation 0μA < IREF < 200μA 1 1.2 % Output Switch (SW) SW On Resistance(6) VIN = 5V 250 mΩ VIN = 3V 400 mΩ SW Current Limit ILIM TJ=+25oC 2.5 3.6 A TJ=-40oC to +125oC 2.2 3.6 SW Leakage Current VSW = 22V 0.5 1 μA GL Dropout Voltage (7) VGL = –10V, IGL = –20mA 0.1 0.3 V GH Dropout Voltage (7) VGH = 20V, IGH = 20mA 0.45 1 V GL Leakage Current VIN2 = –15V, VGL = GND 1 μA GH Leakage Current VIN3 = 25V, VGH = GND 1 μA Thermal Shutdown(6) 160 C Notes: 6) Not production tested. 7) Dropout Voltage is the input to output differential at which the circuit ceases to regulate against further reduction in input voltage.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 4 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V, IGH = 10mA, TA = +25C, unless otherwise noted.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 5 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V, IGH = 10mA, TA = +25C, unless otherwise noted.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 6 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. PIN FUNCTIONS QFN Pin # Name Description 1 SW Step-Up Converter Power Switch Node. Connect an inductor between the input source and SW, and connect a rectifier from SW to the main output to complet e the step-up converter. SW is the drain of the internal 250mΩ N-Channel MOSFET switch. 2 CT Timing Capacitor for Power Supply Soft-Start and Power-On Sequencing. A capacitor from CT to GND controls the soft-start and sequencing turn-on delay periods. See Power-On Sequencing and Start Up Timing Diagram. RDY Regulators Not Ready. During startup RDY will be left high. Once the turn -on sequence is complete, this pin will be pulled low if all FB voltages exceed 80% of their specified thresholds. After all regulators are turned-on, a fault in any regulator that causes the respective FB voltage to fall below 80% of its threshold will cause RDY to go high after approximately 15μs. If the fault persists for more than approximately 6ms (for CCT=10nF), the entire chip will shut down. See Fault Sensing and Timer.
4 FB1
Step-Up Converter Feedback Input. FB1 is the inverting input of the internal error amplifier. Connect a resistive voltage divider from the output of the step -up converter to FB1 to set the step -up converter output voltage. 5 COMP Step-Up Converter Compensation Node. COMP is the output of the error amplifier. Connect a series RC network to compensate the regulation control loop of the step-up converter. 6 IN Internal Power Input. IN supplies the power to the MPQ1530. Bypass IN to PGND with a 10μF or greater capacitor. 7 GND Signal Ground.
8 REF
Reference Output. REF is the 1.25V reference voltage output. Bypass REF to GND with a 0.1μF or greater capacitor. Connect REF to the low-side resistor of the negative linear regulator feedback string. 9 FB2 Negative Linear Regulator Feedback Input. Connect the FB2 feedback resistor string between GL and REF to set the negative linear regulator output voltage. FB2 regulation threshold is GND. 10 FB3 Positive Linear Regulator Feedback Input. Connect the FB3 feedback resistor string between GH and GND to set the positive linear regulator output voltage. FB3 regulation threshold is 1.25V. 11 EN On/Off Control Input. Drive EN high to turn on the MPQ1530, drive EN low to turn it off. For automatic startup, connect EN to IN. Once the MPQ1530 is turned on, it sequences the outputs on (See Power-On Sequencing). When turned off, all outputs are immediately disabled. 12 GL Negative Linear Regulator Output. GL is the output of the negative linear regulator. GL can supply up to 20mA to the load. Bypass GL to GND with a 1μF or greater, low-ESR, ceramic capacitor.
13 IN2
Negative Linear Regulator Input. IN2 is the input of the negative linear regulator. Drive IN2 with an inverting charge pump powered from SW. IN2 can go as low as -20V. For QFN package, connect the exposed pad to IN2 pin. 14 GH Positive Linear Regulator Output. GH is the output of the positive linear regulator. GH can supply as much as 20mA to the load. Bypass GH to GND with a 1μF or greater, low-ESR, ceramic capacitor. 15 IN3 Positive Linear Regulator Input. IN3 is the input to the positive linear regulator. Drive IN3 with a doubling, tripling, or quadrupling charge pump from SW. IN3 voltage can go as high as 38V. 16 PGND Power Ground. PGND is the source of the internal 250mΩ N -Channel MOSFET switch. Connect PGND to GND as close to the MPQ1530 as possible. Pad Expos ed pad No internal electrical connections. Solder it to the lowest potential (IN2 pin) plane to reduce thermal resistance.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 7 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. BLOCK DIAGRAM Figure 1—Functional Block Diagram
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 8 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. OPERATION The MPQ1530 is a step -up converter with two integrated linear regulators to power TFT LCD panels. Typically the linear regulators are powered from charge -pumps driven from the switch node (SW). The user can set the positive charge-pump to be a doubler, tripler, or quadrupler to achieve the required linear regulator input voltage for the selected output voltage. Typically the negative charge -pump is configured as a 1x inverter. Step-Up Converter The step-up, fixed-frequency, 1.4MHz converter employs a current -mode control architecture that maximizes loop bandwidth to provide fast - transient responses needed for TFT LCD drivers. High switching frequency allows for smaller inductors and capacitors minimizing board space and thickness. Linear Regulators The positive l inear regulator ( GH) uses a PChannel pass element to drop the input voltage down to the regulated output voltage. The feedback of the positive linear regulator is a conventional error amplifier with the regulation threshold at 1.25V. The negative linear r egulator ( GL) uses a NChannel pass element to raise the negative input voltage up to the regulated output voltage. The feedback threshold for the negative linear regulator is ground. The resistor string goes from REF (1.25V) to FB2 and from FB2 to GL to set the negative output voltage. The difference between the voltage at IN3 and the voltage at IN2 is limited to 60V abs. max. Fault Sensing and Timer Each of the 3 outputs has an internal comparator that monitors its respective output voltage by measuring t he voltage at its respective FB input. When any FB input indicates that the output voltage is below approximately 80% of the correct regulation voltage, the fault timer enables and the RDY pin goes high. The fault timer uses the same CT capacitor as the soft-start sequencer. If any fault persists to the end of the fault timer (One CT cycle is 6ms for a 10nF capacitor), all outputs are disabled. Once the outputs are shut down due to the fault timer, the MPQ1530 must be re -enabled by either cycling EN or by cycling the input power. If the fault persists for less than the fault timer period, RDY will be pulled low and the part will function as though no fault has occurred. Power-On Sequencing and Soft-Start The MPQ1530 automatically sequences its outputs at startup. When EN goes from low to high, or if EN is held high and the input voltage IN rises above the under -voltage lockout threshold, the outputs turn on in the following sequence: 1. Step-up Converter 2. Negative Linear Regulator (GL) 3. Positive Linear Regulator (GH) Each output turns on with a soft -start voltage ramp. The soft -start ramp period is set by the timing capacitor connected between CT and GND. A 10nF capacitor at CT sets the soft -start ramp period to 6ms. The timing diagram is shown in Figure 2. After the MPQ1530 is enabled, the power -on reset spans three periods of the CT ramp. First the step -up converter is powered up with reference to the CT ramp and allowed one period of the CT ramp to settle. Next the negative linear regulator ( GL) is soft -started by ramping REF, which coincides with the CT ramp, and also allowed one CT ramp period to settle.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 9 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. The positive linear regulator (GH) is then soft - started and allowed to settle in one period of CT ramp. Nine period s of the CT ramp have occurred since the chip enabled. If all outputs are in regulation (>80%), the CT will stop ramping and be held at ground. The RDY pin will be pulled down to an active low. If any output remains below regulation (<80%) before and through the nine CT periods, RDY will remain high and CT will begin its fault timer pulse. Figure 2—Startup Timing Diagram
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 10 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltages Set the output volta ge on each output by selecting the resistive voltage divider ratio. The voltage divider drops the output voltage to the feedback threshold voltage. Use 10k Ω to 50kΩ for the low-side resistor RL of the voltage divider. For the step -up converter, determine t he high- side resistor RH by the equation: L 1FB 1FBMAIN H R V VVR Where VMAIN is the output voltage of the step-up converter. For the positive charge -pump, determine the high-side resistor RH by the equation: L 3FB 3FBGH H R V VVR For the negative charge -pump, determine the high-side resistor RH by the equation: L REF GL H R V VR Selecting the Inductor The inductor is required to force the higher output voltage while being driven by the input voltage. A larger value inductor results in less ripple current that results in lower peak inductor current, reducing stress on the internal NChannel.switch. However, the larger value inductor has a larger physical size, higher series resistance, and/or lower saturation current. A 4.7 µ H inductor is recommended for most applications. A good rule of thumb is to allow the peak -to-peak ripple current to be approximately 30 -50% of the maximum input current. Make sure that the peak inductor current is below 75% of the current limit to prevent loss of regulation due to the current limit. Also make sure that the inductor does not saturate under the worst -case load transient and startup conditions. Calculate the required inductance value by the equation: I f V ) V-(V VL SW OUT INOUTIN IN )M AX(LOADOUT )M AX(IN V IV I Where I LOAD(MAX) is the maximum load current, ΔI is the peak -to-peak inductor ripple current, and η is efficiency. Selecting the Input Capacitor An input capacitor is required to supply the AC ripple current to the inductor, while limiting noise at the input source. A low ESR capacitor is required to keep the noise at the IC to a minimum. Since it absorbs the input switching current it requires an adequate ripple current rating. Use a capacitor with RMS current rating greater than the inductor ripple current (see selecting the Inductor to determine the inductor ripple current). One 10 μF ceramic capacitor is used in the application circuit of Figure 3 because of the high source impedance seen in typical lab setups. Actual applications usually have much lower source impedance since the step-up converter typically runs directly from the output of another regulated supply. Typically, the input capacitance can be reduced below the value used in the typical application circuit. To insure stable operation place the input capacitor as close to the IC as possible. Alternately a smaller high quality 0.1μF ceramic capacitor may be placed closer to the IC if the larger capacitor is placed further away.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 11 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Selecting the Rectifier Diodes The MPQ1530’s high switching frequency demands high-speed rectifiers. Schottky diodes are recommended for most applic ations because of their fast recovery time and low forward voltage. Typically, a 1A Schottky diode is recommended for the step -up converter. 100mA Schottky diodes such as Central Semiconductor CMPSH -3 are recommended for low current charge-pump circuits. Selecting the Output Capacitor of the Step Up Converter The output capacitor is required to maintain the DC output voltage. Low ESR capacitors are preferred to keep the output voltage ripple to a minimum. The characteristics of the output capacitor also aff ect the stability of the regulation control system. A 10μF ceramic capacitor works well in most applications. In the case of ceramic capacitors, the impedance of the capacitor at the switching frequency is dominated by the capacitance, and so the output vo ltage ripple is mostly independent of the ESR. The output voltage ripple is estimated to be: SW LOAD M AIN IN RIPPLE f2C I V V1V Where VRIPPLE is the output ripple voltage, I LOAD is the load current, and C2 is the capacitance of the output capacitor of the step-up converter. Selecting the Number of Charge -Pump Stages For highest efficiency, always choose the lowest number of charge -pump stages that meets the output requirement. The number of positive charge -pump stages NPOS is given by: DM AIN M AINDROPOUTGH POS V2V VVVN Where V D is the forward voltage drop of the charge-pump diode, and V DROPOUT is the dropout margin for the linear regulator. The number of negative charge -pump stages NNEG is given by: DM AIN DROPOUTGL NEG V2V VVN Use V DROPOUT = 1V for positive charge -pump and VDROPOUT = 0.3V for negative charge-pump. Selecting the Flying Capacitor in Charge- Pump Stages Increasing the flying capacitor C X values increases the output current capability. A 0.1μF ceramic capacitor works well in most low current applications . The flying capacitor’s voltage rating must exceed the following: M AINCX VNV Where N is the stage number in which the flying capacitor appears. Step-Up Converter Compensation The MPQ1530 uses current mode control which unlike voltage mode has only a single pole roll off due to the output filter. The DC gain (AVDC) is equated from the product of current control to output gain ( AVCSCONTROL), error amplifier gain (AVEA), and the feedback divider. 1FBEACSCONTROLDC AAvAAv LOAD IN CSCONTROL I V4A MAIN 1FB 1FB V VA M AINLOAD 1FBIN DC VI VV1600Av The output filter pole is given in hertz by: 2CV If M AIN LOAD FILTERPOLE The output filter zero is given in hertz by: 2CR2 ESR FILTERZERO Where RESR is the output capacitor’s equivalent series resistance.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 12 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. With all boost regulators the right half plane zero (RHPZ) is given in hertz by: 1LI2 VV V f LOAD MAIN MAIN IN RHPZ Error Amplifier Compensation To stabilize the feedback loop dynamics the error amplifier compensation is as follows: 3C102 1f 61POLE 3C3R2 1f 1ZERO Where R3 and C3 are part of the compensation network in Figure 3. A 6.8k Ω and 10nF combination gives about 70 of phase margin and bandwidth of about 35kHz for most load conditions. Linear Regulator Compensation The positive and negative regulators are controlled by a transconductance amplifier and a pass transistor. The DC ga in of either LDO is approximately 100dB with a slight dependency on load current. The output capacitor (CLDO) and resistance load (R LOAD) make -up the dominant pole. LDOLOAD 1LDOPOLE CR2 1f The pass transistor’s internal pole is about 100Hz to 3 00Hz. To com pensate for the two pole system and add more phase and gain margin, a capacitor network can be added in parallel with the high-side resistor. For the positive linear regulator: 7C8R9R2 1f 1POSPOLE 7C9R2 1f 1POSZERO For the negative linear regulator: 9C5R7R2 1f 1NEGPOLE 9C7R2 1f 1NEGZERO fPOSPOLE1 and f NEGPOLE1 are necessary to cancel out the zero created by the equivalent series resistance (RLDOESR) of the output capacitor. LDOLDOESR LDOZERO CR2 1f For the component values shown in Fig ure 3, a 330pF capacitor provides about 30 of phase margin and a bandwidth of approximately 90kHz on both regulators. Layout Considerations Careful PC board layout is important to minimize ground bounce and noise. First, place the main boost converter ind uctor, output diode and output capacitor as close to the SW and PGND pins as possible with wide traces. Then place ceramic bypass capacitors near IN, IN2 and IN3 pins to the PGND pin. Keep the charge-pump circuitry close to the IC with wide traces. Place all FB resistive dividers close to their respective FB pins. Separate GND and PGND areas and connect them at one point as close to the IC as possible. Avoid having sensitive traces near the SW node and high current lines. Refer to the MPQ1530 demo board for an example of proper board layout.
7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Figure 3. The typical performa nce and circuit Evaluation Board Datasheets.
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED MPQ1530 Rev. 1.02 www.MonolithicPower.com 14 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUITS Figure 3—Triple Output Boost Application Circuit
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party I ntellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ1530 Rev.1.02 www.MonolithicPower.com 15 7/14/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved.
PACKAGE INFORMATION
QFN16 (3 x 3mm)