MPM4730

MPM4730 MPS | Alldatasheet

Document overview

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Technical content

2.8V to 22V VIN, Max 1A, 4-Switch Integrated Buck-Boost Module MPM4730 Rev. 1.0 MonolithicPower.com 1 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

DESCRIPTION

The MPM4730 is a synchronous, four -switch integrated buck-boost module with a 2.8V to 22V input voltage (V IN) range. The device regulates the output voltage (VOUT) with high efficiency, and provides integrated VOUT scaling and output current (IOUT) limit functions. The MPM4730 uses constant -on-time (COT) control in buck mode and constant -off-time control in boost mode, providing a fast load transient response and smooth buck -boost mode transient s. The MPM4730 features automatic pulse -frequency modulation (PFM)/pulse-width modulation ( PWM) or forced PWM switching modes. It also provides a selectable switching frequency (fSW) and configurable soft start. Full protection features include over -current protection (OCP), over -voltage protection (OVP), under-voltage protection (UVP), and thermal shutdown. The MPM4730 is available in a n ECLGA-18 (3mmx3mm) package.

FEATURES

2.8V to 22V Operating Input Voltage (VIN) Range
0.08V to 1.637V Reference Voltage (VREF) Range with 0.8mV Resolution via the I2C (1) (Default 1V VREF)
Configurable Output Voltage (VOUT) via the FB Pin
1A Max Output Current (IOUT)
500kHz/750kHz Selectable Switching Frequency (fSW)
Output Over-Voltage Protection (OVP) and Short-Circuit Protection (SCP) with Hiccup Mode
Over-Temperature Warning (OTW) and Shutdown
I2C Interface with ALT Pin
One-Time Programmable (OTP) Non- Volatile Memory (NVM)
I2C-Configurable Pulse-Frequency Modulation (PFM)/Pulse-Width Modulation (PWM) Mode, Soft Start, Over-Current Protection (OCP), and OVP
Configurable EN Shutdown Discharge
Available in an ECLGA-18 (3mmx3mmx1.86mm) Package

APPLICATIONS

Server Power Supply Units (PSUs)
Buck-Boost Bus Supplies All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. Note: 1) For applications where V OUT is below 3V, the switching frequency decreases.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 2 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL APPLICATION MPM4730 GND EN VIN AGND SW1VIN = 12V VCC 1µF SDA COUT 22µF x 5 100µF C1A 22µF SW2BST2 SCL I2C Slave OUT OC FB BST1 ALT 21.5kΩ 22nF 499kΩ VOUT = 15V 22nF 42.2kΩ 3kΩ RT 49.9kΩ 100 0 0.5 1 EFFICIENCY (%) LOAD CURRENT (A) Efficiency vs. Load Current VIN = 12V, fSW = 500kHz, FCCM VOUT=15V

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 3 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL MPM4730GPQ- xxxx** ECLGA-18 (3mmx3mmx1.86mm) See Below 3 MPM4730GPQ-0000 ECLGA-18 (3mmx3mmx1.86mm) See Below 3 * For Tape & Reel, add suffix -Z (e.g. MPM4730GPQ-xxxx-Z). ** The 4-digit suffix code “xxxx” is the configuration identifier for the register settings stored in the multiple-time programmable (MTP) memory. For the default configuration, the code is “0000”. See Table 2 on page 30 and Table 3 on page 30 for the detailed configuration information. For customized configurations, contact an MPS FAE to assign a 4-digit suffix code. TOP MARKING BXL: Product code of MPM4730GPQ Y: Year code LLL: Lot number PACKAGE REFERENCE TOP VIEW VCC FB OC SDA SCL ALT EN GND VIN BST1SW1SW1SW2SW2BST2 VOUT GND AGND 1 4 5 6 7 8 9 131415161718 ECLGA-18 (3mmx3mm)

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 4 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 AGND Analog ground. Connect AGND to GND. 2, 11 GND Power ground. The GND pin is the reference ground of the regulated output voltage (VOUT). GND requires extra consideration during PCB layout. Connect GND with copper traces and vias. 3 VOUT Output power pin. Place the output capacitor close to VOUT and GND. 4 BST2 Test pin. The BST2 pin can be floated. 5, 6 SW2 Test pin. The internal switches are connected to SW2. This is a test pin that can be floated. 7, 8 SW1 Test pin. The internal switches are connected to SW1. This is a test pin that can be floated. 9 BST1 Test pin. The BST1 pin can be floated.

10 VIN

Supply voltage. The VIN pin is the drain of the internal power device, and it provides power to the entire chip. The MPM4730 operates from a 2.8V to 22V input voltage (VIN). An input capacitor (CIN) is required to prevent large voltage spikes from appearing at the input. Place CIN as close to the IC as possible. 12 EN On/off control for the entire chip. Drive the EN pin high to turn the device on. Drive EN low or float EN to turn it off. EN has an internal 2MΩ pull-down resistor connected to ground. 13 ALT Alert output. If the ALT pin pulls to logic low, a fault or warning has occurred. 14 SCL Clock pin of the I2C interface. The SCL pin can support an I2C clock up to 3.4MHz. If not used, SCL should be pulled up to VCC. 15 SDA Data pin of the I2C interface. If the SDA pin is not used, SDA should be pulled up to VCC. 16 OC Output constant current limit setting pin. 17 FB Feedback. An external resistor divider from the output to AGND (tapped to FB) sets VOUT. 18 VCC Internal 3.65V low-dropout (LDO) regulator output. Decouple the VCC pin with a 1µF capacitor.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 5 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (2) Continuous power dissipation (TA = 25°C) (3) (6) ESD Ratings (4) Recommended Operating Conditions (5) Operating input voltage (VIN) range……………... Operating junction temp (TJ) .... -40°C to +125°C Thermal Resistance θJA θJC ECLGA-18 (3mmx3mm) Notes: 2) Exceeding these ratings may damage the device. 3) The maximum allowable power dissipation is a function of the maximum junction temperature , TJ (MAX), the junction -to- ambient thermal resistance , θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can produce an excessive die temperature, and the regulator may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) HBM, per JEDEC specification JESD22 -A114; CDM, per JEDEC specification JESD22 -C101. The JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. The JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. 5) The device is not guaranteed to function outside of its operating conditions. 6) Measured on the MPM4730 evaluation board, a 4-layer PCB, 51mmx51mm.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 6 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 12V, VEN = 5V, TJ = -40°C to +125°C (7), typical value is tested at T J = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Shutdown supply current IIN VEN = 0V 0 3 μA Quiescent supply current IQ Non-switching, I2C sets PFM mode 1 mA EN rising threshold VEN_RISING 1 1.1 1.2 V EN hysteresis VEN_HYS 110 mV EN-to-ground resistance REN VEN = 2V 2 MΩ EN on to output voltage (VOUT) > 90% delay tDELAY See Figure 9 on page 18 3.6 ms VCC regulator VCC 3.3 3.65 4 V VCC load regulation VCC_LOG ICC = 10mA 1 % Input voltage (VIN) under- voltage lockout (UVLO) rising threshold VIN_UVLO 2.5 2.65 2.8 V VIN UVLO threshold hysteresis VUVLO_HYS 160 mV Power Converter Feedback voltage VFB TJ = 25°C -1% 1000 +1% mV % mV Feedback current IFB VFB = 1.05V 10 nA Output discharge resistance RDIS 60 100 Ω Switch leakage ISWLKG VEN = 0V, VSW1/SW2 = 22V, TJ = 25°C 1 μA Oscillator frequency fSW1 Set FREQ = 500kHz via I2C, TJ = 25°C -20% 520 +20% kHz fS2W Set FREQ = 750kHz via I2C, TJ = 25°C 750 kHz Minimum on time (8) tON_MIN1 Switch A, B, C, D 160 ns Maximum duty cycle (8) DMAX Buck mode, FREQ = 500kHz 85 % Minimum duty cycle (8) DMIN Boost mode, FREQ = 500kHz 15 % Soft-start time tSS Can be changed by I2C, VREF from 0V to 1V, default SS time 3.5 ms Protections Output over-voltage protection (OVP) VOVP_R 150% 160% 170% VREF Output OVP recovery VOVP_F 130% 140% 150% VREF Output current (IOUT) limit threshold (8) IOUT_LIMT 2 A Output under-voltage (UV) threshold VUVP 20µs deglitch, UV falling 45% 50% 55% VREF ALT sink current capability VALT_LOW Sink 4mA 0.2 0.4 V

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 7 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VEN = 5V, TJ = -40°C to +125°C (7), typical value is tested at T J = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units ALT leakage IALT_LKG VPULL = 5V 1 μA Thermal shutdown rising threshold (8) TSTD 150 °C Thermal hysteresis (8) TSTD_HYS 20 °C I2C Specifications (8) Input logic high VIH I2C pull-up VDD can be 1.8V to 5V 1.4 V Input logic low VIL 0.4 V Output voltage logic low VOUT_L Sink current = 4mA 0.4 V SCL clock frequency fSCL 400 3400 kHz SCL high time tHIGH 60 ns SCL low time tLOW 160 ns Data set-up time tSU_DAT 10 ns Data hold time tHD_DAT 0 60 ns Set-up time for (repeated) start command tSU_STA 160 ns Hold time for (repeated) start command tHD_STA 160 ns Bus free time between a start and a stop command tBUF 160 ns Set-up time for stop command tSU_STO 160 ns SCL and SDA rising time tR 10 300 ns SCL and SDA falling time tF 10 300 ns Pulse width of suppressed spike tSP 0 50 ns Capacitance for each bus line CB 400 pF Notes: 7) Not tested in production. Guaranteed by over-temperature (OT) correlation. 8) Guaranteed by engineering sample characterization.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 8 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS Performance waveforms are tested on the evaluation board. VIN = 12V, VOUT = 5V, FCCM, fSW = 500kHz, TA = 25°C, unless otherwise noted. 100 0 0.5 1 1.5 EFFICIENCY (%) LOAD CURRENT (A) Efficiency vs. Load Current VIN = 12V, fSW = 500kHz, FCCM VOUT=3.3V VOUT=5V VOUT=9V VOUT=12V VOUT=15V VOUT=20V 0.2 0.4 0.6 0.8 1.2 1.4 1.6 60 70 80 90 100 110 120 LOAD CURRENT(A AMBIENT TEMPERATURE ( C) Thermal Derating VIN = 12V, fSW = 500kHz, no airflow VOUT=3.3V VOUT=5V VOUT=9V VOUT=12V VOUT=15V VOUT=20V 0.2 0.4 0.6 0.8 1.2 1.4 1.6 0 2 4 6 8 10 12 14 16 18 20 22 24 IO_MAX (A) INPUT VOLTAGE (V) IO_MAX vs. Input Voltage 22µF x 5 ceramic COUT capacitor VOUT=20V VOUT=15V VOUT=12V VOUT=9V VOUT=5V VOUT=3.3V -0.15 -0.1 -0.05 0.05 0.1 LOAD REGULATION (%) LOAD CURRENT (A) Load Regulation VIN = 12V VOUT=3.3V VOUT=5V VOUT=9V VOUT=12V VOUT=15V VOUT=20V 0 0.5 1 0.2 0.4 0.6 0.8 1.2 1.4 1.6 60 70 80 90 100 110 120 LOAD CURRENT (A) AMBIENT TEMPERATURE ( C) Thermal Derating VIN = 12V, fSW = 500kHz, with airflow VOUT=3.3V VOUT=5V VOUT=9V VOUT=12V VOUT=15V VOUT=20V -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 LINE REGULATION (%) INPUT VOLTAGE (V) Line Regulation VOUT = 3.3V IOUT=0.0A IOUT=0.5A IOUT=1A

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 9 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board. VIN = 12V, VOUT = 5V, FCCM, fSW = 500kHz, TA = 25°C, unless otherwise noted. -0.8 -0.6 -0.4 -0.2 0.2 0.4 LINE REGULATION (%) INPUT VOLTAGE (V) Line Regulation VOUT = 5V IOUT=0.0A IOUT=0.5A IOUT=1A -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 LINE REGULATION (%) INPUT VOLTAGE (V) Line Regulation VOUT = 9V IOUT=0.0A IOUT=0.5A IOUT=1A -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 LINE REGULATION (%) INPUT VOLTAGE (V) Line Regulation VOUT = 12V IOUT=0.0A IOUT=0.5A IOUT=1A -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 LINE REGULATION (%) INPUT VOLTAGE (V) Line Regulation VOUT = 15V IOUT=0.0A IOUT=0.5A IOUT=1A -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 LINE REGULATION (%) INPUT VOLTAGE (V) Line Regulation VOUT = 20V IOUT=0.0A IOUT=0.5A IOUT=1A

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 10 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board. VIN = 12V, VOUT = 5V, FCCM, fSW = 500kHz, TA = 25°C, unless otherwise noted. EN Bit Enabled via the I2C IOUT = 0A EN Bit Enabled via the I2C IOUT = 1A CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. EN Bit Shutdown via the I2C IOUT = 0A EN Bit Shutdown via the I2C IOUT = 1A CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. EN Pin Enabled IOUT = 0A EN Pin Enabled IOUT = 1A CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 11 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board. VIN = 12V, VOUT = 5V, FCCM, fSW = 500kHz, TA = 25°C, unless otherwise noted. EN Pin Disabled IOUT = 0A EN Pin Disabled IOUT = 1A CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. Start-Up through VIN IOUT = 0A Start-Up through VIN IOUT = 1A CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. Shutdown through VIN IOUT = 0A Shutdown through VIN IOUT = 1A CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 12 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board. VIN = 12V, VOUT = 5V, FCCM, fSW = 500kHz, TA = 25°C, unless otherwise noted. Steady State fSW = 500kHz, 0A Steady State fSW = 500kHz, 1A CH1: VOUT/AC 10mV/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT/AC 10mV/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. Steady State fSW = 750kHz, 0A Steady State fSW = 750kHz, 1A CH1: VOUT/AC 10mV/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT/AC 10mV/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. I2C VID VOUT = 5V to 12V, IOUT = 0A I2C VID VOUT = 12V to 5V, IOUT = 0A CH1: VOUT 10V/div. CH2: SW1 10V/div. CH3: SW2 10V/div. CH4: IOUT 1A/div. CH1: VOUT 10V/div. CH2: SW1 10V/div. CH3: SW2 10V/div. CH4: IOUT 1A/div.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 13 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board. VIN = 12V, VOUT = 5V, FCCM, fSW = 500kHz, TA = 25°C, unless otherwise noted. I2C VID VOUT = 5V to 12V, IOUT = 1A I2C VID VOUT =12V to 5V, IOUT = 1A CH1: VOUT 10V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 10V/div. CH2: SW1 10V/div. CH3:SW2 5V/div. CH4:IOUT 1A/div. Load Transient Response VIN = 12V, VOUT = 5V, no line drop compensation, 0A to 0.5A, 150mA/μs Load Transient Response VIN = 12V, VOUT = 5V, no line drop compensation, 0.5A to 1A, 150mA/μs CH1: VOUT/AC 100mV/div. CH4:IOUT 1A/div. CH1: VOUT/AC 100mV/div. CH4:IOUT 1A/div. Short-Circuit Protection Entry with Latch-Off Mode Short-Circuit Protection Entry with Hiccup Mode CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 14 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board. VIN = 12V, VOUT = 5V, FCCM, fSW = 500kHz, TA = 25°C, unless otherwise noted. Short-Circuit Protection Recovery with Hiccup Mode VOUT OVP with Hiccup Mode CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 10A/div. CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div. VOUT OVP with Latch-Off Mode CH1: VOUT 5V/div. CH2: SW1 10V/div. CH3: SW2 5V/div. CH4: IOUT 1A/div.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 15 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM Bootstrap Regulator On Timer Buck-Boost Control Logic ALT I2C/OTP IF and Register DACSCL SDA SS EN VIN VCC BST1 SW1 GND BST2 SW2 GND OUT A B D C OUT A, B, C, D FET Sensing PG and OVP FB OV AGND IN OC COMP Bootstrap Regulator 2MΩ Current-Limit ComparatorReference VCC Regulator Error Amplifier VCC HS Driver LS Driver HS Driver LS Driver VCC VCC 0.1µF 0.1µF 4.7µH Figure 1: Functional Block Diagram

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 19 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. cycle. In latch -off mode, the MPM4730 stops switching until the IC restarts (power cycling on VIN or EN, or EN bit toggling). Over-Voltage Protection (OVP) The MPM4730 monitors a resistor-divided VFB to detect output over -voltage (O V) conditions . When the feedback voltage exceeds 160% of the target voltage, the over-voltage protection (OVP) comparator output goes high. The OUT-to- ground discharge resistor turns on. The OUT pin has an absolute OVP function. Once VOUT exceeds the absolute OVP threshold (23V), the MPM4730 stops switching and turn s on the OUT-to-ground discharge resistor. Start-Up and Shutdown If both VIN and EN exceed their respective thresholds, the chip is enabled. The reference block starts first, generating a stable reference voltage and current, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: EN going low, VIN going low, and thermal shutdown. During shutdown, the signaling path is blocked to avoid fault triggers. Then VCOMP and the internal supply rail are pulled down. The floating driver is not subject to this shutdown command. Output Discharge The MPM4730 has an output discharge function that provides a resistive discharge path for the external output capacitor. The function is active when the part is disabled (input voltage is under UVLO or enable off), the discharge path is turned off when V OUT < 50mV or wait s for the 50ms maximum timer to pass. This function can also be disabled via the I2C. Thermal Warning (TSW) and Thermal Shutdown (TSD) Thermal warning and thermal shutdown prevent the part from operating at exceedingly high temperatures. When the silicon die temperature exceeds 120°C, the MPM4730 sets the OTW bit (STATUS (09h), bit [D5]) to 1. When the temperature falls below its lower threshold (typically 100°C), the OTW bit is set to 0. When the silicon die temperature exceeds 150°C, the entire chip shuts down . When the temperature falls below its lower threshold (typically 130°C), the chip is enabled. This is a non-latch protection.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 20 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. I2C INTERFACE I2C Serial Interface Description The I2C is a two-wire, bidirectional , serial interface consisting of a data line (SDA) and a clock line (SCL). The lines are pulled to a bus voltage externally when they are idle. When connecting to the line, a master device generates the SCL signal and device address , and arranges the communication sequence. The MPM4730 interface is an I 2C slave that supports fast mode (400kHz) and high -speed mode (3.4MHz). The I2C interface adds flexibility to the power supply solution. The output voltage, transition slew rate, and other parameters can be controlled instantaneously via the I2C interface. When the master sends the address as an 8 -bit value, the 7-bit address should be followed by a 0 to indicate a write operation, or 1 to indicate a read operation. Start and Stop Commands The start and stop commands are signaled by the master device, which signifies the beginning and end of an I2C transfer. The start (S) command is defined as the SDA signal transitioning from high to low while the SCL is high. The stop (P) command is defined as the SDA signal transitioning from low to high while the SCL is high (see Figure 10). The master then generates the SCL clocks and transmits the device address and the read/write (R/W) direction bit on the SDA line. Transfer Data Data is transferred in 8-bit bytes by an SDA line. Each byte of data should be followed by an acknowledge (ACK) bit. I2C Update Sequence The MPM4730 requires a start command, a valid I2C address, a register address byte, and a data byte for a single data update. The MPM4730 acknowledges that it has received each byte by pulling the SDA line low during the high period of a single clock pulse. A valid I 2C address selects the MPM4730. The MPM4730 performs an update on the falling edge of the least significant bit (LSB) byte. Figure 11 on page 20, and Figure 12, Figure 13 on page 21 show examples of I2C write and read sequences. I2C Start-Up Timing I2C functionality is enabled once EN is active and VIN exceeds its UVLO threshold. The I2C works during OCP, OVP, and thermal shutdown. SDA SCL Start Command Stop Command S P Figure 10: Start and Stop Commands S Slave Address WR A Register Address K Write DataA A P

8 Bits 8 Bits 8 Bits

A = Acknowledge (SDA = Low) S = Start Command P = Stop CommandNA = Not Acknowledge (SDA = High) WR Write = 0 RD Read = 1 Figure 11: I2C Write Example (Write Single Register)

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 21 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. S Slave Address WR A Register Address K Write Data KA PA Write Data K + 1 A Write Data K + N Multi-byte write executed from current register location (the read-only register is skipped) A Master to Slave Slave to Master A = Acknowledge (SDA = Low) S = Start Command P = Stop CommandNA = Not Acknowledge (SDA = High) WR Write = 0 RD Read = 1 Figure 12: I2C Write Example (Write Multi-Register) S Slave Address WR A Register Address K Read Data KA A P Master to Slave Slave to Master A = Acknowledge (SDA = Low) S = Start Command P = Stop CommandNA = Not Acknowledge (SDA = High)

8 Bits

WR Write = 0 RD Read = 1 Register address to read specified Read register data from current register location Sr = Repeat Start Command Figure 13: I2C Read Example (Read Single Register)

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 22 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. I2C REGISTER MAP Add (Hex) Name R/W D7 D6 D5 D4 D3 D2 D1 D0

00 VREF_L R/W RESERVED VREF DATA BIT LOW [2:0] (9)

01 VREF_H R/W VREF DATA BIT HIGH [10:3] (9)

02 VREF_GO R/W RESERVED

PG_ DELAY_ EN (9) GO_ BIT

03 IOUT_LIM R/W RESERVED RESERVED

04 CTL1 R/W EN (9) HICCUP

OCP_OVP (9) DISCHG _EN (9) MODE (9) FREQ (9) RESERVED

05 CTL2 R/W RESERVED SS (9) RESERVED

06 RESERVED R RESERVED, all “0” RESERVED

07 RESERVED R RESERVED

08 RESERVED R RESERVED

09 STATUS R PG OTP OTW CC_CV RESERVED

0A INTERRUPT W1C OTEMPP_ ENTER OT WARNING_ ENTER OC_ ENTER OC_ RECOVER UVP_ FALLING OTEMPP _EXIT OT WARNING _EXIT PG_ RISING 0B MASK R/W RESERVED OTPMSK (9) OTWMSK (9) OC_ MSK (9) UVP_ MSK (9) PG_ MSK (9) 0C ID1 R OTP configuration code. “0x00” means the default MPM4730.

27 MFR_ID R Manufacturer ID: b ‘0000 1001’

28 DEV_ID R Device ID: b ‘0101 1000’

29 IC_REV R IC revision: b ‘0000 0001’

Note: 9) These items have one-time programmable (OTP) non-volatile memory (NVM). The OTP is reloaded to the I 2C register when VIN exceeds the under-voltage lockout (UVLO) threshold, or during EN shutdown.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 23 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. REGISTER DESCRIPTION I2C Bus Slave Address The MPM4730 I2C slave address is fixed to 60h. VREF_H (00h) and VRE_L (01h) (Output Reference Voltage Setting) The VREF_L and VREF_H registers set the reference voltage (VREF) and follow the 11-bit direct format. Name VREF Format Direct, unsigned binary integer Register Name N/A VREF_H D[7:0] VREF_L D[2:0] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function N/A Data Bit High Data Bit Low Default Value (1000mV) N/A 1250 Integer VREF can be calculated with Equation (1): REFV (mV) V 0.8= (1) Where V is an 11-bit unsigned binary integer from VREF[10:0] that ranges between 0 and 2047. The VREF resolution is 0.8mV/LSB. The VREF changing slew rate is fixed at 1mV/µs. See the GO_BIT section below to change the reference voltage. VREF_GO (02h) Format: Unsigned binary The VREF_GO command sets the control instruction of VREF beings to change and PG_DELAY_EN Bits Access Bit Name Default Description D [7:2] N/A RESERVED N/A Reserved. D [1] R/W PG_DELAY_EN 1b’0 Enables PG delay. 1: Enables. PG experiences a 100µs rising delay 0: Disabled. There is no PG delay D [0] R/W GO_BIT 1b’0 Controls whether the output reference changes. The MPM4730 can be controlled when V REF begins to change. Set GO_BIT to 1 to start the output reference change based on the VREF register. When the V REF change is complete (internal V REF reaches its target value), GO_BIT auto-resets to 0. This prevents a false operation of VREF scaling. Write to the reference voltage (0x00 and 0x01 registers) first, and then set GO_BIT = 1. V REF changes based on the new register setting. GO_BIT resets to 0 when V REF reaches a new value. The host can read GO_BIT to determine whether V REF scaling has completed. The VOUT-to-ground discharge function is enabled when GO_BIT = 1. This can ramp VOUT from high to low under light-load conditions. 1: Enabled. VREF begins to change based on the VREF register setting. After VREF scaling finishes, GO_BIT is automatically reset to 0: Disabled. VREF does not change

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 24 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. CTL1 (04h) Format: Unsigned binary The CTL1 command sets the EN function, the over-current protection (OCP) and over-voltage protection (OVP) mode s, the output discharge function, the pulse-frequency modulation ( PFM)/pulse-width modulation (PWM) mode, and the switching frequency. Bits Access Bit Name Default Description D [7] R/W EN 1b’1 Turns the part on and off. When the external EN pin is low, the converter is off, and the I2C shuts down. When EN is high, the EN bit takes over. 1: Enable the part 0: Disable the part D [6] R/W HICCUP_OCP_OVP 1b’1 Selects the mode for OCP and OV). 1: Hiccup mode 0: Latch-off mode D [5] R/W DISCHG_EN 1b’1 Enables the output discharge function. 1: Output discharge occurs during EN or VIN shutdown 0: No output discharge occurs during shutdown D [4] R/W MODE 1b’1 Enables PFM/PWM mode. The default is PWM mode under light- load conditions. 0: Enables auto-PFM/PWM mode 1: Sets forced PWM mode D [3:2] R/W FREQ 2b’00 Sets the switching frequency. 00: 500kHz 01: 750kHz 10: Reserved 11: Reserved D [1:0] N/A RESERVED N/A Reserved. CTL2 (05h) Format: Unsigned binary The CTL2 command sets the soft-start time. Bits Access Bit Name Default Description D [7:6] N/A RESERVED N/A Reserved. D [5:4] R/W SS 2b’10 Sets the output start-up soft-start timer (from 0% to 100% of VREF) if the reference voltage is 1V. 00: 1.1ms 01: 2.2ms 10: 3.5ms 11: 4.4ms The SS slew rate is constant, but SS time changes with different VREF values. For example, the SS time = 3.5ms for a 1V VREF, and the SS time = 5.25ms for a 1.5V VREF. D [3:0] N/A RESERVED N/A Reserved.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 25 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. STATUS (09h) Format: Direct The STATUS command monitors the power good (PG), over -temperature protection (OTP), and over- temperature warning (OTW) statuses . It also enables constant-current (CC) or constant -voltage (CV) mode. These status bits indicate instantaneous values. Bits Access Bit Name Default Description D [7] R PG N/A Indicates the output PG status. 0: Output power is not good 1: Output power is good D [6] R OTP N/A Indicates whether OTP has occurred. 0: OTP has not occurred 1: OTP has occurred D [5] R OTW N/A Indicates whether OTW has occurred. 0: OTW has not occurred 1: OTW has occurred D [4] R CC_CV N/A Enables CC output mode or CV output mode. 0: CV mode 1: CC mode D [3:0] N/A RESERVED N/A Reserved. INTERRUPT (0Ah) Format: Direct The INTERRUPT command monitors the status es of OTEMPP_ENTER, OTWARNING_ENTER, OC_ENTER, OC_RECOVER, UVP_FALLING, OTEMPP_EXIT, OTWARNING_EXIT, and PG_RISING. Each bit in this command is latched once triggered. Write 0xFF to this register to reset the interrupt and the ALT pin’s state. Bits Access Bit Name Description D [7] W1C OTEMPP_ ENTER Indicates when the device enter s over-temperature protection (OTP). When this bit is high, the IC enters thermal shutdown. This bit is not masked, even if OTPMSK = 1. Setting OTPMSK to 1 only masks the interrupt pin’s output (ALT). D [6] W1C OTWARNING_ ENTER Indicates when the device enters the d ie temperature early warning condition. When this bit is high, the die temperature exceeds 120°C. This bit is not masked, even if OTWMSK = 1. Setting OTWMSK to 1 only masks the interrupt pin’s output (ALT). D [5] W1C OC_ENTER Indicates when the device enters over-current (OC) or constant-current (CC) current-limit mode. THE OC_MSK bit can enable or disable the OC_ENTER and OC_RECOVER ALERT outputs. D [4] W1C OC_RECOVER Indicates when the device recovers from constant-current (CC) current- limit mode. If the device recovers from a hiccup, it does not trigger this interrupt signal. D [3] W1C UVP_FALLING Indicates when the reference voltage is within its under-voltage protection (UVP) threshold. D [2] W1C OTEMPP_EXIT Indicates when OTP ends. OTPMSK can mask off the ALT signals of this bit.

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 29 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUIT MPM4730 GND EN VIN AGND SW1VIN = 2.8V to 22V VCC 1µF SDA C2B 22µF 100µF C1B 22µF SW2BST2 SCL I2C Slave OUT OC FB BST1 ALT VCC 21.5kΩ 22nF 42.2kΩ 3kΩ 499kΩ 2, 111 9 7, 8 4 5, 6 C2C 22µF VOUT = 15V C2A 0.1µF C1A 0.1µF 22nF 10kΩ C2D 22µF C2E 22µF C2F 22µF RT 49.9kΩ Figure 18: Typical Application Circuit (VOUT = 15V)

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 30 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. DEFAULT OTP CONFIGURATION Table 2: 0000 Suffix Code Configuration OTP Items Default Output Voltage 15V Reference Voltage 1V Initial On/Off On Mode FCCM Soft-Start Time 3.5ms Output Discharge EN Enabled OCP/OVP Mode Hiccup mode Switching Frequency 500kHz PG Delay EN Disabled OTP Mask Off OTW Mask Off OC Mask Off UVP Mask Off PG Mask Off Software Initial I2C Slave Address 0x60 Table 3: 0000 Suffix Register Value Register Hex Value 0x00 02h 0x01 9Ch 0x02 00h 0x04 F0h 0x05 20h 0x09 80h 0x0A 01h 0x0B 00h 0x0C 00h 0x27 09h 0x28 58h 0x29 01h

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 31 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

PACKAGE INFORMATION

ECLGA-18 (3mmx3mm) BOTTOM VIEWTOP VIEW SIDE VIEW PIN 1 ID MARKING PIN 1 ID INDEX AREA NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS . 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX . 3) JEDEC REFERENCE IS MO -303. 4) DRAWING IS NOT TO SCALE . PIN 1 ID 0.125X45° TYP

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE MPM4730 Rev. 1.0 MonolithicPower.com 32 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package (3mmx3mmx 1.86mm)

2500 N/A N/A 13in 12mm 8mm

(3mmx3mmx 1.86mm)

MPM4730 – 2.8V TO 22V VIN, MAX 1A, BUCK-BOOST MODULE Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPM4730 Rev. 1.0 MonolithicPower.com 33 3/11/2024 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2024 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 3/11/2024 Initial Release -

Summary

2.8V to 22V VIN, Max 1A, 4-Switch Integrated Buck-Boost Module 3/11/2024 Rev. 1.0

Description