Power Management

MPF0900AVNA5ES

NXP Semiconductors

Nine-channel power management IC with advanced system safety monitoring Rev. 1.3 - 16 December 2025

Manufacturer: NXP Semiconductors

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PDF pages: 205

Technical content

Datasheet sections

1 Overview
2 Features and benefits
3 Applications
4 Simplified application diagram
5 Ordering information
6 Device versioning
7 Functional block diagram
8 Internal block diagram
9 Pinning information
9.1 Pinning
9.2 Pin description
10 General product description
10.1 Features
10.2 Power tree summary
10.3 Device identification
11 Functional state machine description
11.1 Functional state machine
11.2 State descriptions
11.2.1 VIN cold boot initialization
11.2.2 ULPOFF state
11.2.3 LPOFF state
11.2.4 DBGOFF state
11.2.5 Self-test routine
11.2.6 Power-up sequence
11.2.7 RUN State
11.2.8 STANDBY state
11.2.9 Power-down sequence
11.2.9.1 TURNOFF state
11.2.9.2 FAULT state
11.2.9.3 RESET state
11.2.10 Fail-safe transition
11.2.11 Deep Fail-safe (DFS) state
11.2.12 VDDOTP modes
11.2.12.1 Debug operation
12 General device operation
12.1 UVDET
12.2 VIN OV monitoring
12.3 Device power-up
12.3.1 IC startup
12.3.2 Power-up events
12.3.3 Regulator Power-up sequence
12.3.3.1 Time-based power-up
12.3.3.2 Dynamic power-up
12.4 Power down
12.4.1 Turn-off events
12.4.1.1 Non-PMIC failure turn-off events
12.4.1.2 Turn-off event due to a hard fault condition
12.4.2 Reset conditions
12.4.2.1 Hard reset
12.4.2.2 Soft reset
12.4.2.3 Reset counter
12.4.3 Early warning
12.4.4 Power-down sequencing
12.4.4.1 VAON power-down control
12.4.4.2 Power-down delay
12.5 RUN/STANDBY transitions
12.5.1 RUN to STANDBY transition
12.5.2 STANDBY to RUN transition
12.6 Fault management
12.6.1 Fault counter
12.6.2 System regulators and external VMON fault
12.6.2.1 Output state control
12.6.2.2 Fault bypass control
12.6.2.3 Fault timer
12.6.3 VAON fault management
12.6.3.1 VAON always-on mode
12.6.3.2 VAON as system regulator
12.6.4 Fault monitoring during time-based power
12.6.5 Fault monitoring during dynamic power up
12.7 System diagnostics
12.7.1 System fault flags
12.7.2 Interrupt management
12.7.3 System test commands
12.8 I/O interface pins
12.8.1 Interfacing I/O electrical characteristics
12.8.2 PWRON
12.8.2.1 Level-sensitive mode
12.8.2.2 Edge-sensitive mode
12.8.3 STBY
12.8.4 INTB
12.8.5 RSTB
12.8.5.1 RSTB pin diagnostic
12.8.6 PGOOD
12.8.6.1 PGOOD pin diagnostic
12.8.7 FS0B
12.8.7.1 Fault status mode
12.8.8 FCCU1 (XRESET mode)
12.8.9 GPIO1
12.8.9.1 GPO mode
12.8.9.2 VSELECT mode
12.8.10 GPIO2
12.8.10.1 GPO mode
12.8.10.2 LDO1EN mode
12.8.11 GPIO3
12.8.11.1 GPO mode
12.8.12 GPIO4
12.8.12.1 GPO mode
12.8.13 XFAILB
12.8.13.1 Power-up synchronization
12.8.13.2 Power-down synchronization
12.8.14 I2C Interface
12.8.14.1 I2C CRC verification
12.8.14.2 I2C secure write
13 Functional blocks
13.1 Analog core and internal references
13.1.1 VANA
13.1.2 VDIG
13.1.3 Internal bandgap references
13.2 System voltage generation
13.2.1 VAON

Nine-channel power management IC with advanced system safety monitoring Rev. 1.3 — 16 December 2025 Product data sheet

1 Overview

The PF09 is a power management integrated circuit (PMIC) optimized for high performance i.MX9x based applications. It Integrates multiple high-efficiency switch mode and linear voltage regulators to support base system power from a pre-regulated system rail (3.3 V to 5.0 V). It provides low quiescent current in STANDBY (STBY) and low-power Off modes. Built-in multiple time programmable configuration stores key startup configurations, drastically reducing the number of external components typically used to set the output voltage and sequence of external regulators. Regulator parameters are adjustable through high-speed I2C communication after startup, offering flexibility for different system states. The PF09 is developed in compliance with the ISO 26262 standard, including safety features, with Fail-safe outputs and integrated self-test mechanisms, becoming part of a safety-oriented system partitioning targeting high-integrity safety levels up to ASIL D, and complying with the IEC61508 industrial safety specification targeting high safety integrity levels up to SIL 2.

Nine-channel power management IC with advanced system safety monitoring

2 Features and benefits

Up to five buck regulators with internal power stage and programable current limits
Three low-dropout linear regulators with load switch operation
Ultra-low power always-on LDO supply
Two external voltage monitoring inputs
Programmable I/O interfacing pins
Advanced frequency management with frequency spread spectrum
Multi-channel analog multiplexer for system voltage monitoring
High speed I2C interface with up to 3.4 MHz operation
Advanced thermal monitoring and thermal shutdown protection
Functional safety architecture to target up to ASIL D automotive applications
Functional safety architecture to target up to SIL 2 industrial applications
Multiple-time programmable configuration (MTP)
56-pin QFN Package with exposed pad
Automotive qualified by AEC-Q100 rev J up to Grade 1 PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring

3 Applications

Automotive infotainment
High-end consumer and industrial
Connectivity domain controller
Telematics PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

4 Simplified application diagram

5 Ordering information

Table 1. Ordering information [1] To order parts in tape and reel, add the R2 suffix to the part number. Table 2. Ordering options PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

6 Device versioning

last two digits of the device core number, for example, PF09XX. Table 3 below provides the functional safety feature partitioning for all standard safety grades. Table 3. Device versioning strategy [1] Available features can be enabled or disabled in OTP. Please refer to the specific OTP configuration report for specific information. [2] Enabled features are enabled all the time to provide real-time protection. [3] May not be available in some part numbers with a reduced feature set. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Nine-channel power management IC with advanced system safety monitoring be required to move up to a different tier or generate a custom request to create a new device customization if possible. Finally, at the third level, all members of the PF09 family are provided with one-time programmable (OTP) registers to set the default hardware configuration and behaviors of the device at power-up. OTP configuration bits are discussed throughout this document in order to provide visibility of the possible configuration that can be achieve within the context of the functional behaviors of each configuration. However, OTP configuration is only possible during the part number customization stage (OTP ID generation) and cannot be modified during system operation. OTP emulation and programming performed by the customer is allowed during engineering development using NXP’s latest graphical user interface and socketed evaluation board. The customer is not allowed to perform OTP programming for production purposes. Only NXP or a recommended third party are allowed to program the device for production purposes. Contact your NXP representative for more detailed information on how to request a custom configuration or in- house programming procedure to generate custom parts suitable to your specific system needs. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

7 Functional block diagram

8 Internal block diagram

9 Pinning information

9.1 Pinning

The PF09 is offered in a 56-pin, 8 x 8 mm2 body size QFN with exposed pad and wettable flanks. Figure 5. PF09 package pinout (top view)

9.2 Pin description

10 General product description

10.1 Features

Up To five buck regulators with internal power stage – SW1 single-phase operation, 0.5 V to 3.3 V @ 3.5 A with up to 1.5 % DC accuracy – SW2 multi-phase operation, 0.3 V to 3.3 V @ 2.5 A with up to 1.5 % DC accuracy – SW3 multi-phase operation, 0.3 V to 3.3 V @ 2.5 A with up to 1.5 % DC accuracy – SW4 multi-phase operation, 0.3 V to 3.3 V @ 2.5 A with up to 1.5 % DC accuracy – SW5 multi-phase operation, 0.3 V to 3.3 V @ 2.5 A with up to 1.5 % DC accuracy – Programmable current limit
Three low-dropout linear regulators. – LDO1: LDO/load switch with output voltage from 0.75 V to 3.3 V @ 500 mA. – LDO2 and LDO3: low-power LDO/load switch with output voltage from 0.65 V to 3.3 V @ 200 mA
Ultra-low power always-on LDO supply – Configurable output voltage: 1.8 V, 3.0 V or 3.3 V with up to 2 % DC accuracy
Two external voltage monitoring inputs – Dynamic monitoring voltage selection – Selectable monitoring threshold with up to 1% monitoring accuracy
Programmable I/O interface
Advanced frequency management with frequency spread spectrum
Multi-channel analog multiplexer for system voltage monitoring
High-speed I2C interface with up to 3.4 MHz operation
Advanced thermal monitoring and thermal shutdown protection
Functional safety architecture to target up to ASIL D automotive applications
Functional safety architecture to target up to SIL 2 industrial applications
Multiple-time programmable (MTP) configuration
56-pin QFN package with exposed pad
Automotive qualified by AEC-Q100 rev J up to Grade 1

10.2 Power tree summary

Table 5. PF09 voltage regulator summary. [1] Input supply for switching regulators must be capable to sink current to avoid overvoltage condition during the power-down sequence of the device. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

10.3 Device identification

The DEV_ID[4:0] bits are provided to identify the core ID for each member of the PF09 family.

00000 PF0900

00001 PF0901

00010 PF0902

11111 PF0931

Table 6. DEVICE_ID bit field

001 ASIL B

010 ASIL D

011 SIL 2

100 Reserved

101 Reserved

110 Reserved

111 Reserved

Table 7. FS_ID bit field safety mechanism provided on the corresponding device. The DEVICE_FAM[7:0] bits is provided to identify the family code for the PF09. Table 8. DEVICE_FAM bit field programmed devices provide by NXP. The PROG_IDH[4:0] bits provide the hexadecimal coding of the first OTP ID character (A - Z). Table 9. PROG_IDH bit field PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 9. PROG_IDH bit field...continued The PROG_IDL[5:0] bits provide the hexadecimal coding of the second OTP ID character (1 - 9 and A – Z). Table 10. PROG_IDL bit field PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

100010 NOT ASSIGNED

100011 NOT ASSIGNED

111111 NOT ASSIGNED

Table 10. PROG_IDL bit field...continued The OTP_VIN_SEL bit is provided to select the intended input voltage in the system. Table 11. OTP_VIN_SEL bit 5.0 V to improve system robustness. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

11 Functional state machine description

11.1 Functional state machine

11.2 State descriptions

11.2.1 VIN cold boot initialization

operation of the PWRON pin set in the OTP registers. sequence to ensure the supply is up in regulation by the time the system is ready to request a power-up event. safety mechanism are healthy at power up. proceed with the power-up sequence. Table 12. VIN_POR thresholds

11.2.2 ULPOFF state

ULPOFF state as long as the VIN does not fall below the VIN_POR_FALL threshold. notification flags will be lost and reset to the default state once a wake-up event is present.

11.2.3 LPOFF state

configuration selected by the OTP_PWRON_MODE bit. current in the ULPOFF state when the device is intended to remain in the OFF condition. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Nine-channel power management IC with advanced system safety monitoring In systems requiring to operate the PWRON pin in edge sensitive mode, the LPOFF state becomes the static low-power state for the system, since the PWRON pin is expected to be pulled up to VIN externally. In this scenario, the device will automatically detect a wake-up event upon entering the ULPOFF state, and proceed to perform the fuse load routine and move into the LPOFF state to wait for a Falling edge on the PWRON pin to generate a valid power-on event.

11.2.4 DBGOFF state

During normal system operation, the DBGOFF (debug off) state will be a transitory state between a power-on event and the power-up sequence. It serves as the gating state to ensure the PMIC is ready to start a power- up sequence, and allow synchronization of two or more PMICs providing full power architecture to a complex system. If the VDDIO supply is provided externally, the device is able to communicate through the I2C bus during the DBGOFF state, allowing the PMIC to operate in development/debugging modes. In such scenarios, the DBGOFF state becomes a full-biased OFF state, to allow full access to the functional and OTP registers to enable OTP emulation and/or OTP fuse programming. Contact your NXP representative for detailed instructions on OTP emulation and fuse programming. If the VAON is set as an always-on Regulator, the VAON supply is monitored for OV/UV conditions to ensure the supply is in regulation before allowing the power-up sequence to start. If the XFAILB synchronization function is available, the device will use the DBGOFF state as the synchronization point to start the power-up sequence. The PF09 will release the XFAILB pin internally when it is ready to start the Power-up sequence, based on the following conditions:

Self-test has finished (if self-test is available in the device)
&& The LBIST_STATUS[1:0] is different from 0b10 (if LBIST is available in the device)
&& the fuse loading (_NOK - Register Address Flags: 0x2D) flags are not asserted
&& VAON has reached regulation (if VAON set as always-on regulator)
&& VIN < VIN_OV (if the VIN_OV monitor is enabled)
&& TJ is at least 10 °C below the TSD threshold
&& VDDOTP < 3.0 V If any of the conditions mentioned above are not met, the XFAILB will remain asserted and the device will remain in the DBGOFF state until all conditions are met. Once the XFAILB pin has been internally released, the device will monitor the XFAILB pin to pause the power-up sequence until the pin has been released HIGH by all devices connected to it. If the XFAILB synchronization function is not available, the XFAILB status is no longer a condition to proceed with the power-up sequence and the following conditions must be met to allow the power-up sequence to be started:
Self-test has finished (if self-test is available in the device)
&& The LBIST_STATUS[1:0] is different from 0b10 (if LBIST is available in the device)
&& the fuse loading (_NOK - Register Address Flags: 0x2D) flags are not asserted
&& VAON has reached regulation (if VAON set as an always-on regulator)
&& VIN < VIN_OV (if VIN_OV monitor is enabled)
&& TJ is at least 10 °C below the TSD threshold
&& VDDOTP < 3.0 V In the event the device is stuck in the DBGOFF state, a power-off event in the PWRON pin will send the device to the corresponding OFF state and wait for a new power-up event to attempt the power-up sequence again. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring

11.2.5 Self-test routine

In devices with a high safety integrity level (ASIL/SIL) the self-test routine is performed when the state machine transitions out of the LPOFF state. During the self-test, the PF09 performs a startup self-check routine to verify the integrity of the system: The high speed oscillator circuit is operating within a maximum of 6 % tolerance. The outputs of both the voltage generation bandgap and the monitoring bandgap are not drifting apart from each other. A CRC is performed on the mirror registers during the self-test routine, to ensure the integrity of the OTP registers before powering up. Analog built-in test on all voltage monitors and Safety I/Os is performed. (Refer to section Section 14.8 for details on ABIST implementation.) To allow for varying settling times for the internal bandgap and oscillators, the self-test routine is executed up to three times (with 2 ms between each test) if a failure is encountered. If all three checks result in a failure, the state machine will proceed to the Fail-safe transition to prevent operation with a potential latent fault present. A failure in the ABIST test is not interpreted as a self-test failure, and it will only set the corresponding ABIST flag in order to prevent the system from exiting a safe state after power-up.

11.2.6 Power-up sequence

The PF09 provides a highly configurable power-up sequence to enable the system regulators and general purpose IO pins in a specific order and timing during the power-up state. The default configuration for the power-up sequence is loaded from the OTP registers to ensure the system always turns on with the correct configuration every power-up cycle as defined on each specific part number. The RSTB pin is also programmable as part of the power-up sequence, and it is used as the condition to enter the SYSTEM ON states. Voltage monitoring functions are provided during the power-up sequence to ensure the system is brought out of reset only if all voltage regulators enabled before the RSTB pin have reached regulation and are operating properly. The RSTB may be released in the middle of the Power-up sequence. In this case, the remaining supplies in the power-up still continue to ramp up while the state machine enters the system-on states to process fault conditions actively. Refer to section Section 12.3.3 for details.

11.2.7 RUN State

If the power-up sequence is completed successfully, the state machine transitions directly into the RUN state. The RUN State is a full-featured state providing full functionality and monitoring as described in this document. All safety-related monitoring is fully operational during the RUN State if the corresponding feature is enabled via OTP or functional registers. Upon entering the RUN State, the I2C functional registers are loaded with the default values set by the OTP registers, or with the default configuration. The MCU is expected to perform a booting sequence to modify the PMIC functional configuration as required by the application. All registers to control the regulators' output voltage, operating modes, interrupt masks and other miscellaneous functions can be written to or read from the functional I2C register map during the SYSTEM ON states once the power-up sequence is finalized. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

11.2.8 STANDBY state

monitoring or low-power operation. detailed description of the STBY pin operation. the proper VDDIO is supplied.

0 Monitored STANDBY

1 Low-power STANDBY

Table 13. OTP_LP_STBY bit the STANDBY registers, with most monitoring functions available. Table 14. STANDBY operation summary [1] If block is available in the device and/or OTP configuration. [2] FCCU monitoring allowed with limited functionality in the safe state. in the customized part number. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Nine-channel power management IC with advanced system safety monitoring When the device transitions from the RUN to the STANDBY state, the system will trigger a PWRDN_I interrupt. The PWRDN_I event will assert the INTB pin only if the PWRDN_M = 0 (interrupt un-masked). By default, the PWRDN_M bit is masked upon power up.

11.2.9 Power-down sequence

Three types of events may lead to the power-down sequence.

Non-faulty or requested turn-off event
Turn-off events due to a PMIC fault
Reset event During the power-down sequence, the system regulators are disabled as described in the power-down sequencing section.

11.2.9.1 TURNOFF state

Non-faulty turn-off events move directly into the corresponding low-power state as soon as the power-down sequence is finalized. If the VAON is set to operate as an always-on regulator, the VAON output will remain enabled during the turn- off event and into the low-power modes. If the VAON is set as a system regulator, the VAON regulator will be disabled as defined in the power-down sequence. All other system regulators will be disabled as defined in the power-down sequence.

11.2.9.2 FAULT state

Turn-off events due to a PMIC fault will move into the Fail-safe transition as soon as the power down sequence is finalized. If the VAON is set as an always-on regulator, the VAON output will remain enabled during a fault event transitioning through the Fail-safe transition. If the VAON is set as a system regulator, the VAON output will be disabled as defined in the power-down sequence. All other system regulators are disabled as defined in the power-down sequence.

11.2.9.3 RESET state

A RESET state is provided to allow the system to refresh the configuration without looping through a full power cycle. During a reset event, the system can decide whether the VAON supply remains enabled, to maintain the always-on domain or turn off to generate a full system reset condition. When a reset event has occurred, the device turns off the system regulators as defined by the power-down sequence, and it will power back up without the need of a new power-on event.

11.2.10 Fail-safe transition

During the Fail-safe transition, the VAON remains enabled if it is configured as an always-on regulator. All system regulators will remain disabled until the next power-up sequence. The state machine provides a Fail-safe counter (FS_CNT[3:0]) to prevent a non-recoverable cyclic failure from happening. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

a valid condition to exit the state.

11.2.11 Deep Fail-safe (DFS) state

The DFS state is intended to work as a temporary lockdown state upon a cyclic critical failure condition. into the DFS state is programmed using the OTP_MAX_FS_CNT[3:0] bits. system operates only under controlled safe conditions. refreshes when WD_OK_FDC[2:0] != 0x00. In this state, the PGOOD and RSTB pins remain asserted low all the time. FS0B pin will remain asserted low during the DFS state. FS0B will be asserted if the FS0B_DFS = 1, or another fault caused it to assert previously. system regulators to prevent further damage to the system. selectable via the OTP registers during the device customization stage. The OTP_PWRON_DFS bit is provided to allow the device to wake up from the DFS state via the PWRON pin.

0 PWRON is not able to exit DFS

1 PWRON able to exit DFS

Table 15. OTP_PWRON_DFS bit

0 Auto retry Disabled

1 Auto retry Enabled

first and be toggled HIGH again in order to recognize a valid exit from DFS. increase the eight-bit RETRY_CNT[7:0] by one and proceed to attempt a power-up event. Table 17. Auto-retry timer summary bits (4-MSB) of the RETRY_CNT[7:0]. following power-up retry attempt. limited number of times, or every time it enters the DFS state. Table 18. Autoretry dynamic characteristics PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

DFS state via the auto-retry timer. to exit the DFS state on every fault cycle. The retry timer can be rescaled down by writing 0x00 to RETRY_CNT[7:0], which resets it. DFS state until VIN > UVDET. and TA = 25 °C, unless otherwise noted. Table 19. Auto-retry time base

11.2.12 VDDOTP modes

The PF09 supports OTP fuse bank configuration and Debug mode through the VDDOTP pin.

If VDDOTP = GND, the device loads the configuration from the OTP fuses and operates in Normal mode.
If VDDOTP ≥ 1.3 V, the device enters Debug mode. The OTP configuration is accessible through mirror registers, and the device operates in a limited functionality mode.
If VDDOTP ≥ 7.5 V, the device enters Programming mode and the OTP configuration is defined in the OTP registers, allowing the device to fuse the OTP registers. This configuration will be loaded in normal operation. Configuration emulation and programming (OTP) can be performed by the customer during engineering development using NXP's latest graphical user interface and an evaluation board. Customer is not allowed to perform OTP programming for production purposes. Only NXP or a recommended third party are allowed to program the device for production purposes. Function name Description Symbol Min Typ Max Unit VDDOTP_OTP VDDOTP 1.5 V threshold VDDOTP1P4TH 1.3 1.4 1.5 V VDDOTP_DBG VDDOTP 3.0 V threshold VDDOTP3P0TH 2.9 3.0 3.1 V VDDOTP_PGR VDDOTP programming voltage range VDDOTP_PRG 7.5 – 8.5 V

Table 20. VDDOTP pin electrical characteristics

11.2.12.1 Debug operation

The PF09 allows temporary configuration to debug or test a customized power-up configuration in the system. To access Debug mode, the VDDOTP pin should be pulled up to high above VDDOTP3P0TH. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

I2C communication uses standard communication, with no CRC and secure write disabled
The default I2C address is 0x08, regardless of the address configured by OTP
Watchdog operation/monitoring is disabled
Secure write is disabled
XRESET pin is disabled
FCCU is disabled
DVSMIN and DVSMAX limits are disabled The PF09 can operate normally using the Debug mode configuration, as long as VIN does not go below the UVDET threshold. If VIN is lost (VIN < UVDET) the mirror registers will be reset, and Debug mode configuration must be performed again. The DBG_MODE flag is provided to indicate the device is in Debug mode. DBG_MODE Debug mode

0 Disabled

1 Enabled

Table 21. Sys_Diag (register 0x82 )

11.2.12.1.1 Test mode

registers as well as all registers needed for OTP programming.

I2C communication uses standard communication, with no CRC and secure write disabled
The default I2C address is 0x08, regardless of the address configured by OTP
Watchdog operation/monitoring is disabled
Secure write is disabled
XRESET pin is disabled
FCCU is disabled
DVSMIN and DVSMAX limits are disabled OTP Emulation mode allows the user to modify OTP mirror registers before powering up. This facilitates exercising different features of the PF09 while deciding on the best configuration for a given application. This is especially useful when optimizing the SWx compensation for the desired transient response. In emulation mode, only a VIN < UVDET or a critical DMS fault condition sends the device into the DFS state and causes a fuse reload upon exiting the DFS state. OTP fuse burning is performed in the DBGOFF state. To burn the OTP fuses, devices must enter Test mode and write the desired values in the mirror registers. Once the proper configuration is set on the mirror registers, the device is configured. The programming command is executed while VDDOTP has a programming voltage between 7.5 V < VDDOTP < 8.5 V. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

12 General device operation

12.1 UVDET

started, the device allows full operation as long as VIN does not fall below the falling UVDET threshold. Fail-safe state and waits for proper conditions to exit the DFS state. to provide debugging information to the system. The UVDET_FAIL bit can be cleared by writing a 1 to it. Table 22. UVDET electrical characteristics

12.2 VIN OV monitoring

purpose is to prevent PMIC operation with a VIN condition out of the maximum operating range of the PF09. Table 23. VIN_OV_EN bit the OTP registers via the OTP_VIN_OV_SDWN bit.

0 Interrupt Only

1 PMIC Shutdown

Table 24. VIN_OV_SDWN bit up event to ensure the system is not started with a VIN fault condition present. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

11 Reserved

Table 25. VIN_OV_DBNC bit field Table 26. VIN_OV electrical characteristics

12.3 Device power-up

12.3.1 IC startup

reducing the overall turn-on time. power-up sequence, and it will not be considered as a gating factor to reach PWRUP_READY condition. evaluated after the fuse-loading routine is finished (entering the LPOFF state). PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 8. PMIC Startup from Cold boot (VAON Always-on) ULPOFF state until a valid wake-up event is present on the PWRON pin. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 9. PMIC Startup from Cold boot (No default PWRON event) regulation in order to reach the PWRUP_READY condition. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 10. PMIC wake-up from DFS The default timing for the external regulators to start up is set via the OTP bits as described in Section 12.3.3. and TA = 25 °C unless otherwise noted.

From wake-up event (PWRON or cold boot)
Analog core biasing until digital supply is in regulation. – 370 625 µs tFLoad Fuse load time
VDIG in regulation to FUSE_LOAD_DONE – 190 200 µs tSTEST Self-test time
From PWRON event detected until STEST_DONE
PWRUP_READY = STEST_DONE, assuming no event is gating the power-up sequence. 770 800 µs tLBIST LBIST test time
LBIST enabled
Includes initial fuse load – – 4.5 ms tFirst Time from PWRUP_READY to regulator in first slot to start rising. – – 100 µs

12.3.2 Power-up events

low transition, the device will remain in the LPOFF until a valid PWRON event is present.

12.3.3 Regulator Power-up sequence

The PF09 provides two different ways to power up. separation between each slot. hierarchical level have reached the point of regulation.

12.3.3.1 Time-based power-up

When the OTP_SEQ_MODE = 0, the device will power up in time-based mode. Table 28. Default sequencer time base sequencer timing during RUN-to-STANDBY transitions as well as during the power-down sequence. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 29. List of channels with selectable power-up sequencing

Remains OFF in the case of a regulator
Remains low in the case of a GPO
Remains disabled in the case of an external VMON Regulators, GPIOs and voltage monitors that are not enabled during the power-up sequence can be enabled during the SYSTEM ON states via the functional registers. OTP_SWx_SEQ[7:0] OTP_ LDOx_SEQ[7:0] OTP_GPOx_ SEQ[7:0] OTP_VMONx_ SEQ[7:0] OTP_RSTB_SEQ[7:0] SWx_SEQ[7:0] LDOx_ SEQ[7:0] GPOx_ SEQ[7:0] VMONx_ SEQ[7:0] RSTB_SEQ[7:0] Sequence slot Startup time [µs] 00000000 00000000 Off Off 00000001 00000001 0 SLOT0 00000010 00000010 1 SEQ_TBASE x SLOT1 00000011 00000011 2 SEQ_TBASE x SLOT2 … … … … 11111101 11111101 252 SEQ_TBASE x SLOT252 11111110 11111110 253 SEQ_TBASE x SLOT253

Table 30. Channel sequence...continued monitored supplies enabled in the sequence to be within regulation before the RSTB pin can be released. default after the last regulator/GPO/VMON has been enabled. all regulators in the power up sequence are in regulation. external VMON enabled or GPO pin releasing high. an OR condition in which the RSTB signal to the MCU is released only after all PMICs are up in the RUN state. the INTB pin is always asserted to indicate the end of the Power-up sequence to the system MCU. notification that all system supplies are up and running. system is ready to perform full operation. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 11. Power up/down Transitions

12.3.3.2 Dynamic power-up

When the OTP_SEQ_MODE = 1, the device will power up in dynamic mode. for the power-up sequence, instead, the slot number is used to create a hierarchical order during power-up. (Regulators with lower slot numbers belong to a lower hierarchical level). to power down in the reverse time-based sequence as defined in Section 12.4. Table 31. Dynamic power down sequence example powering up only after the previous regulators have reached the point of regulation. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 32. Dynamic sequence settling time voltage regulators will be monitored for OV and UV during and after their turn-on ramp. Section 12.6.5 for more details. the next hierarchical level and restart the settling timer for the following hierarchical level. time, the device will detect a power-up failure and start a power-down event right away. power-down event right away. regulator in the sequence reaches regulation. the RUN state until the last regulator has reached regulation properly. the MCU that it has finished the Power-up sequence properly. finished. At this point PGOOD can be released, if all regulators in the sequence are within regulation.

12.4 Power down

12.4.1 Turn-off events

PMIC (hard fault condition).

12.4.1.1 Non-PMIC failure turn-off events

When OTP_PWRON_MODE = 0, the device will start a power-down event when the PWRON pin is pulled low. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

0 VAON not affected

1 VAON reset

Table 33. VAON reaction on XFAILB enabled again once the power-down delay is over and the device enters the LPOFF State.

12.4.1.2 Turn-off event due to a hard fault condition

When an OV, UV or ILIM condition is present long enough for the fault timer to expire.
When FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0]
When TJ is at least 10 °C below the TSD threshold
When the reset counter reaches the maximum count (RESET_CNT = RESET_MAX)
When the RSTB pin is shorted externally for longer than the OTP_RSTB_TSHORT[1:0] timer

12.4.2 Reset conditions

A watchdog failure
A fault condition in the XRESET input (FCCU1 pin)
A fault condition in the FCCU interface (if programmed to generate the reset)
A fault condition in the ERRMON input (if programmed to generate the reset)
A reset event can be initiated by the PWRON pin in Edge-sensitive mode and OTP_PWRON_RST_EN = 1 A software reset can be requested by writing SYS_CMD[7:0] = 0x3E Reset events can be classified into two types: 1. Hard reset 2. Soft reset PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

12.4.2.1 Hard reset

down as indicated in the power down sequence.

A watchdog failure
The PWRON pin used in edge-sensitive mode with the PWRON_RST_EN = 1
A software reset via the SYS_CMD register
The FCCU1 pin operating in XRESET mode with the XRST_MODE = 0
The FCCU failure with the FCCUx_RESET = 10
The ERRMON failure when ERRMON_RESET = 1 If the VAON is set as an always-on regulator, the PF09 uses the VAON_RESET_EN bit to choose whether the VAON output is included in the RESET event or not. VAON_RESET_EN VAON always-on reset reaction

0 VAON Reset disabled

1 VAON Reset enabled

Table 34. VAON always-on reset reaction

12.4.2.2 Soft reset

The XRESET input (FCCU1 pin) with XRST_MODE = 1
An FCCU failure with the FCCUx_RESET [1:0] = 01 When the VAON is set as an always-on regulator, the soft reset does not have any impact on this regulator. If the VAON is set as a system regulator, the VAON_RESET_EN bit will set the behavior of the VAON during a soft reset event. VAON_RESET_EN Soft reset impact

0 VAON ignores the soft reset

1 VAON reloads default configuration

reset to the default OTP value during a soft reset event.

0 No reset

1 Reset to default OTP

Table 36. WD duration on soft reset

0 Output ignores the soft reset

1 Reset to default value

Table 37. Effect of soft reset on GPO

If OTP_GPIOx_SEQ = 0x00, the output is defaulted to LOW.
If OTP_GPIOx_SEQ != 0x00, the output is defaulted to HIGH. The behavior of the system regulators (SWx/LDOx) upon a soft reset is controlled by the corresponding SWx_SOFTRST_EN/LDOx_SOFTRST_EN bits. SWx_SOFTRST_EN LDOx_SOFTRST_EN Soft reset tmpact

0 Ignores the soft reset

1 Reload the default value

Table 38. Effect of soft reset on system regulators changed during the system operation, it will return to the default voltage level set by the OTP bits. states, will be disabled when the default value is reloaded. current configuration or return to the default configuration when a soft reset is present. Table 39. Effect of soft reset on external VMON input monitoring will be disabled if the block was not enabled by default during the power up sequence. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

at the default voltage level.

00 No RSTB assertion

01 Assert RSTB for 100 μs

10 Assert RSTB for 500 μs

11 Assert RSTB for 1000 μs

Table 40. RSTB pulse on soft reset The OTP_RSTB_SOFTRST[1:0] is provided to set the default value of the RSTB_SOFTRST[1:0] bits. configuration and start servicing the watchdog again. when all voltages finished transitioning to the default values.

12.4.2.3 Reset counter

Figure 12. Reset counter strategy. when the device crosses into the LPOFF state.

12.4.3 Early warning

be asserted before it starts the Power-down sequence.

Fault timer expired
FAULT_CNT = FAULT_MAX_CNT
Thermal shutdown (TJ > TSD)
A hard reset event
A VIN_OV event when VIN_OV_SDWN=1
A turn-off event due to RSTB being asserted externally The OTP_EWARN_TIME[1:0] allows the user to select a time delay from when the EWARN interrupt is generated and the power-down sequence is started. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Table 41. EWARN delay time

12.4.4 Power-down sequencing

voltage monitors will be sequenced down during a power-down event. corresponding _SEQ[7:0] bits will be disabled first, and those with the lower slot will be disabled last. Channels whose _SEQ[7:0] bits are set to 0x00 will be disabled first, before the sequenced slots are disabled. down in the next power cycle following the new values. able to power up with a valid Power-up sequence. pins will be turned off at once when the power-down sequencer is invoked.

12.4.4.1 VAON power-down control

The behavior of the VAON during a power-down sequence is dependent on the mode of operation of this LDO. the _SEQ[7:0] bits, as described in the previous section. Section 12.6.3 for detailed description of the VAON behavior in this particular scenario. and default operation will be recovered once the device exit the DFS state and the OTP fuses are reloaded.

12.4.4.2 Power-down delay

A programable delay after the power-down sequence can be set using the PD_SEQ_DLY[2:0] bits. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

000 No delay

Table 42. Delay after power-down sequence the value during the SYSTEM ON states via the PD_SEQ_DLY[2:0] bits. Figure 13. Power-down delay

12.5 RUN/STANDBY transitions

The PF09 provides independent configuration for the voltage regulators during the RUN and STANDBY states. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 14. RUN and STANDBY transitions

12.5.1 RUN to STANDBY transition

in the power-up sequence needs to be turned off in the STANDBY State. power-down slot assigned in the _SEQ[7:0] bits. ignored and the voltage transition happens at the beginning of the power-down sequence. time due to the external capacitor.

12.5.2 STANDBY to RUN transition

by any of the system regulators set up to enabled during the transition from STANDBY to RUN. configuration is set to OFF, the regulator will be disabled first, before the power-up sequencer is started. The PWRUP_I interrupt is set when the device has finished transitioning from STANDBY to RUN. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Nine-channel power management IC with advanced system safety monitoring

12.6 Fault management

The PF09 provides a flexible fault management scheme to detect and react to internal and external faults:

Voltage regulators are monitored internally for overvoltage, undervoltage, and overcurrent.
Dedicated inputs are used to monitor external supplies for overvoltage and undervoltage. In devices with safety monitoring, external error monitoring is provided via the XRESET, FCCU, and/or ERRMON interfaces. Internal random fault conditions are monitored through the various mechanisms provided by the functional safety architecture. Refer to Section 14 for detailed descriptions and fault handling of safety-related mechanisms. The fault protection mechanisms upon a system regulator fault can be programmed to one or more of the following reactions:
Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.
Disable the failing output if the corresponding _STATE bit is set to 0.
Start the fault timer, if programmed by the TIMER_FAULT[3:0] bits.
Assert the PGOOD pin low of the corresponding OV/UV, if fault condition is not bypassed.
Increase the fault counter, if the OV/UV fault condition is not bypassed.
Assert the FS0B pin (based on device configuration). The fault protection mechanisms upon an external VMONx OV/UV fault can be programmed to one or more of the following reactions:
Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.
Start the fault timer if programmed by the TIMER_FAULT[3:0] bits.
Assert the PGOOD pin low if the corresponding OV/UV if fault condition is not bypassed.
Increase the fault counter if the OV/UV fault condition is not bypassed.
Assert the FS0B pin (based on device configuration). The fault protection mechanisms upon an FCCU fault can be programmed to one or more of the following reactions:
Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.
Assert the FS0B pin.
Generate a reset condition as defined by the FCCUx_RESET[1:0] bits. The fault protection mechanisms upon an ERRMON fault can be programmed to one or more of the following reactions:
Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.
Assert the FS0B pin.
Generate a reset condition as defined by the ERRMON_RESET bit. Fault conditions are classified based on the severity of their reactions:
Hard faults: fault conditions that cause the device to start a power-down sequence. It is assumed that such a fault may limit the ability of the system (MCU) to properly acknowledge and recover from the fault condition, therefore the PMIC is required to take a definite action to bring the system to a known “good” state to resume proper operation.
Soft faults: fault conditions that do not start a power-down sequence. It is assumed such faults do not limit the ability of the system to acknowledge and try to act upon the fault condition. Soft faults are signalled by one or more mechanisms, such as the interrupt registers, INTB, FS0B_S or PGOOD pins. The MCU is expected to listen to any of these signals as defined by the system designer, and the system is expected to perform a PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring corrective action before the PMIC detects a lack of response and proceeds to evaluate the fault conditions as a hard fault.

12.6.1 Fault counter

The PF09 features a programmable fault counter to avoid fault cycling during system operation. The device uses the FAULT_MAX_CNT[3:0] bits to set the maximum number of soft faults allowed before the PMIC detects a cyclic fault condition and generates a hard fault condition. When the FAULT_MAX_CNT[3:0] = 0x00, the soft fault condition will still be detected but the system will not be able to generate a system shutdown due to a hard fault. When the FAULT_MAX_CNT[3:0] is different from 0x00, the PMIC will generate a hard fault when the FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0]. The default value of the FAULT_MAX_CNT[3:0] bits is set by the OTP_FAULT_MAX_CNT[3:0] bits to ensure the system starts operation with a valid configuration. However, the MCU is allowed to change the value of the FAULT_MAX_CNT[3:0] bits at any time to adjust the PMIC reaction to the needs of the application. If the FAULT_CNT[3:0] < FAULT_MAX_CNT[3:0], the device will initiate the corresponding fault protection mechanism based on the type of fault and the configuration in the functional register bits. OV, UV, and ILIM faults in the voltage regulators and external VMON will increased the fault counter only if the fault is not bypassed, and no other persistent OV, UV, or ILIM fault is currently present on any of the system regulators or external VMON blocks. FCCU and ERRMON faults will increase the FAULT_CNT[3:0] only if the FS0B pin transitions from high to low, to prevent multiple fault detections from a fault condition that hasn’t been properly cleared out by the MCU. The MCU is expected to implement a fault acknowledgement routine to read the faults and clear the fault counter when it has taken proper action, and the system is ready to resume normal operation. By implementing such a routine, the system ensures that no fault conditions are stacking up in the fault counter and prevents a random condition from generating a hard fault right away. The fault counter can be cleared manually by writing the FAULT_CNT[3:0] = 0x00 via an I2C command, or automatically by allowing the watchdog interface to reduce the counter gradually when a number of consecutive good watchdog refreshes have been performed. Refer to Section 14.4.3 for more details on using the watchdog interface to decrease the fault counter automatically.

12.6.2 System regulators and external VMON fault management

The switching regulators and LDOs are provided with internal voltage monitors to detect overvoltage (OV) and undervoltage (UV) conditions during the Power-up sequence and the SYSTEM ON states. Additionally, overcurrents are detected and protected during the system-on states by the ILIM mechanism. Note that the voltage monitoring is only able to detect and protect against OV/UV conditions in the monitored STANDBY state (OTP_LP_STBY = 0). If the device is configured to go into the low-power STANDBY state, all monitoring blocks will be disabled to allow the lowest quiescent current possible with the assumption that STANDBY is considered a safe state in which the system will not perform critical activity, therefore no safety monitoring is required. Refer to Section 13.3 for detailed operation and configuration of the OV/UV monitoring blocks. Fault reaction of the system regulators and external voltage monitors can be managed through the dedicated fault management bit provided for each block. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

12.6.2.1 Output state control

regulator is kept enabled or disabled when the corresponding regulator experiences an OV condition.

0 Output disabled

1 Output enabled

Table 43. Regulation reaction on OV condition regulator is kept enabled or disabled when the corresponding regulator experience an UV condition. Table 44. Regulation reaction on UV condition reaction of each specific supply during the system configuration sequence, during the booting stage. experience an OV/UV condition. Table 45. Bits used to disable regulator during UV or OV

0 Output remains disabled

switching regulator will be re-enabled 500 μs after the regulator output has finished its discharge cycle. regulator will allow up to 1000 μs to discharge the output before trying to turn the LDO back on. corresponding enable/mode bits. for each voltage regulator during the system configuration sequence during the booting stage.

12.6.2.2 Fault bypass control

fault for each voltage regulator and external voltage monitor. during the system configuration sequence at power-up.

0 Enabled

1 Bypassed

Table 47. ILIM protection bypass bit the desired configuration during the system configuration sequence at power-up. Table 48. OV protection bypass bit the desired configuration during the system configuration sequence at power-up. Table 49. UV protection bypass bit experience an OV/UV condition. Table 50. Bits to enable/disable regulators at UV/OV PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 50. Bits to enable/disable regulators at UV/OV...continued disabling the regulator, if programmed to turn off upon the specific fault. the corresponding PG_EN is set to 1. asserted if the interrupt is not masked.

12.6.2.3 Fault timer

hard fault in the event the soft-fault condition due to an OV,UV or ILIM cannot be cleared.

0000 Disabled

1101 Reserved

1110 Reserved

1111 Reserved

Table 51. Fault timer...continued timer will be restarted on the next fault condition. Fail-safe transition in order to keep track of the number failing events in the system. to each specific application.

12.6.3 VAON fault management

12.6.3.1 VAON always-on mode

state and the fault mode configuration during the SYSTEM ON states. considered a safety-related block during the safety analysis of the PMIC. VAON output is in regulation before the power-up sequence can be started. selected via the OTP_VAON_FMODE bit. detect the VAON falling below the VAON_LP_UV threshold and generate a full PMIC power-down sequence. system can re-enable the VAON regulator when it reaches the LPOFF state. programable OV/UV monitor on VAON. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

When OTP_VAON_FMODE = 0 the VAON reacts in “notification mode” upon an OV/UV condition. When OTP_VAON_FMODE = 1 the VAON reacts in “Reset mode” upon an OV/UV.

OV/UV Interrupt flag is set and the INTB pin asserted if the interrupt is not masked.
PGOOD is asserted if OV/UV condition is not bypassed and VAON_PG_EN = 1.
Fault counter is increased if OV/UV condition is not bypassed.
Global fault timer is started if OV/UV condition is not bypassed.
The FS0B pin will be asserted as defined by the pin configuration. If the VAON fault reaction is set to notification mode, the VAON regulator will not be turned off internally when a hard fault is detected and the device starts a power-down sequence. When the VAON fault reaction is set to RESET mode, an OV/UV fault condition can start the following protective mechanism:
The OV/UV Interrupt flag is set and the INTB pin asserted if the interrupt is not masked.
PGOOD is asserted if the OV/UV condition is not bypassed and VAON_PG_EN = 1.
Fault counter is increased if the OV/UV condition is not bypassed.
The FS0B pin will be asserted as defined by the pin configuration. The dedicated VAON fault timer is started if the OV/UV condition is not bypassed, and the PMIC will require the fault to be acknowledged to prevent a total system shutdown. When the VAON fault reaction is set to RESET mode, a dedicated fault timer is provided to allow the system to acknowledge an OV/UV fault before the VAON fault timer is expired. The MCU must acknowledge the OV/UV fault on the VAON regulator by clearing the corresponding VAON_OV_I or VAON_UV_I interrupt flags. If the fault condition is still present by the time the VAON_OV_I or VAON_UV_I flags are cleared, the flag will be set again right away and the VAON fault timer is restarted. The default duration of the VAON fault timer is set via the OTP_VAON_TFLT[2:0] bits and it can be modified during the system-on states via the VAON_TFLT[2:0] bits. VAON_TFLT [2:0] VAON fault timer 000 500 us 001 1 ms 010 2 ms 011 5 ms 100 10 ms 101 25 ms 110 50 ms 111 100 ms

Table 52. VAON fault timer duration PMIC reset if the condition is not corrected. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

will resume normal operation until a new OV/UV condition is detected. power-down delay will be applied after the VAON is disabled, to allow the VAON output to be discharged. supply will be re-enabled as soon as the state machine enters the LPOFF state. interrupt event to allow the system to track the fault conditions with a lower priority.

VAON_FLT_REN
VAON_OV_STATE
VAON_UV_STATE The table below summarizes the fault management strategy for the VAON supply in Always-on node. State Fault mode (OTP_VAON_FMODE) Fault reaction OFF states Don’t care An UV condition in the VAON supply crossing the VAON_LP_UV threshold will generate a self-reset of its output. OTP_VAON_FMODE = 0 OV/UV interrupt is generated PGOOD Asserted. Fault counter increased. Global fault timer started. RUN state and monitored STANDBY OTP_VAON_FMODE = 1 OV/UV Interrupt is generated PGOOD asserted. Fault counter increased. VAON fault timer started. MCU must acknowledge and clear OV/UV flags. If fault condition is cleared, return to normal operation If fault condition is not cleared, hard fault includes VAON. OTP_VAON_FMODE = 0 UV/OV conditions are ignored. Low-power STANDBY OTP_VAON_FMODE = 1 An UV crossing the VAON_LP_UV threshold will generate a full PMIC power down (including the VAON)

Table 53. VAON always-on fault management strategy

12.6.3.2 VAON as system regulator

when an OV/UV fault is detected in the VAON supply. circuits are disabled, therefore the PF09 will not detect any OV/UV condition in the VAON output.

OV/UV interrupt flag is set and INTB pin asserted if the interrupt is not masked. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

PGOOD is asserted if OV/UV condition is not bypassed and VAON_PG_EN = 1.
Fault counter is increased if OV/UV condition is not bypassed.
Global fault timer is started if OV/UV condition is not bypassed.
The VAON output is disabled if the VAON_OV_STATE / VAON_UV_STATE = 0.
The VAON output will be re-enabled automatically if the VAON_FLT_REN = 1
The FS0B pin will be asserted as defined by the pin configuration.
During the hard fault, the VAON will be disabled as indicated by the power-down sequence (VAON_SEQ[7:0] bits). State Fault mode (OTP_VAON_FMODE) Fault reaction RUN State and monitored STANDBY Don’t care OV/UV interrupt is generated PGOOD asserted. Fault counter increased. Global fault timer started. Hard fault includes VAON (in sequencer). Low-power STANDBY Don’t care No monitoring available.

Table 54. VAON System regulator fault management

12.6.4 Fault monitoring during time-based power up

the Power-up sequence. It is used as a gating condition to release or not release the RSTB pin. Table 55. OTP_PWRUP_CHK bit RSTB is released will start checking for faults after their corresponding blanking period. sequence and a power-good condition is required to release the RSTB. the Power-up sequence will continue. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 17. Power-up failure with persistent fault condition as described in section Section 12.6.2. management rules during the SYSTEM ON states. the RSTB is ready to be de-asserted, since the PG_EN bits for all regulators are reset to 1 at power up. conditions due to the regulators ramping up too slowly. a power good condition (system-level configuration).

12.6.5 Fault monitoring during dynamic power up

until all regulators enabled previously are in regulation. regulators to ramp up and reach regulation. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

12.7 System diagnostics

12.7.1 System fault flags

VIN goes below the VIN_POR threshold
The device is in the ULPOFF state.
VDIG supply is shorted externally (fault condition) Table 56 provides a summary of the system diagnostic faults available in the PF09 devices. Diagnostic flag Description DCRC_FLG Flag is set when a dynamic CRC error is present DFS_FLG Flag is set when device is waking up from the DFS state VIN_OV_FLG Flag is set when a VIN_OV condition is present XFAIL_FLG Flag is set when a power-down event was initiated via the XFAILB pin. WD_FLG Flag is set when a watchdog reset event is initiated. XRESET_FLG Flag is set when an external reset is requested via the XRESET or FCCU blocks SFAULT_FLG Flag is set when a soft fault is present (OV/UV/ILIM) HFAULT_FLG Flag is set when a hard fault is present.

Table 56. System diagnostic flags The hard-fault event has dedicated flags to trace the source of failure. edge, to indicate the device is waking up from the DFS state after a VIN < UVDET condition. PU_FAIL A power-up failure started the hard fault. TSD_FAIL A power-down sequence is initiated due to a thermal shutdown event. Table 57. Hard-fault Flags previous failure, provided the state machine is able to power up successfully after such a failure. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

12.7.2 Interrupt management

by the PF09. The INTB pin is a reflection of a logic OR of all the interrupt status bits allowed to control the pin. interrupt registers provide the exact source for the interrupt event. level interrupt bit on the SYSTEM_INT register is cleared automatically.

STATUS1_INT STATUS2_I Bit is set when interrupt is generated in registers:
STATUS2_INT
STATUS3_INT MODE_I Bit is set when interrupt is generated in register:
SW_MODE_INT ILIM_I Bit is set when interrupt is generated in registers:
SW_ILIM_INT
LDO_ILIM_INT UV_I Bit is set when interrupt is generated in registers:
SW_UV_INT
LDO_UV_INT OV_I Bit is set when interrupt is generated in registers:
SW_OV_INT
LDO_OV_INT GPIO_I Bit is set when interrupt is generated in registers:
PWRON_INT
IO_INT EWARN_I The EWARN_I is the only interrupt bit in the system without a mask bit, and it will cause the INTB pin to assert every time a critical fault is causing the device to shut down.

Table 58. System interrupt flags write a 1 to the corresponding status bit to clear the interrupt. assert when the power-up sequence is finished. conditions. Interrupts generated by transient faults or events do not provide sense bits.

0 No event present Asserts INTB (not-masked) Condition is not present

1 Event latched Does not assert INTB (masked) Condition is currently present

Table 61. I/O pin sense bits...continued

12.7.3 System test commands

The SYS_CMD[7:0] bit field is provided to request various system tests or commands. Table 62. SYS_CMD[7:0] bit field INTB pin if the interrupt is not masked.

12.8 I/O interface pins

Figure 20. PF09 System interface IO signals

12.8.1 Interfacing I/O electrical characteristics

TA = 25 °C unless otherwise noted.

Minimum voltage to ensure a high state 1.4 – – V VIL_PWRON PWRON input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_PWRON PWRON input buffer hysteresis 60 – – mV RPD_PWRON PWRON internal pulldown – 10 25 MΩ STBY VIN_MAX_STBY Maximum input voltage – – 5.5 V

TA = 25 °C unless otherwise noted.

Minimum voltage to ensure a high state 1.4 – – V VIL_STBY STBY input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_STBY STBY input buffer hysteresis 100 – – mV FCCU1 (XRESET Mode) VIN_MAX_XRESET Maximum input voltage – – 5.5 V VIH_XRESET XRESET input high voltage
Minimum voltage to ensure a high state 0.7*VDDIO – – V VIL_XRESET XRESET input low voltage
Maximum voltage to ensure a low state – – 0.3*VDDIO V IHYS_XRESET XRESET input buffer hysteresis 100 – – mV RPD_XRESET XRESET internal pull-down 400 800 1300 kΩ INTB VOL_INTB INTB output low voltage
Maximum voltage at 10 mA load – – 0.4 V IOL_INTB INTB output low current – – 10 mA tINTB_PULSE INTB test pulse 90 100 110 μs VIN_MAX_RSTB Maximum input voltage – – 5.5 V RSTB VIH_RSTB RSTB input high voltage
Minimum voltage to ensure a high state 1.4 – – V VIL_RSTB RSTB input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_RSTB RSTB input buffer hysteresis 100 – – mV VOH_RSTB_VDDIO RSTB output high voltage
OTP_RSTB_MODE [1:0] = 01. VDDIO – 0.5 – – V VOH_RSTB_VAON RSTB output high voltage
OTP_RSTB_MODE [1:0] = 10 VAON – 0.5 – – V VOL_RSTB RSTB output low voltage
Maximum voltage at 10mA load – – 0.4 V IOL_RSTB RSTB output low current – – 10 mA IOH_RSTB RSTB output high current
OTP_RSTB_MODE = 01 or 10 – – 2 mA tRSTB_PULSE RSTB pulse duration 90 100 110 μs PGOOD VIN_MAX_PGOOD Maximum input voltage – – 5.5 V

TA = 25 °C unless otherwise noted.

Minimum voltage to ensure a high state 1.4 – – V VIL_PGOOD PGOOD input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_PGOOD PGOOD input buffer hysteresis 100 – – mV VOL_PGOOD PGOOD output low voltage
Maximum voltage at 10 mA load – – 0.4 V IOL_PGOOD PGOOD output low current – – 10 mA GPIO1 VIN_MAX_GPIO1 Maximum input voltage – – 5.5 V VIH_GPIO1 GPIO1 input high voltage
Minimum voltage to ensure a high state 1.4 – – V VIL_GPIO1 GPIO1 input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_GPIO1 GPIO1 input buffer hysteresis 100 – – mV VOL_GPIO1 GPIO1 output low voltage
Maximum voltage at 10 mA load – – 0.4 V IOL_GPIO1 GPIO1 output low current – – 10 mA VOH_GPIO1_VIN GPIO1 output high voltage
OTP_GPIO1_MODE[1:0] = 01 (push-pull to VIN)
Load current = 2 mA VIN – 0.5 – – V IOH_GPIO1 GPIO1 output high current – – 2 mA RPD_GPIO1 GPIO1 internal pull-down
In VESELECT mode 1 2 4 MΩ GPIO2 VIN_MAX_GPIO2 Maximum input voltage – – 5.5 V VIH_GPIO2 GPIO2 input high voltage
Minimum voltage to ensure a high state 1.4 – – V VIL_GPIO2 GPIO2 input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_GPIO2 GPIO2 input buffer hysteresis 100 – – mV VOL_GPIO2 GPIO2 output low voltage
Maximum voltage at 10 mA load – – 0.4 V IOL_GPIO2 GPIO2 output low current – – 10 mA VOH_GPIO2_VIN GPIO2 output high voltage
OTP_GPIO2_MODE[1:0] = 01 (push-pull to VIN)
Load current = 2 mA VIN – 0.5 – – V IOH_GPIO2 GPIO2 output high current – – 2 mA

TA = 25 °C unless otherwise noted.

In LDO1EN mode 1 2 4 MΩ GPIO3 VIN_MAX_GPIO3 Maximum input voltage – – 5.5 V VIH_GPIO3 GPIO3 input high voltage
Minimum voltage to ensure a high state 1.4 – – V VIL_GPIO3 GPIO3 input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_GPIO3 GPIO3 input buffer hysteresis 100 – – mV VOL_GPIO3 GPIO3 output low voltage
Maximum voltage at 10 mA load – – 0.4 V IOL_GPIO3 GPIO3 output low current – – 10 mA VOH_GPIO3_VIN GPIO3 output high voltage
OTP_GPIO3_MODE[1:0] = 01 (push-pull to VIN)
Load current = 2 mA VIN – 0.5 – – V IOH_GPIO3 GPIO3 output high current – – 2 mA GPIO4 VIN_MAX_GPIO4 Maximum input voltage – – 5.5 V VIH_GPIO4 GPIO4 input high voltage
Minimum voltage to ensure a high state 1.4 – – V VIL_GPIO4 GPIO4 input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_GPIO4 GPIO4 input buffer hysteresis 100 – – mV VOL_GPIO4 GPIO4 output low voltage
Maximum voltage at 10mA load – – 0.4 V IOL_GPIO4 GPIO4 output low current – – 10 mA VOH_GPIO4_VIN GPIO4 output high voltage
OTP_GPIO4_MODE[1:0] = 01 (push-pull to VIN)
Load current = 2 mA VIN – 0.5 – – V FS0B VIN_MAX_FS0B Maximum input voltage – – 5.5 V VIH_FS0B FS0B input high voltage
Minimum voltage to ensure a high state 1.4 – – V VIL_FS0B FS0B input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_FS0B FS0B input buffer hysteresis 100 – – mV VOL_FS0B FS0B output low voltage
Maximum voltage at 10mA load – – 0.4 V

TA = 25 °C unless otherwise noted.

Minimum voltage to ensure a high state 1.4 – – V VIL_XFAILB XFAILB input low voltage
Maximum voltage to ensure a low state – – 0.4 V IHYS_XFAILB XFAILB input buffer hysteresis 100 – – mV VOL_XFAILB XFAILB output low voltage
Maximum voltage at 10 mA load – – 0.4 V IOL_XFAILB XFAILB output low current – – 10 mA RXPU_XFAILB XFAILB external pullup
Pullup to VANA – 10 – kΩ CXFAILB XFAIL recommended decoupling EMC capacitance – 100 – nF I2C interface VOL_SDA SDA output low voltage
Maximum voltage at 20 mA load – – 0.4 V VIH_SDA SDA input high voltage
Minimum voltage to ensure a high state 0.7*VDDIO – – V VIL_SDA SDA input low voltage
Maximum voltage to ensure a low state – – 0.3*VDDIO V VIH_SCL SCL input high voltage
Minimum voltage to ensure a high state 0.7*VDDIO – – V VIL_SCL SCL input low voltage
Maximum voltage to ensure a low state – – 0.3*VDDIO V FI2C_FMP I2C operating frequency
Fast-mode plus – – 1 MHz FI2C_HS I2C operating frequency
High speed – – 3.4 MHz RXPU_SCL_FMP SCL external pullup Fast mode plus
Pullup to VDDIO
I2C Fast mode – 2.2 – kΩ RXPU_SDA_FMP SDA external pullup Fast mode plus
Pullup to VDDIO
I2C Fast mode – 2.2 – kΩ

TA = 25 °C unless otherwise noted.

Pullup to VDDIO
I2C high speed – 0.8 – kΩ RXPU_SDA_HS SDA external pullup high speed
Pullup to VDDIO
I2C high speed – 0.8 – kΩ

12.8.2 PWRON

modes of operations as programmed by the OTP_PWRON_MODE bit.

0 Level Sensitive

1 Edge Sensitive

Table 64. PWRON operation mode Refer to Section 12.3 for details on power-up requirements.

12.8.2.1 Level-sensitive mode

to generate a power on/off event by controlling the pin high or low, respectively. PWRON pin high will generate a power-on event. automatically when the main power is applied.

12.8.2.2 Edge-sensitive mode

resistor connected to a pushbutton or a controlled signal to generate a Falling-edge pulse on the PWRON pin. device is in the LPOFF state. edge transition and holding the PWRON pin low for as long as the selected time to reset (TRESET). Table 65. Time to reset PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 65. Time to reset...continued the rising and Falling edges. Table 66. PWRON pin debounce when the PWRON pin is held low for longer than 1 s, 2 s, 3 s, 4 s and 8 s respectively.

12.8.3 STBY

will return to the RUN state. The STBY pin is programmable as active-high or active-low using the STBY_POL bit. Table 67. STBY pin polarity The OTP_STBY_POL bit is provided to set the default value of the STBY_POL bit. STANDBY state when the STBY pin is toggled, and to prevent random access to the STANDBY state. need for any STANDBY request command. The OTP_STBY_REQ bit is provided to configure the operation of the STANDBY request window. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

0 Always open

1 Open on request

Table 68. STANDBY request window STANDBY states at any time by toggling the STBY pin, as defined by the STBY_POL polarity bit. STBY_POL bit via I2C communication within the open window (20 ms). the window and send a BAD_CMD_I interrupt to notify the system that the STANDBY request was not fulfilled.

12.8.4 INTB

PMIC. In the application, INTB is typically pulled up to VDDIO with an external 100 kΩ resistor. the INTB pin will assert for 100 μs and then de-assert to its normal state. can then monitor whether the pin is able to toggle high and low as expected. Refer to Section 12.7.2 for detailed information about the events reported through the INTB pin.

12.8.5 RSTB

(and peripherals) into and out of RESET. The OTP_RSTB_MODE[1:0] bit is provided to select the type of buffer used on the RSTB pin.

00 Open drain

01 Push-pull to VDDIO

10 Push-pull to VAON

11 Open drain

the OTP_RSTB_MODE[1:0] bits. to 100 kΩ external resistor. condition until a Power-up sequence is generated successfully.

12.8.5.1 RSTB pin diagnostic

maximum acceptable time before a short in the RSTB pin is considered a fault condition.

00 Hard fault disabled

Table 70. RSTB short-detection timer be reported to the MCU via the RSTB_FLT_I. detection timer is used to ensure the RSTB pin state is indeed high. counting before it can consider such event as a fault condition. The RSTB_S flag is provided to read the real-time state of the RSTB pin.

0 Low

1 High

Table 71. State of RSTB pin on the RSTB pin. If the RSTB_FLT_I interrupt is unmasked, the INTB pin will be driven low. The RSTB_FLT_I bit can be cleared by writing a 1 to it. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

assert for 100 μs and then de-assert to its normal state. and asserts the RSTB_FLT_I flag.

12.8.6 PGOOD

be pulled up to VDDIO (1.8 V or 3.3 V) with a 10 kΩ to 100 kΩ external resistor. device. Each PG monitor reports its status via I2C registers. The status of the PGOOD pin is a logic AND function of the internal PG signals of the selected voltage monitors. The selection of the regulators being reported by the PGOOD pin is done via the PG_EN bits.

0 SW1 does not control PGOOD

1 SW1 controls PGOOD

0 SW2 does not control PGOOD

1 SW2 controls PGOOD

0 SW3 does not control PGOOD

1 SW3 controls PGOOD

0 SW4 does not control PGOOD

1 SW4 controls PGOOD

0 SW5 does not control PGOOD

1 SW5 controls PGOOD

0 LDO1 does not control PGOOD

1 LDO1 controls PGOOD

0 LDO2 does not control PGOOD

1 LDO2 controls PGOOD

0 LDO3 does not control PGOOD

1 LDO3 controls PGOOD

0 VAON does not control PGOOD

1 VAON controls PGOOD

0 VMON1 does not control PGOOD

1 VMON1 controls PGOOD

0 VMON2 does not control PGOOD

1 VMON2 controls PGOOD

Table 72. Voltage reels PGOOD triggers...continued below the programmed OV/UV thresholds. refer to section 16.7.2 Interrupt Management. or VMON blocks enabled in the system. as long as there are one or more regulators/VMONs enabled in the system. power good monitoring during the Power-up sequence.

12.8.6.1 PGOOD pin diagnostic

The PGOOD_S flag is provided to read the real-time state of the PGOOD pin. Table 73. PGOOD_S flag unmasked, the INTB pin will be asserted low. The PGOOD_FLT_I can be cleared by writing a 1 to it. be set HIGHuntil the condition is cleared. set HIGH until the condition is cleared.

12.8.7 FS0B

The operation of the FS0B pin depends on the safety integrity level of the device. In non-safety devices (QM), the FS0B pin operates in Fault status mode. In automotive safety devices (ASIL B/C/D), the FS0B pin operates in Active Safe-state mode. In industrial safety devices (SIL 2) the FS0B pin operates in Active Safe-state mode. Detailed description of the Active Safe-state mode is provided in section 18.5 FS0B Active Safe State Mode.

12.8.7.1 Fault status mode

able to control the FS0B pin. the FS0B pin to report the fault condition to the system. section 16.7.1 System Fault Flags for a detailed description of the system fault flags.

Fault timer expired
FAULT_CNT = FAULT_MAX_CNT
RESET_CNT = RESET_MAX
Power up failure
Thermal shutdown
The RSTB pin short-to-low detected.
VIN crossing the UVDET on the Falling edge

Table 74. FS0B Fault control bits

12.8.8 FCCU1 (XRESET mode)

OTP_FCCU1_MODE[1:0] bits to enable the external reset (XRESET) operation. Table 75. FCCU1 pin operation when FCCU block is not available in the system. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

OTP_FCCU1_MODE[1:0] and OTP_FCCU0_MODE[1:0] bits. Table 76. FCCU1 pin operation when FCCU block is available in the system. [1] For a detailed description of the FCCU operation, refer to section 18.7 FCCU Monitoring. [2] Code 10 in the OTP_FCCU1_MODE[1:0] shall not be used when the FCCU Bistable mode is selected. 16.4.2 Reset Conditions for a detailed description of the implementation of a reset condition. The polarity to detect a reset condition on the XRESET input is configured using the FCCU1_POL bit.

0 Reset event on rising edge

1 Reset event on Falling edge

Table 77. XRESET polarity The OTP_FCCU1_POL bit is provided to set the default value for the FCCU1_POL at power-up. either the rising or Falling edge of the XRESET input. Table 78. XRESET debounce timer The XRST_MODE bit is provided to set the reset type generated upon an XRESET event. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 79. XRST_MODE The OTP_XRST_MODE bit is provided to set the default value of the XRST_MODE at power-up. the external reset signal in the STANDBY state via the XRST_STBY_EN bit. Table 80. XRST_STBY_EN bit The OTP_XRST_STBY_EN is used to set the default operation of the XRESET input in the STANDBY state.

12.8.9 GPIO1

operation via the OTP_GPIO1_MODE[1:0] bit.

00 Open-drain output

01 Push-pull output

10 Reserved

11 VSELECT input

Table 81. GPIO1 mode The GPIO1_S flag is provided to read the real-time state of the GPIO1 pin. Table 82. GPIO1_S flag

12.8.9.1 GPO mode

states. It can be set high by default during the Power-up sequence, or manually during the system-on states. external resistor between 10 kΩ to 470 kΩ. present during OFF condtions. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

a detailed description of the Power-up sequence. to allow full control of the GPIO1 when going in and out of the STANDBY state. In the RUN state, the level of the GPIO1 pin can be controlled manually via the GPIO1_RUN bit. Table 83. GPIO1 state in RUN In the STANDBY state, the level of the GPIO1 pin can be controlled manually via the GPIO1_STBY bit. Table 84. GPIO1 state in STANDBY

12.8.9.2 VSELECT mode

resistor to force a solid low condition in the event of a floating pin. operation, the GPIO1 will operate as a GPO output regardless of the value in the OTP_GPIO1_MODE bit. or via the I2C bits (VLDO2_RUN[4:0] / VLDO2_STBY[4:0]).

0 X VLDO2_RUN[4:0] / VLDO2_STBY[4:0]

Table 85. LDO2 voltage selection VSELECT_I interrupt every time the VSELECT input toggles.

12.8.10 GPIO2

The GPIO2 pin is a programable general-purpose IO with a selectable open-drain or push-pull output buffer. operation via the OTP_GPIO2_MODE[1:0] bit. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

11 LDO1EN input

Table 86. GPIO2 mode The GPIO2_S flag is provided to read the real-time state of the GPIO2 pin. Table 87. GPIO2_S flag

12.8.10.1 GPO mode

states. iI can be set high by default during the Power-up sequence, or manually during the system-on states. selection must ensure that the pullup voltage is not present during off condtions. a detailed description of the Power-up sequence. to allow full control of the GPIO2 when going in and out of the STANDBY state. In the RUN state, the level of the GPIO2 pin can be controlled manually via the GPIO2_RUN bit. Table 88. GPIO2 state in RUN In the STANDBY state, the level of the GPIO2 pin can be controlled manually via the GPIO2_STBY bit. Table 89. GPIO2 state in STANDBY PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

12.8.10.2 LDO1EN mode

resistor to force a solid low condition in the event of a floating pin. the regulator in RUN or STANDBY states respectively (software control). Table 90. LDO1EN mode LDO1EN_I interrupt every time the LDO1EN input toggles.

12.8.11 GPIO3

The GPIO3 pin is a programmable general-purpose IO with a selectable open-drain or push-pull output buffer. ERRMON fault monitoring operation via the OTP_GPIO3_MODE[1:0] bits.

11 ERRMON input

Table 91. GPIO3 mode Refer to section 18.6 External Error monitoring (ERRMON) for a detailed description of the ERRMON operation. working as an input or an output. Table 92. GPIO3 state

12.8.11.1 GPO mode

states. It can be set high by default during the Power-up sequence, or manually during the system-on states. selection must ensure that the pullup voltage is not present during OFF condtions. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

a detailed description of the Power-up sequence. to allow full control of the GPIO3 when going in and out of the STANDBY state. In the RUN state, the level of the GPIO3 pin can be controlled manually via the GPIO3_RUN bit. Table 93. GPIO3 state in RUN state In the STANDBY state, the level of the GPIO3 pin can be controlled manually via the GPIO3_STBY bit. Table 94. GPIO3 state in STANDBY state

12.8.12 GPIO4

The GPIO4 pin is a programmable general-purpose IO with a selectable open-drain or push-pull output buffer. The GPIO pin is configurable as a general-purpose output (GPO) via the OTP_GPIO4_MODE[1:0] bits. Table 95. GPIO4 mode The GPIO4_S flag is provided to read the real-time state of the GPIO4 pin. Table 96. GPIO4_S flag

12.8.12.1 GPO mode

states. It can be set high by default during the Power-up sequence, or manually during the system-on states. external resistor between 10 kΩ and 470 kΩ. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

present during off condtions. a detailed description of the Power up sequence. to allow full control of the GPIO4 when going in and out of the STANDBY state. In the RUN state, the level of the GPIO4 pin can be controlled manually via the GPIO4_RUN bit. Table 97. GPIO4 state in RUN In the STANDBY state, the level of the GPIO4 pin can be controlled manually via the GPIO4_STBY bit. Table 98. GPIO4 state in STANDBY

12.8.13 XFAILB

V to 5.5 V, typically pulled up to VANA in order to reduce current consumption during the Low-power off state. Additionally, a 100 nF capacitor is recommended to improve the EMC performance. The OTP_XFAILB_EN bit is used to enable or disable the XFAILB mode of operation. Table 99. XFAIL operation ON states. Because of this, no synchronization is possible.

12.8.13.1 Power-up synchronization

pin is no longer held low externally. Figure 21. XFAILB during Power-up

12.8.13.2 Power-down synchronization

device starts turning off all the supplies that were already turned on during the Power-up sequence. sequence failure, assert its own XFAILB pin, and turn off all supplies immediately. synchronize the power-down sequence of all the PMICs connected together. low internally, and the device will start a power-down sequence. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

12.8.14 I2C Interface

various system requirements. will depend on the maximum speed used in the system, as shown in the table below. Table 100. I2C mode of operations and user manual UM10204 available at https://www.nxp.com/. The default I2C device address is set in OTP during the part definition stage via the OTP_I2C_ADD[2:0] bit field. Table 101. Setting up the I2C device address the command and wait for a valid I2C transaction. a new transaction each time. communication overview application note found at https://www.nxp.com/. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

and avoid system failures that could be caused by incorrect data.

12.8.14.1 I2C CRC verification

Table 102. Enabling the I2C CRC mechanism Figure 24. I2C CRC Polynomial package, to make a total of 32 bits per transaction. the CRC sent by the MCU, to ensure the configuration command has not been corrupted. When a CRC fault is detected, the device ignores the current configuration command and sets the I2C_CRC_I. the I2C CRC interrupt will assert the INTB pin if the interrupt is not masked.

12.8.14.2 I2C secure write

Table 103. Enabling I2C secure write

The MCU sends a command to modify the secure registers
The MCU reads a random code generated by the PMIC from the RANDOM_GEN register
The MCU must write the correct random code in the RANDOM_CHK register.

as requested by the initial command. waits for a new transaction. transaction and perform the new I2C command. and the device will be ready for a new transaction. The following table provides a list of all the bits requiring a secure write protocol when I2C_SECURE_EN = 1. Table 104. Bit groups that may require a secure write protocol PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

13 Functional blocks

13.1 Analog core and internal references

13.1.1 VANA

disabled during the ULPOFF, LPOFF and DFS states to reduce power consumption on those states. will move to the Deep Fail-safe state (DFS). the interrupt is not masked. The VANA_OV_S bit provides the real-time status of the VANA overvoltage monitor.

0 No OV detected

1 OV detected

Table 105. VANA overvoltage status

13.1.2 VDIG

disabled only during the ULPOFF states, to achieve the lowest power consumption in this state. proper safe reaction even if such a condition causes the main digital controller to be unresponsive. The VDIG_OV_S bit provides the real-time status of the VDIG overvoltage monitor. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 106. VDIG overvoltage status

13.1.3 Internal bandgap references

monitoring bandgap throughout this document.

13.2 System voltage generation

13.2.1 VAON

supports configurable output voltage with nominal current of 10 mA. The VAON output is programmable to 1.8 V, 3.0 V or 3.3 V with up to +/- 2% accuracy.

00 Off

Table 107. VAON output voltage and the OTP_VAON_SEQ[7:0] bits.

00 Don’t care System regulator Default off (enabled via I2C)

Table 108. VAON modes

13.2.1.1 Always-on mode

event when the device experiences a new cold boot or is able to wake up from the DFS state.

13.2.1.2 System regulator mode

MCU to enable the supply on the go at the required voltage level.

13.2.1.3 Electrical characteristics

Ta = 25 °C, unless otherwise noted.

Max IQ at TA = 85°C – 2 5 µA ILIM_VAON VAON current limit 30 – 60 mA VAON_PSRR_AC AC power supply rejection ratio
400 kHz
100 µA < IAON ≤ 10 mA
VIN = VAON + 300 mV 30 – – dB RDSON_VAON VAON dropout mode resistance – – 5 Ω RPD_VAON VAON discharge pulldown resistor – 60 100 Ω VAON_OS VAON startup overshoot – – 200 mV VAON_AC VAON load transient IAON_AC: 0 mA to 10 mA -100 – 100 mV VAON_TON VAON turn-on time
VAON enabled to 90 % of final value – – 1.7 ms VAON_ACC VAON output voltage accuracy -2 – 2 % VAON_LOR VAON DC load regulation -1 – 1 % VAON_LIR VAON DC line regulation -1 – 1 % IVAON VAON nominal output current 10 – – mA VAON_DROP VAON LDO minimum headroom
Minimum headroom to ensure regulation. 200 – – mV VAON_LP_UV VAON low-power undervoltage threshold 1.4 1.5 1.6 V

VSW1_RUN[7:0] functional bits. SW1 regulator during any of the SYSTEM ON states via the VSW1_STBY[7:0] functional bits. mode it wants to achieve at the system level. Table 110. SW1 output voltage configuration bits

Dynamic voltage scaling (DVS) range is between 0.65 V and 0.9 V.
The OV/UV threshold is +/-5% or wider.
DVS ramp must be 3.9 mV/μs or slower.

voltages are not changed by mistake during the SYSTEM ON states. The OTP_SW1_DVS[1:0] bits are used to program the default slew rate for the SW1 turn-on and turn-off ramps. Table 111. DVS ramp selection bits [1] At 20 MHz high frequency clock selection. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

able to fully discharge before a new turn-on cycle is started. the system requires a faster discharge on the SW1 regulator.

0 Same as ramp up

Table 112. DVS ramp-down selection bits selected limits defined for a specific application. Table 113. Maximum DVS selection bits INTB pin if the interrupt is not masked. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

selected limits defined for a specific application. Table 114. Minimum DVS selection bits

01 PWM

10 PFM

01 PWM[1]

Table 116. Mode selection in STANDBY...continued [1] PWM selection is only available during the monitored STANDBY state. The regulator will operate in PFM when the device is in the LP_STANDBY state. The default value for the SW1_STBY_MODE[1:0] bits is loaded at power-up from the OTP_SW1_STBY_EN bit.

0 OFF

1 PFM

Table 117. Default SW1 mode selection during STANDBY current limit is loaded at power up from the OTP_SW1_ILIM[1:0] bits. Table 118. Current limit selection bits phase is loaded at power up from the OTP_SW1_PH[2:0] bits. Table 119. SW1 phase shift selection bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

and off as required by the system. connected to the SW1FB pin to monitor the output voltage.

0 Regulator mode

1 Load switch mode

Table 120. Load switch mode selection bit SW1_RUN_MODE[1:0] and SW1_STBY_MODE[1:0] in the RUN and STANDBY states respectively.

00 Output disable (HS FET open)

01 Output enabled (without monitoring)

10 Output enabled (with monitoring)

11 Reserved (output disabled)

Table 121. SW1LS control bits Table 122. SW1LS default STANDBY configuration generate an OV/UV condition. enabled and will expect a voltage as selected by the VSW1_RUN[7:0] bits. monitoring thresholds are wide enough to account for voltage losses in the load switch. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

present. The default value of the SW1LS_OCP bit is set in OTP via the OTP_SW1LS_OCP bit.

1 SW1LS OFF

Table 123. SW1LS overcurrent protection bit The SW1LS_OCP_I interrupt will assert the INTB pin if the interrupt is not masked. clearing the SW1LS_OCP_I bit.

13.2.2.2 Electrical characteristics

VSW1FB = 3.3 V, ISW1 = 1000 mA, and Ta = 25 °C, unless otherwise noted.

Minimum headroom = VSW1FB + IOUT_MAX * RON / DC.
IOUT_MAX = minimum ILIM selected for SW1
RON includes HS FET RDSON, bond wire resistance, PCB trace resistance and inductor DCR.
Maximum duty cycle = 100% UVDET – 5.5 V fSW Operating switching frequency 1.9 – 3.15 MHz VSW1ACC3 Output voltage accuracy
PWM mode
0.5V ≤ VSW1FB < 0.8V -10 – 10 mV VSW1ACC1 Output voltage accuracy
PWM mode
0.8V ≤ VSW1FB < 1.35V -1.5 – 1.5 % VSW1ACC2 Output voltage accuracy
PWM Mode
1.5V ≤ VSW1FB ≤ 3.3V -1.5 – 1.5 % VSW1PFMACC3 Output voltage accuracy
PFM mode
0.5V ≤ VSW1FB < 0.8 V -20 – 20 mV VSW1PFMACC1 Output voltage accuracy
PFM mode
0.8V ≤ VSW1FB < 1.35 V -3 – 3 % VSW1PFMACC2 Output voltage accuracy
PFM Mode -3 – 3 %

VSW1FB = 3.3 V, ISW1 = 1000 mA, and Ta = 25 °C, unless otherwise noted.

1.5V ≤ VSW1FB ≤ 3.3V VSW1RIPPLE Output voltage ripple
PWM mode
Frequency Spread spectrum Disabled – 6 – mV ISW1 SW1 nominal current 3.5 – – A ILIM1_SW1 SW1 current limit
SW1_ILIM[1:0] = 01 2.8 4.0 5 A ILIM2_SW1 SW1 current limit
SW1_ILIM[1:0] = 10 3.8 5.0 6 A ILIM3_SW1 SW1 current limit
SW1_ILIM[1:0] = 00 or 11 4.75 6 7 A ILIMN_SW1 Negative current limit 1.8 2.5 3.62 A VSOS_SW1 Startup overshoot
SW1_DVS[1:0] = 11 (15.6 mV/μs)
VSW1IN = 5.0 V
VSW1FB = 3.3 V -25 25 50 mV tONMIN_SW1 Turn-on time
From 10 % to 90 % of end value
SW1_DVS[1:0] = 11 (15.6 mV/μs)
VSW1IN = 5.0 V
VSW1FB = 0.5 V 32 – – µs tONMAX_SW1 Maximum turn-on time
From 10 % to 90 % of end value
SW1_DVS[1:0] = 00 (1.95 mV/μs)
VSW1IN = 5.0 V
VSW1FB = 3.3 V – – 1690 µs ηSW1_PWM1 PWM efficiency at full load (see Table 12)
VSW1IN = 5.0 V
VSW1FB = 3.3 V
fSW1 = 2.5 MHz
TA = 25 °C – 90 – % ηSW1_PWM2 PWM efficiency at 40% load
VSW1IN = 5.0 V
VSW1FB = 3.3 V
fSW1 = 2.5 MHz
TA = 25 °C – 94 – % ηSW1_PWM3 PWM efficiency at full load (see Table 12)
VSW1IN = 5.0 V
VSW1FB = 0.8 V
fSW1 = 2.5 MHz
TA = 25 °C – 73 – %

VSW1FB = 3.3 V, ISW1 = 1000 mA, and Ta = 25 °C, unless otherwise noted.

VSW1IN = 5.0 V
VSW1FB = 0.8 V
fSW1 = 2.5 MHz
TA = 25 °C – 81.5 – % tDB_SW1 Dead-band time – 3 5 ns tLXSR1_SW1 Switching node slew time – 2.5 – ns VLOTR1_SW1 Transient load regulation (single phase)
0.5 V ≤ VSW1FB ≤ 1.35 V
ISTEP = 200 mA to 1.0 A, di/dt = 2.0 A/μs
fSW = 2.5 MHz , COUT = 44 μF, LOUT = 0.47 μH
VIN = 5.0 V -25 – 25 mV VLOTR2_SW1 Transient load regulation (single phase)
1.5 V ≤ VSW1FB ≤ 3.3 V
ISTEP = 200 mA to 1.0 A, di/dt = 2.0 A/μs
fSW = 2.5 MHz, COUT = 44 μF, LOUT = 0.47 μH
VIN = 5.0 V -3 – 3 % tPFM2PWM_SW1 PFM to PWM transition time 10 – 50 µs IQPFM_SW1 SW1 regulator quiescent current
PFM mode output not switching
Max IQ at TA = 85 °C – 15 20 µA RDS25_SW1HS High-side FET RDSON [2]
TJ = 25 °C
Including bond-wire and package resistance – 46 – mΩ RDS125_SW1HS High-side FET RDSON [2]
TJ = 125 °C
Including bond-wire and package resistance – 60 – mΩ RDS25_SW1LS Low-side FET RDSON [3]
TJ = 25 °C
Including bond-wire and package resistance – 27 – mΩ RDS125_SW1LS Low-side FET RDSON [3]
TJ = 125 °C
Including bond-wire and package resistance – 35 – mΩ RDIS_SW1 Discharge resistance
Regulator disabled and ramp completed 20 60 100 Ω VSW1IN_LS Operating input range in load switch mode – 3.3 3.5 V ILIM_LS_SW1 Load switch current limit 3.6 – 5.4 A TON_LS_SW1 Load switch turn-on time – – 2000 µs tOCP_LS_SW1 Load switch OCP deglitch time 500 – – µs

[1] UVDET represents the minimum functional level for the PF09; VSW1IN must meet the minimum headroom to ensure proper output voltage regulation. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

[2] Typical high-side FET resistance due to packaging (bondwire + metal) at room temperature is 20.5mΩ. [3] Typical low-side FET resistance due to packaging (bondwire + metal) at room temperature is 21mΩ.

Typical inductor DC resistance: < 25 mΩ
Minimum saturation current at full load: 7.0 A – 0.47 – µH COUT Effective output capacitance
2x22 μF, 6.3 V
Low equivalent series resistance (ESR) ceramic capacitor 22 44 300 µF CIN Input capacitor
4.7 μF, 10 V
Low ESR ceramic capacitor 4.23 4.7 5.17 µF

Table 125. Recommended external components. nominal load current capability. VSWx_RUN[7:0] functional bits. SWx regulator during any of the SYSTEM ON states via the VSWx_STBY[7:0] functional bits. power mode it wants to achieve at system level. Table 126. SW2 voltage setting

DVS range is between 0.65 V and 0.9 V.
The OV/UV threshold is +/-5 % or wider.
The DVS ramp must be 3.9 mV/μs or slower.

voltages are not changed by mistake during the SYSTEM ON states. the SWx_DVS[1:0] bits on the functional registers. Table 127. SWx ramp-down configuration [2] The slope rate is calculated as (6.25 [mV] * FREQ [MHz]) / (8 * clocking factor). fully discharge before a new turn-on cycle is started. the system requires a faster discharge on the SWx regulator. Table 128. Ramp-down DVS selected limits defined for a specific application. Table 129. SWx high-voltage delta PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 129. SWx high-voltage delta...continued INTB pin if the interrupt is not masked. selected limits defined for a specific application. Table 130. SW1 low-voltage delta PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 131. Mode selection in RUN Table 132. Mode selection in STANDBY The default value for the SWx_STBY_MODE[1:0] bits is loaded at power-up from the OTP_SWx_STBY_EN bit. Table 133. Default SWx mode selection in STANDBY current limit is loaded at power up from the OTP_SWx_ILIM[1:0] bits. Table 134. Current limit selection bits phase is loaded at power up from the OTP_SWx_PH[2:0] bits. Table 135. SWx phase shift selection bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 135. SWx phase shift selection bits...continued

13.2.3.1 Multiphase operation

Regulators SW2 and SW3 can be configured for dual-phase operation via the OTP_SW2CONFIG[1:0] bits.

00 Single-phase mode

01 Dual-phase mode

10 Reserved (disabled)

11 Reserved (disabled)

Table 136. SW2 and SW3 multiphase configuration bits In single-phase mode, SW2 and SW3 operate independently ofeach other. which is controlled independently for each channel via the SW2_PH[2:0] and SW3_PH[2:0] bits, respectively. single-phase mode, SW4 and SW5 operate independently of each other. Table 137. SW4 and SW5 multiphase configuration bits which is controlled independently for each channel via the SW4_PH[2:0] and SW5_PH[2:0] bits, respectively. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

13.2.3.2 Electrical characteristics

VSWxFB = 1.0 V, ISWx = 0.5 A, and TA = 25 °C, unless otherwise noted.

Minimum headroom = VSWxFB + IOUT_MAX * RON / DC.
IOUT_MAX = minimum ILIM selected for SWx.
RON includes HS FET RDSON, bond wire resistance, PCB trace resistance and inductor DCR.
Maximum duty cycle = 100 % UVDET – 5.5 V fSW Operating switching frequency 1.9 – 3.15 MHz VSWxACC3 Output voltage accuracy
PWM mode
0.3 V ≤ VSWxFB < 0.8 V -10 – 10 mV VSWxACC1 Output voltage accuracy
PWM mode
0.8 V ≤ VSWxFB ≤ 1.35 V -1.5 – 1.5 % VSWxACC2 Output voltage accuracy
PWM Mode
1.5 V ≤ VSWxFB ≤ 3.3 V -1.5 – 1.5 % VSWxPFMACC1 Output voltage accuracy
PFM mode
0.3 V ≤ VSWxFB < 0.8 V -20 – 20 mV VSWxPFMACC2 Output voltage accuracy
PFM mode
0.8 V ≤ VSWxFB ≤ 1.35 V -3 – 3 % VSWxPFMACC3 Output voltage accuracy
PFM mode
1.5 V ≤ VSWxFB ≤ 3.3 V -3 – 3 % VSWxPP Output voltage ripple
PWM mode
Peak-to-peak – 6 – mV ISWx Nominal current in single phase 2.5 – – A ISWDP Nominal current in dual phase 5 – – A ILIM1_SWx Current limit in single phase
SWx_ILIM[1:0] = 01 1.82 2.6 3.25 A ILIM2_SWx Current limit in single phase
SWx_ILIM[1:0] = 10 2.28 3 3.7 A ILIM3_SWx Current limit in single phase
SWx_ILIM[1:0] = 00 or 11 3.56 4.5 5.4 A ILIM1_SWDP Current limit in dual phase
SWx_ILIM[1:0] = 01 (primary phase) 3.64 5.2 6.5 A ILIM2_SWDP Current limit in dual phase 4.56 6 7.4 A

VSWxFB = 1.0 V, ISWx = 0.5 A, and TA = 25 °C, unless otherwise noted.

SWx_ILIM[1:0] = 10 (primary phase) ILIM3_SWDP Current limit in dual phase
SWx_ILIM[1:0] = 00 or 11 (primary phase) 7.12 9 10.8 A ILIMN_SWx Negative current limit
Per phase 1 1.5 2.3 A VSOS_SWx Startup overshoot
SWx_DVS[1:0] = 11 (15.6 mV/μs)
VSWxIN = 5.0 V , VSWxFB = 1.0 V -25 25 50 mV tONMIN_SWx Turn-on time
From enable to 90 % of end value
SWx_DVS[1:0] = 11 (15.6 mV/μs)
VSWxIN = 5.0 V, VSWxFB = 0.5 V 32 – – µs tONMAX_SWx Maximum turn-on Time
From enable to 90 % of end value
SWx_DVS[1:0] = 00 (1.95 mV/μs)
VSWxIN = 5.0 V, VSWxFB = 1.8 V – – 925 µs ηSWx_PWM_1P8 PWM efficiency at full load
Single phase
VSWxIN = 5.0 V , VSWxFB = 1.8 V
fSW = 2.5 MHz
TA = 25 °C – 86 – % ηSWx_PWM_1P8 PWM efficiency at 40 % load
Single phase
VSWxIN = 5.0 V, VSWxFB = 1.8 V
fSW = 2.5 MHz
TA = 25 °C – 90.5 – % ηSWx_PWM_1P0 PWM efficiency at full load
Single phase
VSWxIN = 5.0 V, VSWxFB = 1.0 V
fSW = 2.5 MHz
TA = 25 °C – 79 – % ηSWx_PWM_1P0 PWM efficiency at 40% load
Single phase
VSWxIN = 5.0 V, VSWxFB = 1.0 V
fSW = 2.5 MHz
TA = 25 °C – 86 – % ηSWx_PWM_0P8 PWM efficiency at full load
Single phase
VSWxIN = 5.0 V, VSWxFB = 0.8 V
fSW = 2.5 MHz
TA = 25 °C – 75 – % ηSWx_PWM_0P8 PWM efficiency at 40 % load – 83.5 – %

VSWxFB = 1.0 V, ISWx = 0.5 A, and TA = 25 °C, unless otherwise noted.

Single phase
VSWxIN = 5.0V, VSWxFB = 0.8 V
fSW = 2.5 MHz
TA = 25 °C ηSWx_PWM_0P5 PWM efficiency at full load
Single phase
VSWxIN = 5.0 V, VSWxFB = 0.5 V
fSW = 2.5 MHz
TA = 25 °C – 69 – % ηSWx_PWM_0P5 PWM efficiency at 40 % load
Single phase
VSWxIN = 5.0 V, VSWxFB = 0.5 V
fSW = 2.5 MHz
TA = 25 °C – 77 – % tDB_SWx Dead-band time – 3 5 ns tLXSR1_SWx Switching node slew time – 2.5 – ns VLOTR1_SWx Transient load regulation (single phase)
0.5 V ≤ VSWxFB ≤ 1.35 V
ISTEP = 200 mA to 1.0 A, di/dt = 2.0 A/μs
COUT = 44 μF, LOUT = 0.47 μH, fSW = 2.5 MHz
VSWxIN = 5.0 V -25 – 25 mV VLOTR2_SWx Transient load regulation (sngle phase)
1.5 V ≤ VSWxFB ≤ 3.3 V
ISTEP = 200 mA to 1.0 A, di/dt = 2.0 A/μs
COUT = 44 μF, LOUT = 0.47 μH, fSW = 2.5 MHz
VSWxIN = 5.0 V -3 – 3 % VLOTR1_SWxDP Transient load regulation (dual phase)
0.5V ≤ VSWxFB ≤ 1.35 V
ISTEP = 400 mA to 2.0A, di/dt = 4.0 A/μs
COUT = 44 μF (per phase)
LOUT = 0.47 μH
fSW = 2.5 MHz
VSWxIN = 5.0 V -25 – 25 mV VLOTR2_SWxDP Transient load regulation (dual phase)
1.5 V ≤ VSWxFB ≤ 3.3 V
ISTEP = 200 mA to 2.0 A, di/dt = 4.0 A/μs
COUT = 44 μF (per phase)
LOUT = 0.47 μH
fSW = 2.5 MHz
VSWxIN = 5.0V -3 – 3 % IQPFM_SWx PFM quiescent current
PFM mode (not switching)
Max IQ at TA = 85 °C – 15 20 µA

VSWxFB = 1.0 V, ISWx = 0.5 A, and TA = 25 °C, unless otherwise noted.

TJ = 25°C
Including bond-wire and package resistance – 60 – mΩ RDS125_SWxHS High-side FET RDSON [2]
TJ = 125°C
Including bond-wire and package resistance – 75 – mΩ RDS25_SWxLS Low-side FET RDSON [3]
TJ = 25°C
Including bond-wire and package resistance – 32 – mΩ RDS125_SWxLS Low-side FET RDSON [3]
TJ = 125°C
Including bond-wire and package resistance – 42 – mΩ RDIS_SWx Discharge-resistance
Regulator disabled and ramp completed 20 60 100 Ω

[1] UVDET represents the minimum functional level for the PF09; VSW1IN must meet the minimum headroom to ensure proper output voltage regulation. [2] Typical high-side FET resistance due to packaging (bondwire + metal) at room temp is 24 mΩ. [3] Typical low-side FET resistance due to packaging (bondwire + metal) at room temp is 21 mΩ.

Nominal inductor DC resistance < 24 mΩ
Minimum saturation current at full load: 5.5 A – 0.47 – µH COUT Effective output capacitance
x 22 μF, 6.3 V
Low ESR ceramic capacitor. 22 44 300 µF CIN Input capacitor
4.7 μF, 10 V
Low ESR ceramic capacitor 4.23 4.7 5.17 µF

Table 139. SWx recommended external components.

13.2.4 LDO1 (500 mA linear regulator with load switch mode)

V. It provides programmable output voltage between 0.75 V and 3.3 V, with up to 2 % output voltage accuracy. mechanism during power down (disable). PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

1 Enable

Table 140. LDO1 output control in RUN default value is loaded from the OTP_LDO1_STBY_EN bit at power up. Table 141. LDO1 output control in STANDBY Table 142. LDO1 output voltage selection bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 142. LDO1 output voltage selection bits...continued level. The ramp-up time is selected in OTP via the OTP_LDO1_SS bit.

0 Slow ramp

1 Fast ramp

Table 143. LDO1 soft-start selection bit

13.2.4.1 Load switch mode

0 LDO mode

Table 144. LDO1 load switch selection mode Power-up sequence, or enabling the output manually via the LDO1_RUN_EN and LDO1_STBY_EN bits. level, to account for DC losses in the pass FET. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

13.2.4.2 Electrical characteristics

VLDO1 = 3.3 V, ILDO1 = 500 mA, TA = 25 °C, unless otherwise noted.

0.75 V ≤ VLDO1 ≤ 1.3 V 1.8 – 5.5 V VLDO1IN Operating input voltage range
1.35 V ≤ VLDO1 < 3.3 V 2.5 – 5.5 V VHDR_LDO1 Minimum input headroom 300 – – mV VACC_LDO1 Output voltage accuracy VACC_LDO1 Output voltage accuracy
1.35 V ≤ VLDO1 ≤ 3.3 V -2 – 2 % VLOR_LDO1 Load regulation – 0.1 0.2 mV/mA VLIR_LDO1 Line regulation – – 20 mV ILDO1 LDO1 nominal current 500 – – mA ILIM_LDO1 Current limit 550 – 900 mA IQ_LDO1 Quiescent current – 10 20 µA RDSON_LDO1 Drop-out/load switch resistance. RDSON does not include the bonding wire and package resistance. @VLDOx = 3.3 V, ILDOx = 500 mA See Figure 25. – 150 250 mΩ RDSON_LDO1 Drop-out/load switch resistance. RDSON including the bonding wire and package resistance. VLDOx = 3.3 V, ILDOx = 500 mA. See Figure 25. – – 300 mΩ LDO1PSRR_DC DC power supply rejection ratio
100 µA < ILDO1 ≤ 500 mA
VLDO1IN = VLDO1 + 300 mV 50 – – dB LDO1PSRR_AC AC power supply rejection ratio
400 kHz
100 µA < ILDO1 ≤ 500 mA
VLDO1IN = VLDO1 + 300 mV 20 – – dB tSS0_LDO1 LDO1 soft-start time
From 10 % to 90 % of target voltage.
OTP_LDO1_SS = 0 320 – 520 µs tSS1_LDO1 LDO1 soft-start time
From 10 % to 90 % of target voltage.
OTP_LDO1_SS = 1 140 – 270 µs tEN_LDO1 LDO1 enable time
From enable signal to 10 % of target voltage.
VLDO1 = 3.3 V – – 125 µs

VLDO1 = 3.3 V, ILDO1 = 500 mA, TA = 25 °C, unless otherwise noted.

Output disabled to 10 % of initial value
VLDO1 = 3.3 V
ILDO1 = 0.0 mA
COUT = 2.2 μF – 650 – µs VOS_LDO1 Startup overshoot – – 2 % VLOTR_LDO1 Load transient response
ILDO1 = 200 mA step in 2.0 μs -2 – -2 % tON_LS1 Load switch turn-on rise time – 150 300 µs ILIM_LS1 Load switch mode current limit 550 – 900 mA RPD_LDO1 Output discharge resistor – 60 100 Ω RTBB_LDO1 LDO DEBUG pulldown resistance – used to detect pin lift or pin disconnection
VDDOTP > 3.0 V and in DBGOFF state 1 2 – kΩ

Table 145. LDO1 electrical characteristics...continued Figure 25. RDSON vs. VLDOUT for LDO1

4.7 μF, 6.3 V (+/- 50 % variation)
X7R low ESR ceramic capacitor. 2.3 4.7 7 µF CIN Input capacitor
1 μF, 10 V
X7R Low ESR ceramic capacitor 0.5 1 2 µF

13.2.5 LDO2 / LDO3 (200 mA linear regulators with load switch mode)

mechanism during power down (disable). Table 147. LDOx output control in RUN default value is loaded from the OTP_LDOx_STBY_EN at power-up. Table 148. LDOx output control in STANDBY RUN and STANDBY states respectively. bits (OTP_VLDOx_RUN[4:0] and OTP_VLDOx_STBY[4:0] ) at power up. Table 149. LDOx output voltage selection bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 149. LDOx output voltage selection bits...continued level. The ramp-up time is selected in OTP via the OTP_LDOx_SS bit. Table 150. LDOx soft-start selection bit operation is selected on OTP via the OTP_LDOx_MODE[1:0] bits.

00 LDO mode

01 LDO bypass mode

10 Load switch mode

11 External VMON mode

13.2.5.1 Load switch mode

LDOx_STBY_EN and LDOx_SEQ[7:0] bits. Power-up sequence or manually via the LDOx_RUN_EN and LDOx_STBY_EN bits. proper level to account for DC losses in the pass FET.

13.2.5.2 External VMON mode

13.2.5.3 LDO bypass mode

disable the external regulators to minimize power consumption during the low-power operation. Figure 26. System connection in LDO bypass mode monitoring voltage level to be expected at the LDOxOUT pin. settle before allowing OV and UV protection. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 152. VLDOxMON blanking time configuration bits in the Power-up or RUN state, where the LDOx block is operating as a voltage monitor for an external supply. Operation for a detailed description of the VMON operation on the LDOx block. monitoring while the output voltage transitions to the new expected level. Table 153. VLDOxMON masking timer LDOx output will be turned on in the corresponding time slot as set by the VLODx_SEQ[7:0] bits. depend on whether the PF09 is in the monitored STANDBY or the low power STANDBY states. Monitored STANDBY mode (OTP_LP_STBY = 0): in this mode, the LDO output will be monitored internally. ensure the LDO output is discharged properly and no false OV/UV condition is flagged. over current consumption during the STANDBY mode. between the voltage regulators. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

two possible scenarios when the LDOx is operating in bypass mode. Scenario #1: the output voltage in RUN and STANDBY is constant; no voltage scaling is required. Figure 27. LDOx Bypass mode RUN to STANDBY transition without voltage scaling PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 28. LDOx Bypass mode RUN to STANDBY transition with voltage scaling

13.2.5.4 Electrical characteristics

VLDOx = 3.3 V, ILDOx = 200 mA, TA = 25 °C, unless otherwise noted.

0.65 V ≤ VLDOx ≤ 1.3 V 1.8 – 5.5 V VLDOxIN Operating input voltage range
1.35 V ≤ VLDOx < 3.3 V 2.5 – 5.5 V VHDR_LDOx Minimum input headroom
Valid from 2.5 V ≤ VLDOx < 3.3 V 250 – – mV VACC_LDOx Output voltage accuracy VACC_LDOx Output voltage accuracy
1.35 V ≤ VLDOx < 3.3 V -2 – 2 % VLOR_LDOx Load regulation – 0.1 0.2 mV/mA VLIR_LDOx Line regulation – – 20 mV/mA ILDOx LDOx nominal current 200 – – mA ILIM_LDOx Current limit 250 – 450 mA IQ_LDOx LDOx quiescent current – 10 20 µA

VLDOx = 3.3 V, ILDOx = 200 mA, TA = 25 °C, unless otherwise noted. RDSON does not include the bonding wire and package resistance. RDSON including the bonding wire and package resistance.

100 µA < ILDOx ≤ 200 mA
VLDOxIN = VLDOx + 300 mV 55 – – dB LDOxPSRR_AC AC power supply rejection ratio
400 kHz
100 µA < ILDOx ≤ 200 mA
VLDOxIN = VLDOx + 300 mV 20 – – dB tSS0_LDOx LDOx soft-start time
From 10 % to 90 % of target voltage
OTP_LDOx_SS = 0 320 – 520 µs tSS1_LDOx LDOx soft-start time
From 10 % to 90 % of target voltage.
OTP_LDOx_SS = 1 140 – 270 µs tEN_LDOx LDOx Enable time
From enable signal to 10% of target voltage.
VLDOx = 3.3 V – – 100 µs tOFF_LDOx Turn-off time
Output disabled to 10 % of initial value
VLDOx = 3.3 V
ILDOx = 0.0 mA
COUT = 2.2 μF – 600 – µs VOS_LDOx Startup overshoot – – 2 % VLOTR_LDOx Load transient response
ILDOx = 10 mA to 200 mA in 2.0 μs -2 – 2 % tON_LSx Load switch turn-on rise time – 150 300 µs ILIM_LSx Load switch current limit 200 250 450 mA RPD_LDOx Output discharge resistor – used to discharge the output capacitance to help LDOs reach the OV level faster – 60 100 Ω RPD_DBG LDOx DEBUG pulldown resistance - used for pin disconnection detection
VDDOTP > 3.0 V and in DBGOFF State 1 2 – kΩ

Figure 29. RDSON vs. VLDOUT for LDO2/LDO3

4.7 μF, 6.3 V (+/-50 % variation)
X7R low ESR ceramic capacitor. 2.2 4.7 7 µF CIN Input capacitor
1 μF, 10 V
X7R ow ESR ceramic capacitor 0.5 1 2 µF

Table 155. Recommended external components.

13.3 Voltage monitoring

13.3.1 System-on monitoring

handling undervoltage and overvoltage conditions in their corresponding outputs. independence between the voltage generation and the voltage monitoring circuits. achieve the lowest quiescent current during this mode. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 156. SWx UV threshold configuration bits...continued Table 157. SWx OV threshold configuration bits output voltage accuracy on the SWx regulators due to the PFM operation.

0 Same as RUN state

1 Open to maximum threshold

Table 158. SWx UV threshold configuration bits during STANDBY Table 159. SWx OV threshold configuration bits during STANDBY modify their values before requesting access to the STANDBY states. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 160. LDOx UV threshold configuration bits Table 161. LDOx OV threshold configuration bits The UV and OV thresholds represent percentages of the nominal voltage programmed on each regulator. overvoltage condition above the selected OV threshold will always be detected by the VMON circuit. voltage accuracy and the monitoring threshold accuracy specifications. Table 162. Hysteresis on 2.5 % OV/UV threshold configuration bits larger OV/UV debounce times to minimize multiple fault detection due to oscillating borderline conditions. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

during safe system operation. Table 163. OV debounce time configuration bits during safe system operation. Table 164. UV debounce time configuration bits

13.3.1.1 VMON during SW1 load switch operation

provide adequate OV/UV thresholds to account for the voltage drop due to DC losses in the pass FET. OTP_SW1_OVTH[2:0] and OTP_SW1_UVTH[2:0] bits.

13.3.1.2 VMON during LDOx load switch operation

voltage drop due to the current going through the LDOxLS pass FET. provide adequate OV/UV thresholds to account for the voltage drop due to DC losses in the pass FET. OTP_LDOx_OVTH[2:0] and OTP_LDOx_UVTH[2:0] bits. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

13.3.2 VAON monitoring

STANDBY states supported by the programmable voltage monitoring circuit with independent reference supply. undervoltage monitor as described in section 16.6.3 VAON Fault Management. like all the other regulators. Figure 32. VAON voltage monitoring architecture Table 165. VAON UV threshold configuration bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 166. VAON OV threshold configuration bits

13.3.2.1 VAON as always-on regulator

DBGOFF state to ensure the VAON is within regulation before the PF09 can start the Power-up sequence. reaction will be performed as described in section 16.6.3 VAON Fault Management.

13.3.2.2 VAON as system regulator

UV fault conditions based on the VAONMON configuration shown above.

13.3.3 External voltage monitoring

references, to allow seamless monitoring of an external supply with dynamic voltage scaling (DVS) capability.

13.3.3.1 VMON1 / VMON2

safety controller to detect and notify when an OV/UV condition is present in the external voltage supplies. Table 167. VMONx UV threshold configuration bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 167. VMONx UV threshold configuration bits...continued Table 168. VMONx OV threshold configuration bits AC output voltage accuracy on the voltage regulator being monitored by the VMONx block. Table 169. VMONx UV threshold selection in STANDBY Table 170. VMONx OV threshold selection in STANDBY can modify their values before requesting access to the STANDBY states. overvoltage condition above the selected OV threshold will always be detected by the VMON circuit. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 171. VMONx monitoring voltage configuration bits...continued MCU must manage the voltage transitions in a safe way at the system level. masking timer to prevent OV/UV conditions from happening during the external voltage transition. masking timer is set in OTP registers via the OTP_VMONx_TMASK[1:0] bits. Table 172. VMONx masking timer configuration bits consideration when selecting the masking time for the VMONx. voltage reference set in the VMONx_RUN[4:0] and VMONx_STBY[4:0] bits. Figure 33. External VMON resistor divider calculation overall monitoring accuracy fallouts. manually via the VMONx_EN bit after the external supply has been enabled and is ready to be monitored. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 173. VMONx enable bit detect faults. The default blanking timer is set on OTP via the OTP_VMONx_TSET[1:0] bits. Table 174. VMONx settling time configuration bits

13.3.3.2 LDO2 / LDO3 external VMON operation

Table 175. LDOx control bits in VMON mode Table 176. VLDOxMON monitoring voltage configuration bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 176. VLDOxMON monitoring voltage configuration bits...continued MCU must manage the voltage transitions in a safe way at system level. masking timer to prevent OV/UV conditions from happening during the external voltage transition. value for the masking timer is set in OTP registers via the OTP_VLDOxMON_TMASK[1:0] bits. Table 177. VLDOxMON masking timer configuration bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

consideration when selecting the masking time for the VLDOxMON. resulting voltage matches the VREF = 0.5 V. Figure 34. External VLDOxMON resistor divider calculation accuracy should be rated 1 % or better to minimize overall monitoring accuracy fallouts. LDOxSTBY_EN bit will control the monitoring block during the Monitored STANDBY states. Table 178. VLDOxMON enable bit OTP_VLDOxMON_TSET[1:0] bit is used to set the settling period after enabling the VLDOxMON block. Table 179. VLDOxMON settling time configuration bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

13.3.4 Electrical characteristics

otherwise noted. MONx applies to all internal voltage monitors: VSWxMON, VLDOxMON, VMONx and VAONMON.

voltage difference between UV rising and falling thresholds 0.5 – 1 % VUVACC_MONx UV threshold accuracy for Vref ≥ 0.75 V -1 – 1 % VUVACC_MONx UV threshold accuracy for Vref < 0.75 V -1.5 – -1.5 % tUVDBN0_MONx UV debounce time
UV_DBNC[1:0] = 00 2.5 5 7.5 µs tUVDBN1_MONx UV debounce time
UV_DBNC[1:0] = 01 10 15 20 µs tUVDBN2_MONx UV debounce time
UV_DBNC[1:0] = 10 20 30 40 µs tUVDBN3_MONx UV debounce time
UV_DBNC[1:0] = 11 25 40 55 µs VOVACC_MONx OV threshold accuracy for Vref ≥ 0.75 V -1 – 1 % VOVACC_MONx OV threshold accuracy for Vref < 0.75 V -1.5 – -1.5 % VOVHYS_MONx OV hysteresis
voltage difference between OV rising and falling thresholds 0.5 – 1 % tOVDBN0_MONx OV debounce time
OV_DBNC[1:0] = 00 15 25 35 µs tOVDBN1_MONx OV debounce time
OV_DBNC[1:0] = 01 35 50 65 µs tOVDBN2_MONx OV debounce time
OV_DBNC[1:0] = 10 55 80 105 µs tOVDBN3_MONx OV debounce time
OV_DBNC[1:0] = 11 90 125 160 µs IQ_VAONMON VAONMON quiescent current – 7 10 µA tON_VAONMON VAONMON settling time after enabled – – 30 µs VUVHYS_ VAONMON VAONMON UV hysteresis
Voltage difference between UV rising and falling thresholds 1 – 2 % VUVACC_ VAONMON VAONMON UV threshold accuracy -2 – 2 % tUVDBN0_ VAONMON VAONMON UV debounce
UV_DBNC[1:0] = 00 2.5 5 7.5 µs tUVDBN1_ VAONMON VAONMON UV debounce
UV_DBNC[1:0] = 01 10 15 20 µs

otherwise noted. MONx applies to all internal voltage monitors: VSWxMON, VLDOxMON, VMONx and VAONMON.

UV_DBNC[1:0] = 10 15 25 35 µs tUVDBN3_ VAONMON VAONMON UV debounce
UV_DBNC[1:0] = 11 25 40 55 µs VOVACC_ VAONMON VAONMON OV threshold accuracy -2 – 2 % VOVHYS_ VAONMON VAONMON OV hysteresis
Voltage difference between OV rising and falling thresholds 1 – 2 % tOVDBN0_ VAONMON VAONMON OV debounce
OV_DBNC[1:0] = 00 20 30 40 µs tOVDBN1_ VAONMON VAONMON OV debounce
OV_DBNC[1:0] = 01 35 50 65 µs tOVDBN2_ VAONMON VAONMON OV debounce
OV_DBNC[1:0] = 10 55 80 105 µs tOVDBN3_ VAONMON VAONMON OV debounce
OV_DBNC[1:0] = 11 90 125 160 µs

Table 180. Voltage monitor electrical characteristics...continued

13.4 Clock management

digital clock management interface supporting all the interaction among them.

Low-power 100 kHz oscillator
Internal high-frequency oscillator with programmable frequency
Clock watchdog monitor
Phase-locked loop (PLL)

13.4.1 High-frequency clock

states to achieve minimum power consumption in these states.

13.4.1.1 Manual frequency tuning

Table 181. Manual frequency tuning The default operating frequency is set in the OTP registers via the OTP_CLK_FREQ[3:0] bits. frequency-ready interrupt will assert the INTB pin when the interrupt is not masked.

13.4.1.2 Spread spectrum

the internal frequency clock, and it will be disabled when the external clock synchronization is enabled. the MCU can enable or disable the spread spectrum during the SYSTEM ON states using the FSS_EN bit. Table 182. Frequency spread spectrum enable bit Table 183. Frequency spread spectrum center frequency selection bits PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 183. Frequency spread spectrum center frequency selection bits...continued performed within the clock frequency limits. spread spectrum is set in the OTP registers via the OTP_FSS_MODE bit.

0 Triangular modulation

1 Pseudo-random Modulation

Table 184. Spread-spectrum mode selection bit Figure 35. Triangular modulation through three randomly generated frequency steps between each base point transition. frequency base point, causing an aleatory modulation. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 36. Pseudo-random modulation

13.4.2 Clock synchronization

devices. The pin is suitable for 1.8 V or 3.3 V level signals. changed during the system operation.

0 SYNCOUT mode

1 SYNCIN Mode

Table 185. FSYNC mode selection bit

13.4.2.1 SYNCOUT mode

frequency clock to generate the switching frequency for the switching regulators. output frequency is disabled, and the MCU must enable it during the configuration phase. Table 186. Enabling FSYNC output frequency enable bit

13.4.2.2 SYNCIN mode

the system is expected to operate the switching regulators in PWM mode to ensure clock synchronization. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

seamless transition to the internal clock, in the event a bad external frequency failure is present. until the external clock is applied. The FSYNC pin accepts frequencies in two selectable ranges as defined by the FSYNC_RANGE bit. Table 187. FSYNC input frequency range selection bit switching frequency from the valid external frequency. INTB pin if it is not masked. frequency on the SYNC pin, and it will clear to 0 when the external frequency is back within the valid range. cleared and the frequency watchdog is detecting a valid input frequency.

13.4.2.3 Electrical characteristics

and TA = 25 °C unless otherwise noted.

Minimum voltage at 2 mA load VDDO-0.5 – – V IOH_FSYNC FSYNC output high current – – 2 mA VOL_FSYNC FSYNC output low voltage
Maximum voltage at 10 mA load – – 0.4 V IOL_FSYNC FSYNC output low current – – 2 mA FOUT_FSYNC FSYNC output frequency 1.9 – 3.1 MHz tPDLY_FSYNC FSYNC propagation delay – – 35 ns VIH_FSYNC FSYNC Input high voltage
Minimum voltage to ensure a HIGH state 0.7*VDDIO – – V VIL_FSYNCOUT FSYNC Input low voltage
Maximum voltage to ensure a LOW state – – 0.4 V IHYS_FSYNCOUT FSYNC Input buffer hysteresis 100 – 400 mV IIN_LEAK_FSYNC FSYNC input leakage
Pin shorted to 5.5 V – – 1 μA

and TA = 25 °C unless otherwise noted.

FSYNC_RANGE = 1 333 – 475 kHz FIN_HF_FSYNC FSYNC high frequency input range
FSYNC_RANGE = 0 2.1 – 2.8 MHz DIN_FSYNC FSYNC input duty cycle range 40 – 60 %

Table 188. FSYNC electrical characteristics...continued

13.5 Analog multiplexer

always within 1.65 V, making it suitable for 3.3 V or 1.8 V ADC inputs. The AMUX_EN bit is provided to enable or disable the AMUX block.

0 AMUX disabled, pulled to ground

Table 189. AMUX enable bit The AMUX output is selected with the AMUX_SEL[4:0] bits. Table 190. AMUX channel selection PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 190. AMUX channel selection...continued multiple devices to connect to the same ADC input and drive the AMUX line one device at a time.

13.5.1 Electrical characteristics

and TA = 25 °C unless otherwise noted.

Max step size of 1.6 V
Bus capacitance 150 pF – – 50 µs tAMUX_CHG AMUX settling time (channel-to-channel Transition) – – 50 µs

and TA = 25 °C unless otherwise noted.

Max step size of 1.6 V
Bus capacitance 150 pF VCLAMP AMUX clamping voltage 1.8 – 2.5 V VDIV4V0 Input divider ratio by 4 tolerance 3.95 4 4.05 – VDIV2V5 Input divider ratio by 2.5 tolerance 2.48 2.5 2.52 – VDIV1V0 Input divider ratio by 1 tolerance 0.995 1 1.005 –

Table 191. AMUX electrical characteristics...continued

13.6 Thermal monitors

Center of die
Vicinity of SW1
Vicinity of SW2
Vicinity of SW3
Vicinity of SW4
Vicinity of SW5
Vicinity of LDO1
Vicinity of LDO2
Vicinity of LDO3 The output of the temperature sensors is internally connected to the AMUX, allowing the user to read the raw voltage equivalent to the temperature on each sensor. Sensor temperature at any point is calculated with the following formula: Where VTSENSE is the thermal sensor voltage measured on the corresponding AMUX channel. The temperature sensor at the center of the die is used to generate thermal interrupts and thermal shutdown. The processor can read outputs of the other temperature sensors and take appropriate action (such as reducing loading, or turning off a regulator) if the temperature exceeds desired limits at any point in the die. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Figure 37. Thermal monitoring architecture utilization without sacrificing thermal monitoring availability. Table 192. Thermal thresholds notification bits edge, and it will assert the INTB pin as long as the corresponding interrupt is not masked. temperature (either by turning off external regulators, reducing load, or turning on a fan). temperature has decreased below the TSD with a 10 °C hysteresis. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

13.6.1 Electrical characteristics

and TA = 25 °C unless otherwise noted.

Applies to devices with 165 °C thermal shutdown 155 165 175 ºC TSD_175C Thermal shutdown threshold
Applies to devices with 175 °C thermal shutdown 165 175 185 ºC TWARN_HYS Thermal threshold hysteresis – 5 – ºC TSD_HYS Thermal shutdown hysteresis – 10 – ºC tTMP_DBNC Debounce timer for temperature thresholds (on both rising and falling temperatures) – 10 – µs tS_INTERVAL Sampling interval time – 3 – ms tS_WINDOW Sampling window – 450 – µs

14 Functional safety

functional safety features to reach an automotive safety integrity level up to ASIL D and industrial SIL 2.

Output voltage monitoring with dedicated bandgap reference
Bandgap monitoring
Protected I2C protocol with CRC verification.
Hash fault monitoring (dynamic CRC)
System watchdog management
Dedicated Fail-safe output (FS0B)
System interface safety outputs (RSTB, PGOOD, INTB)
External fault detection inputs (FCCU, ERRMON)
Power-up analog self-test + ABIST on demand
Power-up logic built-in self-test + LBIST on demand
Fully isolated digital machine supervisor Main digital controller aaa-056080 Clock monitoring VIN_OV monitor OV monitoring ABIST BG MON Monitoring BG Analog supply Digital supply Clock management Regulator BG Safety outputsAMUX Thermal monitoring FCCU mon ERRMON XRESET FCCU1/2 MCU I2C comm. MCU ADC Input supply CRC + secure write LBIST System checks Dynamic CRC OTP CRC ABIST WD monitoring Digital machine supervisor SHS DMS digital supply Input supply FS0B RSTB PGOOD REG OUT OV/UV monitoring External VMON Voltage generation I2C comm. Non-safety functions Functional safety Supply

Nine-channel power management IC with advanced system safety monitoring

14.1 Output voltage monitoring

The PF09 is intended to operate as the main safety controller for the full power management architecture, providing high precision OV/UV monitoring during the RUN and Monitored STANDBY states for the PF09 system regulators, as well as external regulators supplied by one or more companion PMICs. The OV/UV monitoring circuits implement a dedicated bandgap reference which is fully independent from the bandgap reference used for the voltage generation. Safety OV/UV monitoring is performed on the following regulators:

Switch mode power supplies (SMPS): SW1, SW2, SW3, SW4, SW5
Linear regulators (LDO): LDO1, LDO2, LDO3, VAON External voltage monitoring is performed via the two dedicated external VMON pins.
VMON1
VMON2 Additional external voltage monitoring pins are available in the LDO2 and LDO3 if the regulators are not required in the system.
VLDO2MON (LDO2OUT pin)
VLDO3MON (LDO3OUT pin) Refer to section 17.3 Voltage Monitoring for operational details of the safety-related VMON blocks. Voltage monitoring of the VAON regulator in the Low-power modes (OFF and STANDBY states) is not considered to be a safety-related mechanism, therefore the undervoltage detection in such scenarios is designed to prioritize power consumption over physical independence of the voltage reference between the regulator and the voltage monitor.

14.1.1 Voltage monitoring during a pin disconnection

The switching regulators and LDOs are provided with a pin-lift mechanism to detect a random pin disconnection that could potentially lead to an unsafe/undetectable condition, resulting in a violation of the safety goal. When the VAON operates as an always-on regulator with very low quiescent current, this rail is intended to supply the low-level voltage domain in the MCU in charge of communicating and interfacing with the PF09 device. It is assumed a pin disconnection in the VAON output will cause the MCU to become unresponsive, and such a fault will be detected by other mechanisms, therefore a pin-lift feature is not needed in the VAON.

14.1.1.1 Switching regulators FB disconnection

Each switching regulator is provided with an internal weak pullup resistor to VIN at its respective SWxFB pad, to ensure the VMON is able to perform a safe reaction when the regulation is operating in PWM mode. A pullup on the FB node will force the VMON into to an OV condition, while the error amplifier will try to lower the output voltage by reducing the PWM, resulting in an incorrect OV fault detection but safe reaction to an FB pin disconnection. It is assumed the PFM mode is intended to be used during low-power STANDBY mode, which is considered a safe state with no critical activity. In these scenarios, the internal pullup resistor will be disabled in the PFM mode to ensure proper operation of the PFM control loop.

14.1.1.2 LDO regulators output disconnection

The LDOs are provided with an internal mechanism to detect a real-time pin disconnection during normal operation. A current source injects small amounts of current with a frequency wide enough to cause a pin PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

14.2 Bandgap monitoring

the device will start a protective mechanism. monitor will result in a failing self test, preventing a power-on event with an erroneous bandgap. interrupt, which in turn can assert the INTB pin if the interrupt is not masked. The BGMON_S bit is provided to read the real-time status of the bandgap monitor.

0 No BG fault

1 BG fault detected

Table 194. Bandgap monitor status bit Digital Machine Supervisor for detailed description and configurability of the DMS block.

14.3 Clock monitoring

between the internal system clocks. power-on event with an erroneous clock leading to a potential single-point failure. assert the FS0B pin and set a CLKMON_I flag , which in turn can assert the INTB if the interrupt is not masked. Machine Supervisor for detailed description and configurability of the DMS block.

14.4 Watchdog management

manually during the RUN and the monitored STANDBY state by writing the WD_EN bit on the I2C register map. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

0 WD disabled

1 WD enabled

Table 195. System watchdog enable bit The system watchdog is not available in the Low-power STANDBY or SYSTEM OFF states. The PF09 family of devices supports two different modes of operation for the watchdog monitoring interface. The mode of operation depends on the target safety integrity level supported by each specific device version. for timing, stuck-at and I2C data write conditions in the MCU. to ensure coverage for timing, stuck-at conditions, I2C read/write and data computing condition in the MCU.

14.4.1 Static WD

however a soft reset will not reset the WD seed. the PMIC watchdog, but the MCU can modify this value if it decides to use a different key for security purposes.

14.4.2 Dynamic WD

Seed readback method: the MCU must read the current seed from the WD_SEED[7:0] bits, and use the

value read to calculate the response key to service the current WD cycle.

Seed calculation method: the MCU will synchronize its starting seed with the PMIC during the booting

always read the current seed, or re-set the seed via I2C, to regain synchronization with the PMIC. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 39. Dynamic watchdog polynomial

14.4.3 Servicing the watchdog timer

enabled, whereas the seed remains stable in the static WD mode.

The response is calculated as the bitwise NOT of the WD_SEED[7:0] bits.
The response must be provided within an open window. Providing a valid key into the WD_CLEAR[7:0] register will generate a WD_OK event. When the MCU fails to clear the system watchdog (invalid response or WD duration expired), the device will generate a WD_NOK event, set the WD_ERROR_I flag, and the INTB will be asserted, as long as the interrupt is not masked The watchdog timer will be reset after either a WD_OK or a WD_NOK event, to start a new service window. The WD_DURATION[3:0] bits are used to set the duration of the watchdog timer to service the watchdog. The WD timer will expire when it reaches the value set on the WD_DURATION[3:0] while WD refresh is present. WD_DURATION[3:0] Watchdog timer duration 0000 1 ms 0001 2 ms 0010 4 ms 0011 8 ms 0100 16 ms 0101 32 ms 0110 64 ms 0111 128 ms 1000 256 ms 1001 512 ms 1010 1024 ms

Table 196. System watchdog timer configuration bits...continued At power up, the WD timer will start counting only after the RSTB pin is released in the Power-up sequence. The default value of the WD_DURATION[3:0] bits is set on OTP by the OTP_WD_DURATION[3:0] bits. the system is properly synchronized with the MCU. The OTP_WD_WINDOW[1:0] bits are provided to select the close/open ratio to service the system watchdog. Table 197. System watchdog window configuration bits the WD within the watchdog duration, will be interpreted as a bad watchdog refresh.

An invalid response will increase the WD_NOK_CNT[2:0] by 2
A valid response will decrease the WD_NOK_CNT[2:0] by 1 If WD_NOK_CNT[2:0] = WD_NOK_MAX[2:0], the device will generate a hard reset event and the RESET_CNT[3:0] bits will be increased by 1. Refer to section 16.4.2 Reset Conditions, for a detailed description of the reset behavior. The initial value for the WD_NOK_MAX[2:0] is set in the OTP by the OTP_WD_NOK_MAX[2:0] bits. The WD_NOK_CNT counter uses a 2-by-1 count strategy to ensure the system is not caught in a software loop that is able to service one good WD per each bad WD within the loop.
An invalid response will increase the WD_NOK_CNT[2:0] by 2
A valid response will decrease the WD_NOK_CNT[2:0] by 1 Due to the 2-by-1 design of the watchdog counter, when the WD_NOK_MAX[2:0] is set to 0x01 or 0x02, a WD reset event will be initiated as soon as the first bad WD refresh occurs. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Figure 40. System watchdog operation refresh, however, there will be no maximum count, hence no WD reset is possible. counter increases by 1 every time a good refresh is present, but it will clear to 0 when a bad refresh occurs. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 41. WD_OK counter events to reduce the fault and reset counters by 1. fault counters within the software loop.

000 Good WD cannot clear faults

001 Every one WD refresh OK

010 Every two WD refresh OK

011 Every three WD refresh OK

100 Every four WD refresh OK

101 Every five WD refresh OK

110 Every six WD refresh OK

111 Every seven WD refresh OK

Nine-channel power management IC with advanced system safety monitoring When the WD counter is disabled or the WD_OK_FCD[2:0] bits are set to 0b000, the WD_OK_CTN[2:0] bits will have no effect on the FAULT_CNT[3:0] or RESET_CNT[3:0] counters. In this case, the system must implement a routine to clear the system counters manually, to avoid a turnoff event due to compounded random faults.

14.5 FS0B active safe-state mode

In devices targeting a high safety integrity level, the FS0B is used as a dedicated safety output operating in Active Safe-state mode. In this mode, the PF09 implements several mechanisms to ensure the FS0B is able to assert LOW, to indicate the PMIC is in a safe state. The PF09 assumes the following safe states:

PMIC in RUN state with FS0B pin asserted
PMIC in STANDBY state with FS0B pin asserted
PMIC in OFF states with RSTB and FS0B asserted
PMIC in Deep Fail-safe state with RSTB and FS0B asserted
System reset (WD or XRESET event with RSTB and FS0B asserted)
Unresponsive main digital control unit with FS0B and RSTB asserted During the RUN states, the FS0B remains asserted low until the MCU requests an FS0B release command via I2C. In the STANDBY states, the FS0B is always asserted LOW. To request an FS0B release command, the MCU must write the code 0xA5 into the FS0B_RELEASE [7:0] bits. Any other value on the FS0B_RELEASE[7:0] bits will be ignored. The FS0B will be allowed to release only after all conditions flagging a potential safety-related fault are acknowledged and cleared when the FS0B release command is requested:
Power-up sequence has been finished
RSTB is released. ( device is in the SYSTEM ON states)
All ABIST flags are 0 (ABIST OK)
The LBIST_STATUS[1:0] = 11 (LBIST Passed)1
The FAULT_CNT[3:0] = 0x00
The DCRC_FLG = 0
The DFS_FLG = 0
The VIN_OV_FLG = 0
The XFAIL_FLG = 0
The WD_FLG = 0
The XRESET_FLG = 0
The SFAULT_FLG = 0
The HFAULT_FLG = 0
The BGMON_I = 0 (no Bandgap drift detected)
The CLKMON_I = 0 (no clock drift detected)
The SHS_I = 0 (no safety handshake fault detected)1
No Short condition is detected on PGOOD and FS0B outputs Once the FS0B pin is released, the pin will assert LOW if one or more safety-related fault conditions occur:
The MCU writes a 0x4B code into the FS0B_RELEASE[7:0] bits
The RSTB pin is asserted LOW (internally or externally)
An OV condition in the VDIG or VANA supplies
A hard fault starts a power-down sequence 1 Conditions are evaluated only on devices featuring functions such as LBIST, DMS, or safety handshake. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

The device is powered down into any of the OFF states
The device moves into the DFS state
The XFAILB pin is asserted externally
A dynamic CRC (DCRC) fault is present
A VIN_OV condition is present
An XRESET event is present
An OV/UV/ILIM condition is present and the fault is not bypassed
An FCCU failure is detected
An ERRMON failure is detected
The BGMON detects a bandgap drift condition
The CLKMN detects a clock drift condition
A short condition is detected on PGOOD or FS0B outputs During the RUN states, every time the FS0B pin is asserted the MCU must perform the necessary diagnostic to clear all fault conditions and request an FS0B release command, to release the pin and resume normal operation.

14.5.1 FS0B pin diagnostic bit

The FS0B_S bit provides the real-time state of the FS0B pin.

0 Pin sensed LOW

1 Pin sensed HIGH

Table 199. FS0B status bit FS0B pin. The FS0B fault event will assert the INTB pin if the FS0B_FLT_I interrupt is not masked. sense bits FS0B_S2H (short to high) and FS0B_S2L (short to low). bit is set HIGH until the condition is no longer present. set HIGH until the condition is no longer present. sticky bits, and their values will remain after the event is over.

14.5.2 Redundant FS0B control

assuming the condition is derived from a pin disconnection. will behave in a safe way as the overall input supply is discharging.

14.6 External error monitoring (ERRMON)

a non-critical, safety-related external error signal from the system via the ERRMON mechanism. The polarity to detect an external error is programmable in OTP via the OTP_ERRMON_POL bit.

0 Error on rising edge

1 Error on Falling edge

Table 200. ERRMON polarity selection bit indicate an external fault has been confirmed. Figure 42. ERRMON operation states via the ERRMON_TIME bits. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 201. ERRMON timer configuration bit condition in the ERRMON input.

0 No reset (default)

1 Reset on fault confirmed

Table 202. ERRMON reaction configuration bit ERRMON_I interrupt is not masked in the interrupt registers. monitoring for an external error as soon as the RSTB pin is released after the Power-up sequence. will start monitoring the ERRMON input as soon as it enters the RUN state. preventing the FS0B from releasing). ERRMON_I interrupt until the error condition is removed. The GPIO3_S bit can be used to sense the real-time status of the ERRMON input.

14.6.1 ERRMON dynamic characteristic

and TA = 25 °C unless otherwise noted. Table 203. ERRMON dynamic characteristics PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.7 FCCU monitoring

MCU or other protocols compatible with other MCU. set in the OTP registers via the OTP_FCCUx_MODE[1:0] bits. input depending on the targeted safety integrity level of the application. The OTP_FCCU0_MODE[1:0] bits provide the default mode of operation for the FCCU0 pin.

00 No operation

01 Single FCCU0 level monitoring

10 Single FCCU0 PWM monitoring

11 FCCU bistable monitoring

Table 204. FCCU0 mode selection bits The OTP_FCCU1_MODE[1:0] bits provide the default mode of operation for the FCCU1 pin.

01 Single FCCU1 level monitoring

10 Single FCCU1 PWM monitoring

11 XRESET operation

Table 205. FCCU1 mode selection bit Table 206. FCCUx debounce time configuration bit PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

00 No reset (only FS0B)

01 Soft reset (FS0B + supply recovery)

10 Hard reset (full power reset)

11 No reset (only FS0B)

Table 207. FCCUx reaction configuration bit FCCU monitoring is always disabled during the Low-power STANDBY and OFF states. In the Monitored STANDBY state, the system is considered to be in the safe state with the FS0B asserted LOW. Full FCCU monitoring is available during the RUN state as described in this section. interface is defaulted to have effect only over the FS0B pin. section 16.4.2 Reset Conditions for detail description of the soft and hard reset reactions. FS0B will not be released until all fault conditions are removed. disable the pull resistor during the SYSTEM ON states via the respective FCCUx_RPULL_EN bits.

0 Internal resistor disabled

1 Internal resistor enabled

Table 208. FCCUx internal pull resistor selection bits selected pin polarity, as described in the following sections.

14.7.1 FCCU full bistable operation

Figure 43. FCCU bistable protocol During bistable operation, the FCCU0_POL bit will set the polarity to detect a fault condition.

0 Low Low Fault

0 Low High Fault

0 High Low OK

0 High High Fault

1 Low Low Fault

1 Low High OK

1 High Low Fault

1 High High Fault

Table 209. Fault detection in bistable mode detection upon a pin disconnection. Table 210. Pull resistor configuration in bistable mode

14.7.2 Hybrid bistable mode

family of microcontrollers supporting the FCCU interface. conditions with an edge transition to request a PMIC reset if the MCU detects an internal issue during boot-up. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

request to release the safety output (FS0B) to allow normal operation. 16.8.8 FCCU1 (XRESET Mode) for a detailed description of the XRESET behavior. operating in hybrid bistable mode until the FCCU interface is requested to switch to full FCCU mode. Switching to full bistable mode is required, but does not constitute sufficient conditions for releasing the FS0B. The MCU must ensure all conditions are met before requesting an FS0B release via the FS0B_RELEASE bits. Figure 44. FCCU Hybrid bistable operation

The FCCU to XRESET Request command is sent (SYS_CMD[7:0] = 0xBA): to avoid unwanted transition

asserted LOW, either due to a fault condition or commanded by the MCU via the FS0B_RELEASE[7:0] bits. ignore the request and set the BAD_CMD_I to generate an interrupt event to the system.

Device moves into the STBY state (Monitored or LP_STBY): When PF09 is going into any of the STBY

FCCU interface will be reset to the default XRESET operation (FCC0 ignored, FCCU1 = XRESET input). PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Device goes through a Power-up sequence due to a Turn-off event or a hard reset: When the PF09

to full bistable mode via the SYS_CMD[7:0] bits once it has performed its corresponding booting sequence.

14.7.3 Single-ended FCCU-level monitoring

be used to monitor an independent single-ended error signal. The FCCUx_POL bit is used to set the polarity to detect a fault condition on each pin independently.

0 Fault when FCCUx = low

1 Fault when FCCUx = high

Table 211. FCCUx fault detection in single-ended mode polarity, to allow a fault detection upon a pin disconnection.

0 X FCCUx tri-stated

Table 212. Pull resistor selection in single-ended level monitoring

14.7.4 Single-ended FCCU PWM monitoring

used to monitor an independent single-ended PWM error signal. Figure 45. FCCU single-ended PWM operation PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 213. FCCUx error conditions

0 Pull-down disabled

1 Pull-down Enabled

Table 214. FCCUx internal pull resistor selection in single-ended PWM mode

14.7.5 FCCU diagnostics

pin if the interrupt is not masked. The FCCUx_S bit provides the real time status of the corresponding FCCUx input.

0 No error mode

1 FCCU error detected

Table 215. FCCUx sense bit In bistable operation the FCCU0_S bit provides the real time fault status of the FCCU interface. Table 216. FCCU0 sense bit

14.7.6 Electrical characteristics

and TA = 25 °C, unless otherwise noted.

Maximum voltage to ensure a low state – – 0.3*VDDIO V VIH_FCCUx FCCUx high input level threshold 0.7*VDDIO – – V

and TA = 25 °C, unless otherwise noted.

Minimum voltage to ensure a high state VHYST_FCCUx FCCUx input voltage hysteresis 0.1 – 0.4 V RPD_FCCUx FCCUx internal pull-down
FCCUx_RPULL_EN = 1 400 800 1300 kΩ RPU_FCCUx FCCUx internal pullup to VDDIO
FCCUx_RPULL_EN = 1 100 200 400 kΩ tFCCUx_DBNC0 FCCUx debounce time in PWM mode 0.8 1 1.2 μs tFCCUx_DBNC1 FCCUx debounce time
FCCUx_DBNC[1:0] = 00 1 3 4 μs tFCCUx_DBNC2 FCCUx debounce time
FCCUx_DBNC[1:0] = 01 4 6 8 μs tFCCUx_DBNC3 FCCUx debounce time
FCCUx_DBNC[1:0] = 10 8 12 16 μs tFCCUx_DBNC4 FCCUx debounce time
FCCUx_DBNC[1:0] = 11 16 20 24 μs tFCCUx_HF FCCUx high-frequency detection time 6 7.75 10 μs tFCCUx_LF FCCUx low-frequency detection time 51 64 80 μs

Table 217. FCCU electrical characteristics...continued

14.8 ABIST

controller of an OV or UV condition using an internal reference.

OV and UV comparators for each individual SWx, LDOx and VAON supply
OV and UV comparators for each individual VMONx input.
OV comparator for the internal VDIG supply.
OV comparator for the internal VANA supply.
TSD comparator for the thermal monitor
RSTB pin is tested for short to high conditions
FS0B pin is tested for short to high conditions If any of the comparators is not able to toggle during ABIST, the corresponding ABIST flag will be set to 1 to allow the MCU to inspect the fault condition and prevent unsafe operation. The ABIST flags cannot be cleared manually, and they can be cleared only after a new ABIST test is performed and passed. ABIST flags Description AB_SWx_OV SWx OV monitor ABIST flag AB_SWx_UV SWx UV monitor ABIST flag

Table 218. ABIST flags...continued FS0B is used as a safety output. with an FS0B short-to-high condition.

14.9 ABIST on demand

OV/UV comparators for each individual SWx, LDOx and VAON supply
OV/UV comparators for each individual VMONx input
OV monitor for the internal VDIG supply
OV monitor for the internal VANA supply
TSD comparator for the thermal monitor When the ABIST on demand is requested, the ABIST routine will be performed only on voltage regulators and external VMON enabled at the time it is requested. When the FS0B is operating in Active Safe state, if a failure condition is found during the ABIST on demand command, the FS0B will be asserted immediately to place the system in a safe state. The PF09 will not be able to release the FS0B pin until a new ABIST is requested and passed successfully.

14.10 Logic built-in self-test (LBIST)

14.10.1 Startup LBIST

functional integrity of the logic gates controlling the safety mechanism within the digital control unit. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

designer must take into consideration the extra time needed for the LBIST test for every power-on cycle.

OV/UV monitoring logic and deglitchers
FCCU inputs
ERRMON input
Watchdog management
Dynamic CRC
FS0B control logic (on main)
PGOOD control logic
DMS interface logic (on main) If the LBIST routine is failed at power-up, the PF09 will not be able to start a power-up sequence to prevent a startup with a potential single-point or latent failure. For debugging purposes, the LBIST_STATUS[1:0] bits are provided to read the status/result of the LBIST during the DBGOFF state in the event the LBIST has failed. LBIST_STATUS[1:0] LBIST status

00 LBIST not executed

01 Test in progress

10 LBIST Failed

11 LBIST Passed

Table 219. LBIST status bits

14.10.2 LBIST on demand

with always-on operating cycles.

Read all save the Registers content:

LDO1_SEQ[7:0]
LDO2_SEQ[7:0]
LDO3_SEQ[7:0]
SW1_SEQ[7:0]
SW2_SEQ[7:0]
SW3_SEQ[7:0]
SW4_SEQ[7:0]
SW5_SEQ[7:0]
VAON_SEQ[7:0]
VAON[1:0]
VLDO1_RUN[4:0]
VLDO2_RUN[4:0]
VLDO3_RUN[4:0]

Nine-channel power management IC with advanced system safety monitoring

VSW2_RUN[7:0]
VSW3_RUN[7:0]
VSW4_RUN[7:0]
VSW5_RUN[7:0]
VSELECT_EN
LDO1_RUN_EN
LDO2_RUN_EN
LDO3_RUN_EN
SW1_RUN_MODE[1:0]
SW2_RUN_MODE[1:0]
SW3_RUN_MODE[1:0]
SW4_RUN_MODE[1:0]
SW5_RUN_MODE[1:0] 2. Initiate request for LBIST on demand by sending SYS_CMD = 0x4A 3. Wait until the LBIST flag "LBIST_DONE_I" is set to "1" 4. Write back the registers content to the registers 5. Clear the LBIST flag (LBIST_DONE_I) 6. Release FS0B When an LBIST on-demand routine is started, the device will assert the FS0B pin to set the system into a safe state. It will perform the LBIST routine while maintaining functional operation such as providing proper output voltage regulation. The PF09 will test the logic gates controlling the following safety related mechanisms:
OV/UV monitoring logic and deglitchers
FCCU inputs
ERRMON input
Watchdog management
Dynamic CRC
FS0B control logic (on main)
PGOOD control logic
DMS interface logic (on main) During LBIST on demand, the RSTB pin remains released to ensure the MCU is still out of reset and in control of the system operation, in order to maintain a safe state during the execution of the LBIST routine. When the MCU is requesting an LBIST on demand, it knows it will enter a non-monitored condition, therefore it should stop any critical operation and enter a safe state until the LBIST_DONE interrupt is provided. The system can inspect the result for the LBIST routine and proceed to release FS0B via I2C communication. The LBIST_STATUS[1:0] bits will be used to read the status/result of the LBIST after the LBIST_DONE interrupt is generated (see Table 219). If the LBIST routine fails, the PF09 will not be able to release the FS0B pin until a new LBIST on-demand routine is requested and LBIST passes. To prevent a WD desynchronization during LBIST on demand, if the watchdog monitoring is enabled, the WD counter will be temporarily halted during the LBIST routine and it will regain operation when the LBIST_DONE_I flag is cleared. At this point, the system will be able to re-synchronize the WD when it clears the LBIST_DONE_I flag. The FS0B will not release if the LBIST_DONE_I flag is asserted. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring

14.11 Dynamic CRC (DCRC)

The PF09 features a dynamic cyclic redundancy check (DCRC) routine to check the integrity of the functional and OTP configuration registers. The dynamic CRC is able to detect bit-flips in the configuration registers that could lead to a potential single-point or latent failure. A base CRC code is calculated and stored in memory every time a successful I2C transaction is made on the functional registers. The base CRC will be used as the reference value to compare with the check CRC code calculated every 5 ms. If the check CRC code is different from the base CRC code, the dynamic CRC routine is considered a bad dynamic CRC and the PF09 will generate a DCRC_I interrupt to report the fault condition. The dynamic CRC interrupt will assert the INTB pin if the interrupt is not masked. The dynamic CRC routine is performed within the PF09 logic and does not require any interaction with the system MCU, however, a fault condition in the dynamic CRC will require the MCU to evaluate and try to correct the fault condition, to ensure proper operation of the PMIC. A control flag DCRC_FLG bit is provided to help manage a dynamic CRC failure. The DCRC_FLG will be set when a bad dynamic CRC condition is present, and the MCU must clear the flag by writing a 1 to it after taking corrective action. When the DCRC_FLG is cleared, the PF09 will perform a new CRC check to ensure the registers' configuration has been corrected and is able to return to safe operation. A dynamic CRC fault condition can have two levels of severity: 1. The first level of severity includes all fault conditions affecting any of the functional registers. This type of fault can be addressed and fixed by the MCU during the SYSTEM ON states. The second level of severity includes a fault condition affecting any of the OTP configuration registers. This type of fault cannot be cleared by the MCU directly, and the MCU must take proper action to request a PMIC restart to force a clean OTP reload at power up. A dynamic CRC fault condition should be managed as follows: 1. When a dynamic CRC fault condition is present, the PF09 will notify the MCU and set the system into a safe state by asserting the FS0B pin. 2. The MCU must verify and/or reload the expected configuration in the functional registers before trying to clear the DCRC_FLG. 3. The MCU must clear the DCRC_FLG to force a new dynamic CRC calculation and read back the flag again. 4. If the DCRC_FLG was successfully cleared, it means the low-severity fault condition has been cleared, and the MCU can proceed to release the FS0B again. 5. If the DCRC_FLG flag is still present after clearing the DCRC_FLG, it means the high-severity fault is on the OTP registers and cannot be fixed. In this scenario, the MCU must place the system into a safe state before it can request a power-down event via the PWRON pin, or by sending a turnoff event via the SYS_CMD registers (0xA5). Fault conditions in the OTP registers will be mostly latent failures, therefore it is acceptable to allow the system to perform a safe turnoff event to avoid a sudden stop of operation causedby the PMIC. In devices with lower safety integrity level (ASIL B) where the FS0B pin is used as a programmable fault status output, the dynamic CRC can also drive the FS0B if FS0B_DCRC = 1. This allows the system to prioritize the dynamic CRC fault condition over a regular interrupt. The strategy to service the dynamic CRC fault is the same, regardless the mode of operation of the FS0B.

14.12 Digital machine supervisor

In devices targeting high safety integrity levels (ASIL D / SIL 2) with the FS0B operating in an active safe state, the PF09 features an NXP proprietary digital machine supervisor (DMS) block to ensure the main digital control PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

generation, as well as its own independent logic performing key sanity checks on the main digital control logic.

FS0B status
RSTB status
CUTOFF status
Critical fault status
Safety handshake
Register loading aaa-056087 BGMONVDIG OV DMS digital supply M2DMS interface SHS FS0B sDriver RSTB sDriver DMS clock Power cutoff Power cutoff RSTB FS0B VDIG BG1 VDIG OV

20 MHz clock

Nine-channel power management IC with advanced system safety monitoring Because the DMS is intended to detect and protect against random failures in the main control logic, such failures are considered critical and not fixable at the system level. However random conditions may lead to temporary failures that may return to normal operation before they can be considered to be critical failures. Each temporary fault condition will cause the DMS to assert the FS0B pin and set the corresponding interrupt. If the fault condition was cleared before it was considered a critical fault, and the system MCU is still responsive, it can go ahead and clear the interrupt and proceed to release the FS0B pin to resume normal operation. A persistent fault condition will cause the DMS to assert the FS0B and take a strong protective action against a critical fault condition, as defined in the DMS OTP configuration registers. The DMS provides secondary control of the system safety output (FS0B) and system reset signal (RSTB), to ensure the system is placed in a known safe state when a safety-critical fault condition is found in the digital control unit. During system operation, the main digital control unit (DCU) has full control of the FS0B and RSTB pins. If the main DCU becomes unresponsive or there is a failure that may affect the ability of the main DCU to detect a failure, the DMS will take control of the safety outputs and assert the pins to place the system in a safe state. The power cutoff signals in the DMS block provide direct control of the power stage of the voltage regulators, allowing the DMS to disable the output of the power supplies in the event of a critical system failure. Critical faults leading to a non-functional digital controller will result in the DMS forcing a safe state until the condition is removed and the digital circuit is able to recover logic control. Critical faults detected by the DMS but still maintaining the main logic operation will result in the DMS forcing a safe state and requesting the main digital control unit to move into the Deep Fail-safe state (DFS). The PF09 can then exit the DFS state based on the OTP configuration for this state.

14.12.1 DMS safety coverage

The independent power supply (VDIG_DMS) is provided to eliminate common-cause failures with respect to the main digital supply, allowing the DMS to detect a fault condition in the main digital controller due to a bad VDIG supply. The independent DMS clock is provided to eliminate common-cause faults with respect to the main system clocks, allowing the DMS to detect fault conditions in the main digital controller due to clock drift or stuck-at condition. A bidirectional safety handshake protocol (SHS) is provided to verify that the main digital control unit is responsive. The safety handshake uses key information to verify the integrity of the DMS configuration registers and the real-time status of the logic signal controlling the voltage monitoring circuits. The safety handshake protocol is designed in such way that It behaves as a self-redundant mechanism that is able to check for single-point or latent failures in the main digital control unit, as well as latent failures in the DMS block itself. Dedicated input-monitoring signals are also provided to ensure proper operation of key analog blocks that may result in a single-point or latent failure in the main logic controller. These blocks include the main VDIG_OV monitoring and the bandgap comparator, providing a higher level of protection against a random fault that could cause the main digital control unit to become unresponsive, and therefore unable to react.

14.12.2 DMS safety configuration

The severity of the reaction to the various fault conditions is programmable in the main OTP registers. The DMS configuration registers, however, are passed to and stored in the dedicated DMS logic control unit, to ensure the DMS block can perform proper monitoring even if the main logic is lost. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

14.12.2.1 Safety handshake configuration registers

and generate a critical fault condition.

111 No RSTB asserted Infinite

Table 220. SHS faults to assert RSTB

111 No Power Cutoff Infinite

Table 221. SHS faults to power cutoff

14.12.2.2 Bandgap monitor fault protection

DMS sends a critical fault notification to assert the RSTB pin.

00 No assertion

Table 222. BGMON RSTB debounce time to assert RSTB via the DMS...continued disables the power stages of the voltage regulators.

00 No Power Cutoff

Table 223. BGMON debounce time to enable the power cutoff via the DMS

14.12.2.3 VDIG_OV monitor fault protection

DMS sends a critical fault to assert the RSTB pin. Table 224. VDIG_OV debounce time to assert RSTB via the DMS the DMS sends a critical fault to disable the power stages of the voltage regulators. Table 225. VDIG_OV debounce time to enable the power cutoff via the DMS PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.12.3 Electrical characteristics

and TA = 25 °C, unless otherwise noted.

OTP_BGM_RSTB[1:0] = 01 9.5 10 10.5 μs tBGM_RSTB2 BGMON RSTB debounce
OTP_BGM_RSTB[1:0] = 10 95 100 105 μs tBGM_RSTB3 BGMON RSTB debounce
OTP_BGM_RSTB[1:0] = 11 475 500 525 μs tBGM_CUTOFF1 BGMON CUTOFF debounce
OTP_BGM_CUTOFF[1:0] = 01 9.5 10 10.5 μs tBGM_CUTOFF2 BGMON CUTOFF debounce
OTP_BGM_CUTOFF[1:0] = 10 95 100 105 μs tBGM_CUTOFF3 BGMON CUTOFF debounce
OTP_BGM_CUTOFF[1:0] = 11 475 500 525 μs tVDIGOV_DGL VDIG OV input fault deglitch time 90 100 110 μs tVDIGOV_RSTB1 VDIG OV RSTB debounce
OTP_VINOV_RSTB[1:0] = 01 9.5 10 10.5 μs tVDIGOV_RSTB2 VDIG OV RSTB debounce
OTP_VINOV_RSTB[1:0] = 10 95 100 105 μs tVDIGOV_RSTB3 VDIG OV RSTB debounce
OTP_VINOV_RSTB[1:0] = 11 475 500 525 μs tVDIGOV_CUTOFF1 VDIG OV CUTOFF debounce
OTP_VINOV_CUTOFF[1:0] = 01 9.5 10 10.5 μs tVDIGOV_CUTOFF2 VDIG OV CUTOFF debounce
OTP_VINOV_CUTOFF[1:0] = 10 95 100 105 μs tVDIGOV_CUTOFF3 VDIG OV CUTOFF debounce
OTP_VINOV_CUTOFF[1:0] = 11 475 500 525 μs

15 PF09 register map

15.1 Functional registers

Bits are reset when the VDIG_POR is crossed on the rising edge.

Full power cycle (VIN remove)
Returning from ULPOFF state Fault flags are intended to hold fault data through a power-on cycle (LPOFF) and a DFS cycle. BIST Bits are reset during LBIST, ABIST or self test. Bits are loaded with the result of the test. SC Bits self-clear after a write. PWRUP_SEQ Reset with default value before starting a Power-up sequence (power on and hard reset) OFF_OTP Bits are loaded directly from the OTP mirror registers. Reset occurs at the following times
Upon entering LPOFF
Right before entering the Power-up sequence
During a hard-reset event. SOFT_RST Reset with default value before starting a Power-up sequence (power on and hard reset) and after a soft reset. SOFT_OTP_RST Bits are loaded directly from the OTP mirror registers. Reset occurs at the following times
Upon entering LPOFF
Right before entering the Power-up sequence
During a hard reset event.
During a soft reset (if programmed to do so)

Table 227. I2C register reset conditions R Read-only: writing to this bit will have no effect. W Write-only: reading this bit will return a fixed value. RW1C Read current value of the bit, write 1 to clear the bit. Writing 0 will have no effect. RWRO Bit is read/write in the test mode (for debug purposes), and read-only in normal operation. Table 228. I2C bit type definitions Table 229. Functional register map PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

15.2 Functional register reset conditions

Figure 47. Functional bits reset diagram

Transition from the DBGOFF into the Power-up sequence
Device performs a hard reset

Only functional registers following the soft reset will be able to reload the default value when a soft reset occurs. configure the safety reaction. Table 230. Bits reset during soft reset. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

15.3 OTP registers

during the normal system operation. Table 231. OTP register color code Table 232. OTP Register Map PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Nine-channel power management IC with advanced system safety monitoring Note: Switching regulator compensation bits (OTP_SWx_LSEL, OTP_SWx_CCOMP[1:0], OTP_SWx_RCOMP[1:0], OTP_SWx_GM[2:0]) are intended for part optimization and must be recommended by NXP to ensure proper device operation. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

16 ESD requirements

QFN package - all pins – – 500 V ILATCHUP Latch-up current – – 100 mA

Table 233. ESD Ratings All ESD specifications will be compliant with the AEC-Q100 specification. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

17 Thermal characteristics

consideration must be made to ensure device operation below the maximum TJ = 150 °C. Table 234. Thermal characteristics Table 235. QFN56 thermal resistance package dissipation ratings temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [2] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

18 Operating conditions

otherwise noted. Typical values are characterized at VIN = 5.0 V, TA = 25 °C, unless otherwise noted. VDDIO Typical IO Voltage Supply.

VAON regulator disabled
Max IQ Current at TA = 85 °C
VDDIO = 0 V – 5 10 µA IQ_LPOFF Low-power mode quiescent current
VAON regulator disabled
Max IQ current at TA = 85 °C
VDDIO = 0 V – 40 70 µA IQ_SYSON SYSTEM ON quiescent current
VAON regulator disabled
All system regulators off
High-frequency clock enabled
VDDIO = 0 V – 1800 2500 µA IQ_STBY STANDBY quiescent current
VAON regulator disabled
All system regulators off
In low-power Standby (OTP_LP_STBY = 1)
High-frequency clock disabled
Max IQ Current at TA = 85 °C
VDDIO = 0 V – 100 200 µA IQ_DFS Deep Fail-safe (DFS) quiescent current
Max IQ current at TA = 85 °C
VDDIO = 0 V – 40 70 µA

Table 236. Operating conditions [1] VSWxIN must be connected to VIN supply to ensure proper operation of the switching regulators. [2] Minimum VSWxIN supply must be higher than VSWxOUT + headroom. PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Added new part number "MPF0900AVSA0ES" in Table 2
Updated VAON_TON Max value from "1" to "1.7" in Table 109 PF09 v.1.2 11 November 2025
Updated "Automotive qualified by AEC-Q100 rev H up to Grade 1" to "Automotive qualified by AEC-Q100 rev J up to Grade 1" in Section 2 and Section 10.1
Removed "Max value = 400" from IHYS_GPIO1, IHYS_GPIO2, IHYS_GPIO3, IHYS_GPIO4, IHYS_FS0B, IHYS_XFAILB in Table 63
Updated 0x0D DEFAULT value from "0001_1111" to "0011_1111" in Table 229 PF09 v.1.1 15 October 2025 • Updated "OTP_MAX_FS[3:0]" parameter to "OTP_MAX_FS_CNT[3:0]" in Section 11.2.11
Updated description in FLTCNT_FAIL from "The Fault counter reaches the maximum number of failures allowed. (FAULT_CNT[3:0] = MAX_FLT_CNT[3:0]" to "The Fault counter reaches the maximum number of failures allowed. (FAULT_ CNT[3:0] = FAULT_MAX_CNT[3:0]" in Table 57
Removed VAON ILIM INT, VAON ILIM MSK, and VAON ILIM SNS BIT3 register in Table 60
Updated Figure 20 PF09 v.1.0 30 September 2025
Changed Figure 23 title from "Dual PMIC interaction with fault on master device" to "Dual PMIC interaction with fault on controller device"
Updated Table 2
Updated Table 26 – Changed VIN_OV_HYS Min value from "70" to "50" – Added VIN_OV_HYS Typ value as "100"
Updated Table 203 – Changed ERRMON deglitch time Min value from "4" to "9" and Max value from "8" to "11" – Added ERRMON deglitch time Typ value as "10"
Updated how to request LBIST on demand steps in Section 14.10.2
Updated VDDIO description in Table 236 PF09 v.0.7 21 August 2025 • Preliminary data sheet
Global: corrected capitalization, hyphenation, and format (adding and removing subscript format)
Updated Table 2
Table 3: updated watchdog manager characteristic for SIL2 to static watchdog
Figure 16: adjusted font for legibility
Figure 17: adjusted font for legibility
Added table title to Table 59
Added table title to Table 90
Section 12.8.9.2: corrected bit field descriptions for VLDO_RUN and VLDO_STBY
Table 85: corrected bit field descriptions for VLDO_RUN and VLDO_STBY
Section 12.8.10.2: changed LDO2EN to LDO1EN
Section 13.2.2: updated DVS information
Table 126: corrected the heading of the second column
Updated Section 13.2.4
Table 145: added RDSON information
Updated Section 13.2.5
Section 13.2.5.3: corrected VLDOx_RUN bit field description

Added Figure 25
Table 154: added RDSON information
Added Figure 29
Updated Table 180
Updated Section 13.5.1
Updated Section 14.7.2
Updated Section 14.10.2
Updated Table 229
Updated Table 232 PF09 v.0.6 24 June 2025 Initial release of preliminary data sheet

Nine-channel power management IC with advanced system safety monitoring Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. 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Nine-channel power management IC with advanced system safety monitoring Tables Tab. 29. List of channels with selectable power-up Tab. 45. Bits used to disable regulator during UV or Tab. 53. VAON always-on fault management Tab. 59. Interrupt latch, interrupt mask, and sense Tab. 75. FCCU1 pin operation when FCCU block is Tab. 76. FCCU1 pin operation when FCCU block is Tab. 104. Bit groups that may require a secure write PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring Tab. 117. Default SW1 mode selection during Tab. 136. SW2 and SW3 multiphase configuration Tab. 137. SW4 and SW5 multiphase configuration Tab. 152. VLDOxMON blanking time configuration Tab. 158. SWx UV threshold configuration bits during Tab. 159. SWx OV threshold configuration bits during Tab. 162. Hysteresis on 2.5 % OV/UV threshold Tab. 169. VMONx UV threshold selection in Tab. 170. VMONx OV threshold selection in Tab. 171. VMONx monitoring voltage configuration Tab. 176. VLDOxMON monitoring voltage Tab. 177. VLDOxMON masking timer configuration Tab. 179. VLDOxMON settling time configuration bits .. 133 Tab. 183. Frequency spread spectrum center Tab. 186. Enabling FSYNC output frequency enable Tab. 193. Thermal monitoring electrical Tab. 197. System watchdog window configuration Tab. 198. WD_OK events required to reduce the PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring Tab. 211. FCCUx fault detection in single-ended Tab. 212. Pull resistor selection in single-ended level Tab. 214. FCCUx internal pull resistor selection in Tab. 222. BGMON RSTB debounce time to assert Tab. 223. BGMON debounce time to enable the Tab. 224. VDIG_OV debounce time to assert RSTB Tab. 225. VDIG_OV debounce time to enable the Tab. 235. QFN56 thermal resistance package PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring Figures Fig. 7. PF09 Startup from cold boot (VAON as Fig. 8. PMIC Startup from Cold boot (VAON Fig. 9. PMIC Startup from Cold boot (No default Fig. 17. Power-up failure with persistent fault Fig. 23. Dual PMIC interaction with fault on Fig. 27. LDOx Bypass mode RUN to STANDBY Fig. 28. LDOx Bypass mode RUN to STANDBY Fig. 34. External VLDOxMON resistor divider Fig. 50. PCB design guidelines - solder mask Fig. 51. PCB design guidelines - I/O pads and Fig. 52. PCB design guidelines - solder paste PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback

Nine-channel power management IC with advanced system safety monitoring 13.2.2 SW1 (3.5 A peak/valley current mode buck 13.2.3 SW2 - SW5 (2.5 A peak/valley current

13.2.4 LDO1 (500 mA linear regulator with load

13.2.5 LDO2 / LDO3 (200 mA linear regulators

14.1.1 Voltage monitoring during a pin

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2026 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 16 December 2025 Document identifier: PF09

Product Information

MPF0900AVNA5ES specifications and overview.

Summary

Nine-channel power management IC with advanced system safety monitoring Rev. 1.3 - 16 December 2025

Description

Nine-channel power management IC with advanced system safety monitoring Rev. 1.3 - 16 December 2025

Source title MPF0900AVNA5ES Datasheet(PDF) - NXP Semiconductors

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