MPC106ARXTG NXP | Alldatasheet
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Technical content
This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2001. All rights reserved. # MPC106EC/D); specifications not addressed herein are unchanged. (including tables) not included in the hardware specifications are noted. are listed in the following table. For more detailed ordering information, see Table 12.
1.4 Electrical and Thermal Characteristics
for the MPC106 parts described herein. Table 1. Part Numbers Addressed by this Part Number Specification
1.4.1 DC Electrical Characteristics
1.4.2.1 Clock AC Specifications
The following tables provides the revised VCO AC timing specifications for the parts described herein.
1.8.1 PLL Configuration
Table 2. Recommended Operating Conditions Table 6. Clock AC Timing Specifications Table 11. PLL Configuration
16.6 MHz
20 MHz
25 MHz
33.3 MHz
MPC106 Part Number Specifications
Ordering Information
1.10 Ordering Information
The following table provides the ordering information for the extended temperature MPC106 part numbers described herein. 1001 3:1 x4 — 60 (240) 75 (300) —
0011 PLL-bypass
SYSCLK clocks core circuitry directly 1x core/SYSCLK ratio implied
1111 Clock off
PLL[0–3] settings not listed are reserved. Some PLL configurations may select bus, CPU, or VCO frequencies which are not useful, not supported, or not tested. See Section 1.4.2.1, “Clock AC Specifications,” for valid SYSCLK and VCO frequencies. 5:2 clock modes are only supported by MPC106 Rev 4.0; earlier revisions do not support 5:2 clock modes. The 5:2 modes require a 60x bus clock applied to the 60x clock phase (LBCLAIM ) configuration input signal during power-on reset, hard reset, and coming out of sleep and suspend power-saving modes. In PLL-bypass mode, the SYSCLK input signal clocks the internal circuitry directly, the PLL is disabled, and the core/SYSCLK ratio is set for 1:1 mode operation. This mode is intended for factory use and third-party tool vendors only. Note also : The AC timing specifications given in this document do not apply in PLL-bypass mode. In clock-off mode, no clocking occurs inside the MPC106 regardless of the SYSCLK input. Table 12. Ordering Information for the PowerPC 106 Table 11. PLL Configuration (Continued)
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