MPC106ARX66DG

MPC106EC NXP | Alldatasheet

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Order Number: MPC106EC/D Rev. 6, 10/2001 Semiconductor Products Sector This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2001. All rights reserved. Technical Data MPC106 PCI Bridge/Memory Controller Hardware Specifications The Motorola MPC106 PCI bridge/memory controller provides a PowerPC™ microprocessor common hardware reference platform (CHRP™) compliant bridge between the PowerPC microprocessor family and the Peripheral Component Interconnect (PCI) bus. In this document, the term ‘106’ is used as an abbreviation for the phrase ‘MPC106 PCI bridge/memory controller.’ This document contains pertinent physical characteristics of the 106. For functional characteristics, refer to the MPC106 PCI Bridge/Memory Controller User’s Manual This document contains the following topics: Topic Page Section 1.1, “Overview” 2 Section 1.2, “Features” 3 Section 1.3, “General Parameters” 5 Section 1.4, “Electrical and Thermal Characteristics” 5 Section 1.5, “Pin Assignments” 15 Section 1.6, “Pinout Listings 16 Section 1.7, “Package Description” 20 Section 1.8, “System Design Information” 22 Section 1.9, “Document Revision History” 27 Section 1.10, “Ordering Information” 27 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

bits, and floating-point data types of 32 and 64 bits (single-precision and double-precision). http://www.mot.com/SPS/PowerPC/.

1.1 Overview

106 and describes briefly how those units interact. Figure 1. Block Diagram Freescale Semiconductor, Inc.

MPC106 PCI Bridge/Memory Controller Hardware Specifications

Features

The 106 provides a PowerPC microprocessor CHRP-compliant bridge between the PowerPC microprocessor family and the PCI bus. CHRP documentation provides a set of specifications that define a unified personal computer architecture. PCI support allows the rapid design of systems using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The 106 integrates secondary cache control and a high-performance memory controller, uses an advanced, 3.3-V CMOS process technology, and is fully compatible with TTL devices. The 106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds. The 60x address bus is 32 bits wide and the data bus is 64 bits wide. The 60x processor interface of the 106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. The address and data buses are decoupled to support pipelined transactions. The 106 provides support for the following configurations of 60x processors and L2 cache:

• Up to four 60x processors with no L2 cache
• A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal L2 cache controller of the 106
• Up to four 60x processors plus an externally controlled L2 cache (such as the Motorola MPC2605 integrated secondary cache) The memory interface controls processor and PCI interactions to main memory and is capable of supporting a variety of configurations using DRAM, EDO, SDRAM, ROM, or Flash ROM. The PCI interface of the 106 complies with the PCI Local Bus Specification, Revision 2.1, and follows the guidelines in the PCI System Design Guide, Revision 1.0, for host bridge architecture. The PCI interface connects the processor and memory buses to the PCI bus, to which I/O components are connected. The PCI bus uses a 32-bit multiplexed address/data bus, plus various control and error signals. The PCI interface of the 106 functions as both a master and target device. As a master, the 106 supports read and write operations to the PCI memory space, the PCI I/O space, and the PCI configuration space. The 106 also supports PCI special-cycle and interrupt-acknowledge commands. As a target, the 106 supports read and write operations to system memory. The 106 provides hardware support for four levels of power reduction: doze, nap, sleep, and suspend. The design of the MPC106 is fully static, allowing internal logic states to be preserved during all power-saving modes.

1.2 Features

This section summarizes the major features of the 106, as follows:

• 60x processor interface — Supports up to four 60x processors — Supports various operating frequencies and bus divider ratios — 32-bit address bus, 64-bit data bus — Supports full memory coherency — Supports optional 60x local bus slave — Decoupled address and data buses for pipelining of 60x accesses — Store gathering on 60x-to-PCI writes Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MPC106 PCI Bridge/Memory Controller Hardware Specifications

• Secondary (L2) cache control — Configurable for write-through or write-back operation — Supports cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte — Up to 4 Gbytes of cacheable space — Direct-mapped — Supports byte parity — Supports partial update with external byte decode for write enables — Programmable interface timing — Supports pipelined burst, synchronous burst, or asynchronous SRAMs — Alternately supports an external L2 cache controller or integrated L2 cache module
• Memory interface — 1 Gbyte of RAM space, 16 Mbytes of ROM space — Supports parity or error checking and correction (ECC) — High-bandwidth, 64-bit data bus (72 bits including parity or ECC) — Supports fast page mode DRAMs, extended data out (EDO) DRAMs, and synchronous DRAMs (SDRAMs) — Supports 1 to 8 banks of DRAM/EDO/SDRAM with sizes ranging from 2 Mbyte to

128 Mbytes per bank

— ROM space may be split between the PCI bus and the 60x/memory bus (8 Mbytes each) — Supports 8-bit asynchronous ROM or 64-bit burst-mode ROM — Supports writing to Flash ROM — Configurable external buffer control logic — Programmable interface timing

• PCI interface — Compliant with PCI Local Bus Specification, Revision 2.1 — Supports PCI interlocked accesses to memory using LOCK signal and protocol — Supports accesses to all PCI address spaces — Selectable big- or little-endian operation — Store gathering on PCI writes to memory — Selectable memory prefetching of PCI read accesses — Only one external load presented by the MPC106 to the PCI bus — Interface operates at 20–33 MHz — Word parity supported — 3.3 V/5.0 V-compatible
• Support for concurrent transactions on 60x and PCI buses
• Power management — Fully-static 3.3-V CMOS design — Supports 60x nap, doze, and sleep power management modes and suspend mode
• IEEE 1149.1-compliant, JTAG boundary-scan interface
• 304-pin ceramic ball grid array (CBGA) package Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1.3 General Parameters

1.4 Electrical and Thermal Characteristics

This section provides both the AC and DC electrical specifications and thermal characteristics for the 106.

1.4.1 DC Electrical Characteristics

beyond those listed may affect device reliability or cause it permanent damage. these recommended and tested conditions is not guaranteed. Table 1. Absolute Maximum Ratings : Vin must not exceed Vdd by more than 2.5 V at all times including during power-on reset. Freescale Semiconductor, Inc.

Table 3 provides the package thermal characteristics for the 106. Table 5 lists the power consumption of the 106. Table 2. Recommended Operating Conditions Table 3. Package Thermal Characteristics : Refer to Section 1.8, “System Design Information,” for more details about thermal management. Table 4. DC Electrical Specifications Excludes test signals (LSSD_MODE and JTAG signals). . All drivers may optionally be programmed to different driver strengths. Capacitance is periodically sampled rather than 100% tested. Freescale Semiconductor, Inc.

1.4.2 AC Electrical Characteristics

relative to the rising edge of SYSCLK.

1.4.2.1 Clock AC Specifications

Table 5. Power Consumption

• Power consumption for common system configurations assuming 50 pF loads
• Suspend power-saving mode assumes SYSCLK off and PLL in bypass mode.
• Typical power is an average value measured at Vdd = AVdd = 3.30 V and T A = 25 °C.
• Maximum power is measured at Vdd = AVdd = 3.45 V and T A = 25 °C. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 2 provides the SYSCLK input timing diagram. Figure 2. SYSCLK Input Timing Diagram

1.4.2.2 Input AC Specifications

specifications are for operation between 16.67 and 33.33 MHz PCI bus clock (SYSCLK) frequencies. Table 6. Clock AC Timing Specifications Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. Timing is guaranteed by design and characterization and is not tested. The total input jitter (short-term and long-term combined) must be under ±200 ps. asserted for a minimum of 255 bus clocks after the PLL-relock time (100 µs) during the power-on reset sequence. Freescale Semiconductor, Inc.

Figure 3 provides the input timing diagram for the 106. Table 7. Input AC Timing Specifications edge of SYSCLK. Both input and output timings are measured at the pin (see Figure 3). 5 Group III input signals include the following processor and memory interface signals: DL[0–31] and DH[0–31]. (when configured for internal L2 controller). edge of SYSCLK to VOH = 2.4 V or VOL = 0.55 V. IRDY, TRDY, STOP , PAR , PERR, SERR, LOCK, FLSHREQ , and ISA_MASTER. 9 Group VI input signal is the point-to-point PCI GNT input signal. RCS0 , FOE, and DBG0 configuration inputs. nanoseconds) of the parameter in question. 12 These values are guaranteed by design and are not tested. Freescale Semiconductor, Inc.

10 MPC106 PCI Bridge/Memory Controller Hardware Specifications

Figure 3. Input Timing Diagram Figure 4 provides the mode select input timing diagram for the 106. Figure 4. Mode Select Input Timing Diagram

1.4.2.3 Output AC Specifications

Freescale Semiconductor, Inc.

Table 8. Output AC Timing Specifications

12 SYSCLK to output driven (output

18 SYSCLK to AR TR Y high impedance

21 SYSCLK to AR TR Y high impedance

1 These values are guaranteed by design and are not tested. V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 5). 3 The maximum timing specification assumes CL = 50 pF .

5 When the 106 is configured for asynchronous L2 cache SRAMs, the DWE[0–2] signals have a maximum

SYSCLK to output valid time of (0.5 x tPROC ) + 8.0 ns (where tPROC is the 60x bus clock cycle time). 7 The minimum timing specification assumes CL = 0 pF . nanoseconds) of the parameter in question. application note Designing PCI 2.1-Compliant MPC106 Systems (order number AN1727/D). Freescale Semiconductor, Inc.

12 MPC106 PCI Bridge/Memory Controller Hardware Specifications

Figure 5 provides the output timing diagram for the 106. Figure 5. Output Timing Diagram

1.4.3 JTAG AC Timing Specifications

Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)

1 TCK cycle time 40 — ns —

3 TCK rise and fall times 0 3 ns 1

4 TRST setup time to TCK rising edge 10 — ns 2

5 TRST assert time 10 — ns 1

Freescale Semiconductor, Inc.

Figure 6 provides the JTAG clock input timing diagram. Figure 6. JTAG Clock Input Timing Diagram Figure 7 provides the TRST timing diagram. Figure 7. TRST Timing Diagram

6 Boundary-scan input data setup time 5 — ns 3

7 Boundary-scan input data hold time 15 — ns 3

8 TCK to output data valid 0 30 ns 4

9 TCK to output high impedance 0 30 ns 4

10 TMS, TDI data setup time 5 — ns —

11 TMS, TDI data hold time 15 — ns 1

12 TCK to TDO data valid 0 15 ns —

13 TCK to TDO high impedance 0 15 ns —

1 These values are guaranteed by design, and are not tested

2 TRST is an asynchronous signal. The setup time is for test purposes only. 3 Non-test signal input timing with respect to TCK. 4 Non-test signal output timing with respect to TCK. Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued) Freescale Semiconductor, Inc.

14 MPC106 PCI Bridge/Memory Controller Hardware Specifications

Figure 8 provides the boundary-scan timing diagram. Figure 8. Boundary-Scan Timing Diagram Figure 9 provides the test access port timing diagram. Figure 9. Test Access Port Timing Diagram Freescale Semiconductor, Inc.

1.5 Pin Assignments

Figure 10 contains the pin assignments for the MPC106, and Figure 11 provides a key to the shading. Figure 11. Pin Assignments Shading Key Figure 10. Pin Assignments Freescale Semiconductor, Inc.

16 MPC106 PCI Bridge/Memory Controller Hardware Specifications

1.6 Pinout Listings

Table 10. Pinout Listing Freescale Semiconductor, Inc.

Table 10. Pinout Listing (Continued) Freescale Semiconductor, Inc.

18 MPC106 PCI Bridge/Memory Controller Hardware Specifications

Freescale Semiconductor, Inc.

1 All PCI signals are in little-endian bit order. 2 This test signal is for factory use only. It must be pulled up to Vdd for normal device operation. Freescale Semiconductor, Inc.

20 MPC106 PCI Bridge/Memory Controller Hardware Specifications

1.7 Package Description

The following sections provide the package parameters and the mechanical dimensions for the 106.

1.7.1 Package Parameters

The package parameters are as provided in the following list. The package type is a 21 mm x 25 mm, 304-lead C4 ceramic ball grid array (CBGA). Package outline 21 mm x 25 mm Interconnects 303 (16 x 19 ball array minus one) Pitch 1.27 mm Solder attach 63/37 Sn/Pb Solder balls 10/90 Sn/Pb, 0.89 mm diameter Maximum module height 3.16 mm Co-planarity specification 0.15 mm Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1.7.2 Mechanical Dimensions

Figure 12 shows the mechanical dimensions for the MPC106. Figure 12. Mechanical Dimensions Note: All measurements are in mm. Freescale Semiconductor, Inc.

22 MPC106 PCI Bridge/Memory Controller Hardware Specifications

1.8 System Design Information

This section provides electrical and thermal design recommendations for successful application of the 106.

1.8.1 PLL Configuration

configuration input) to resolve clock phasing with the PCI bus clock (SYSCLK). Table 11. PLL Configuration

16.6 MHz

20 MHz

25 MHz

33.3 MHz

0011 PLL-bypass 3 PLL off

1111 Clock off 4 PLL off

2 5:2 clock modes are only supported by MPC106 Rev 4.0; earlier revisions do not support 5:2 clock modes. during power-on reset, hard reset, and coming out of sleep and suspend power-saving modes. 4 In clock-off mode, no clocking occurs inside the MPC106 regardless of the SYSCLK input. Freescale Semiconductor, Inc.

1.8.2 PLL Power Supply Filtering

The A Vdd power signal is provided on the 106 to provide power to the clock generation phase-locked loop. the A Vdd pin to ensure it filters out as much noise as possible. Figure 13. PLL Power Supply Filter Circuit

1.8.3 Decoupling Recommendations

power surges and high frequency noise in its power supply, especially while driving large capacitive loads. clean, tightly regulated source of power. (SMT) capacitors should be used to minimize lead inductance. should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100 µF (A VX TPS tantalum) or 330 µF (A VX TPS tantalum).

1.8.4 Connection Recommendations

To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. be tied (using pull-down resistors) to GND. All no-connect (NC) signals must remain unconnected. Power and ground connections must be made to all external Vdd, A Vdd, and GND pins of the 106.

1.8.4.1 Pull-up Resistor Recommendations

Freescale Semiconductor, Inc.

24 MPC106 PCI Bridge/Memory Controller Hardware Specifications

the system. It is recommended that these signals be pulled up or restored in some manner by the system. pull-up resistors on these signals. recommendations for the MPC106.

1.8.5 Thermal Management Information

design is primarily dependent on the system-level design. Table 12. Pull-Up/Pull-Down Recommendations these may be pulled up to 3.3 VDC. Freescale Semiconductor, Inc.

Figure 14. Exploded Cross-Sectional View

1.8.5.1 Internal Package Conduction Resistance

• The die junction-to-case thermal resistance
• The die junction-to-lead thermal resistance These parameters are shown in Table 13. In this C4/CBGA package, the silicon chip is exposed; therefore, the package “case” is the top of the silicon. Figure 15 provides a simplified thermal network in which a C4/CBGA package is mounted to a printed-circuit board.

Figure 15. C4/CBGA Package Mounted to a Printed-Circuit Board Table 13. Thermal Resistance Freescale Semiconductor, Inc.

26 MPC106 PCI Bridge/Memory Controller Hardware Specifications

1.8.5.2 Board and System-Level Modeling

CBGA thermal models are available on request within FLOTHERM® . Table 14. Die Junction-to-Ambient Thermal Resistance Freescale Semiconductor, Inc.

1.9 Document Revision History

Table 15 lists significant changes between revisions of this document. Table 15. Document Revision History

66 Mhz and from 7 ns to 6 ns at 83 MHz

and included in Specifications 3, 7, and 11. All to reflect current production test. Table 1 and Table 2 include notes on extended temperature parts. Table 9, and Table 10. Added new footnote 2 to Table 6. Changed part number key. Freescale Semiconductor, Inc.

Opportunity/Affirmative Action Employer. DigitalDNA is a trademark of Motorola, Inc. under license from International Business Machines Corporation.

1.10 Ordering Information

for identification purposes only. 1 See Part Number Specifications (MPC106ARXTGPNS/D). 2 For current revision level, contact local Motorola sales office. Figure 16. Part Number Key Freescale Semiconductor, Inc.