MPC105 NXP | Alldatasheet
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(Motorola Order Number) The PowerPC name, PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 604, and PowerPC Architecture are trademarks of International Business Machines Cirp. used by Motorola under license from International Business Machines Corp. This document contains information on a new product under development by Motorola. Motorola reserves the right to Ô change or discontinue this product without notice. Ó Motorola Inc. 1995. All rights reserved.
105 Hardware Specifications
MPC105 PCI Bridge/Memory Controller Hardware Specifications The MPC105 provides a PowerPC Ô reference platform compliant-bridge between the PowerPC microprocessor family and the Peripheral Component Interconnect (PCI) bus. This document contains pertinent physical characteristics of the MPC105. For functional characteristics refer to the MPC105 PCI Bridge/Memory Controller User’ s Manual This document contains the following topics: Topic Page Section 1.1, “MPC105 Overview” 2 Section 1.2, “General Parameters” 3 Section 1.3, “MPC105 Electrical and Thermal Characteristics” 4 Section 1.4, “MPC105 Pinout Diagram” 12 Section 1.5, “MPC105 Package Description” 17 Section 1.6, “System Design Information” 19 In this document, the term “60x” is used to denote a 32-bit microprocessor from the PowerPC Architecture Ô family. 60x processors implement the PowerPC architecture as it is specified for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits (single-precision and double-precision). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
2 105 Hardware Specifications Preliminary/Subject to Change without Notice
1.1 MPC105 Overview
The MPC105 provides a PowerPC reference platform-compliant bridge between PowerPC 601 Ô PowerPC 603 Ô , and PowerPC 604 Ô microprocessors and the PCI bus. PCI support allows system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The MPC105 integrates secondary cache control and a high-performance memory controller that supports DRAM, synchronous DRAM (SDRAM), ROM, and Flash ROM. The MPC105 uses an advanced, 3.3 V CMOS process technology and is fully compatible with TTL devices. The MPC105 supports a programmable interface to a variety of PowerPC microprocessors operating at various bus speeds. The MPC105’s 60x interface allows for a variety of system configurations by providing support for either a second processor or a secondary (L2) cache. The L2 cache control unit generates the arbitration and support signals necessary to maintain a write-through or write-back lookaside cache. The MPC105’s PCI interface is designed to connect the processor and memory system to the PCI local bus without the need for “glue” logic. The MPC105 acts as both a master and slave device on the PCI bus. The memory interface controls processor and PCI interactions to main memory. It is capable of supporting a variety of DRAM or SDRAM, and ROM or Flash ROM configurations. The MPC105 provides hardware support for four levels of power reduction—nap, doze, sleep, and suspend. The MPC105’s design is fully static, allowing internal logic states to be preserved during all power saving modes.
1.1.1 MPC105 Features
Major features of the MPC105 are as follows:
- Processor interface — 60x processors supported at a wide range of frequencies — 32-bit address bus — Configurable 64- or 32-bit data bus — Accommodates an upgrade of either an external L2 cache or a secondary processor — Arbitration for secondary processor on-chip — Full memory coherency supported — Pipelining of 60x accesses — Store gathering on 60x-to-PCI writes
- Secondary (L2) cache control — Configurable for write-through or write-back operation — 256K, 512K, 1M sizes — Up to 4 Gbytes of cacheable space — Direct-mapped — Parity supported — Supports external byte decode or on-chip byte decode for write enables — Programmable timing supported — Synchronous burst and asynchronous SRAMs supported Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
105 Hardware Specifications 3
Preliminary/Subject to Change without Notice
- PCI interface — Compliant with PCI Local Bus Specification, Revision 2.0 — Supports PCI interlocked accesses to memory using LOCK signal and protocol — Supports accesses to all PCI address spaces — Selectable big- or little-endian operation — Store gathering on PCI writes to memory — Selectable memory prefetching of PCI read accesses — Only one external load presented by the MPC105 to the PCI bus — PCI configuration registers — Interface operates at 16–33 MHz — Data buffering (in/out) — Parity supported — 3.3 V/5.0 V compatible
- Concurrent transactions on 60x and PCI buses supported
- Memory interface — Programmable timing supported — Supports either DRAM or SDRAM — High bandwidth (64-bit) data bus — Supports self-refreshing DRAM in sleep and suspend modes — Supports 1 to 8 banks built of x1, x4, x8, x9, x16, or x18 DRAMs — Supports PowerPC reference platform-compliant contiguous or discontiguous memory maps — 1 Gbyte of RAM space, 16 Mbytes of ROM space — Supports 8-bit asynchronous ROM or 32-/64-bit burst-mode ROM — Supports writing to Flash ROM — Configurable external buffer control logic — Parity supported — TTL compatible
- Power management — Fully-static 3.3 V CMOS design — Supports 60x nap, doze, and sleep power management modes, and suspend mode
- IEEE 1149.1-compliant, JTAG boundary-scan interface
- 304-pin ball grid array (BGA) package
1.2 General Parameters
The following list provides a summary of the general parameters of the MPC105. Technology 0.5 m m CMOS, four-layer metal Chip size 6.69 mm x 5.82 mm (38.9 mm Chip performance 25 MHz, 33.33 MHz, 50 MHz, and 66.67 MHz Package Surface mount 304-pin C4 ceramic ball grid array (CBGA) Power supplies 3.3 V Maximum input rating 5.0 V 10% Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.3 MPC105 Electrical and Thermal Characteristics
recent specifications, contact your local Motorola sales office.
1.3.1 DC Electrical Characteristics
Table 1 and Table 2 provide the absolute maximum rating and thermal characteristics for the MPC105. Table 3 provides the DC electrical characteristics for the MPC105. Table 1. Absolute Maximum Ratings
- Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only,
device reliability or cause permanent damage to the device. including during power-on reset. Table 2. Thermal Characteristics Table 3. DC Electrical Specifications Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
105 Hardware Specifications 5
Table 4 provides the power dissipation for the MPC105.
1.3.2 AC Electrical Characteristics
This section provides the clock AC electrical characteristics for the MPC105.
1.3.2.1 Input AC Specifications
operation between 16.67 and 33.33 MHz bus clock (SYSCLK) frequencies.
- Capacitance is periodically sampled rather than 100% tested.
Table 4. Power Dissipation
- Power dissipation for common system configurations assuming 50 pF loads
- Power saving modes assume system clock off.
- Suspend power saving mode assumes system clock off and PLL in clock bypass mode.
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Figure 1. SYSCLK Input Timing Diagram
1.3.2.2 Input AC Specifications
Table 6 provides the input AC timing specifications for the MPC105 as defined in Figure 2 and Figure 3. These specifications are for operation between 16.67 and 33.33 MHz bus clock (SYSCLK) frequencies. Table 5. Clock AC Timing Specifications
6 SYSCLK frequency stability — 1000 ppm
7 SYSCLK jitter —
8 MPC105 internal PLL relock time — 100
9 Phase-lock loop VCO operating range 120 200 MHz 5
- Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
- Specification value is at maximum frequency of operation.
- Relock timing is guaranteed by design and is not tested.
- For configuration of the VCO, see Table 10.
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105 Hardware Specifications 7
Table 6. Input AC Timing Specifications
10 A0–A31, PAR0–PAR7, TT0–TT4, AACK , TA, GBL, CI, WT, TV
12 HIT , TS, ARTR Y, BR0, BR1, XATS input signals valid to SYSCLK
13 Mode select inputs valid to HRST (input setup) 3
14 LOCK , FLSHREQ , ISA_MASTER ,
15 PCI point-to-point signals input signals valid to SYSCLK (input
16 SYSCLK to inputs invalid
17 SYSCLK to PCI inputs invalid
and falling edge of SYSCLK). Both input and output timings are measured at the pin.
- Inputs are composed of the following processor interface signals—A0–A31, PAR0–PAR7,
TT0–TT4, AACK, TA, GBL, CI, WT, TV.
- Inputs are composed of the following processor interface signals—DL0–DL31, DH0–DH31, TBST,
- Inputs are composed of the following processor and L2 interface signals—HIT, TS, ARTR Y, BR0,
- The setup and hold time is with respect to the rising edge of HRST; see Figure 3. The following
- Inputs are composed of all PCI bus signals: LOCK, FLSHREQ , ISA_MASTER , C/BE0–C/BE3,
PAR, TRDY, IRDY, FRAME , STOP , DEVSEL, PERR, SERR, AD0–AD31.
- Inputs are composed of all PCI point-to-point signals. GNT has a setup time of 10.0 ns for a 33
- Guaranteed by design, not tested.
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Figure 2. Input Timing Diagram Figure 3. Mode Select Input Timing Diagram
1.3.2.3 Output AC Specifications
Table 7. Output AC Timing Specifications
20 SYSCLK to output valid
21 SYSCLK to output valid
22 SYSCLK to output valid (for TS, ARTR Y, all non-PCI
23 SYSCLK to output valid
24 SYSCLK to output valid
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105 Hardware Specifications 9
25 SYSCLK to output invalid
27 SYSCLK to AR TR Y high impedance before precharge
30 SYSCLK to AR TR Y high impedance after precharge (1X,
SYSCLK). Both input and output timings are measured at the pin.
- All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level
(0.8 V or 2.0 V) of the signal in question. The output timings are measured at the pin.
- Maximum timing specifications assume CL = 50 pF.
- PCI bus signals are composed of the following signals—LOCK, MEMACK , ISA_MASTER ,
C/BE0–C/BE3, PAR, TRDY, FRAME , STOP , DEVSEL, PERR, SERR, and AD0–AD31.
- PCI point-to-point signals are composed of the GNT signal.
- tSYS is the period of the external bus clock (SYSCLK) in nanoseconds. The numbers given in the table
- These specifications are nominal values.
- Shared outputs, TS and ARTR Y, require pull-up resistors to hold them negated when there is no bus
Table 7. Output AC Timing Specifications (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 4. Output Timing Diagram
1.3.3 JTAG AC Timing Specifications
Table 8 provides the JTAG AC timing specifications. Table 8. JTAG AC Timing Specifications (Independent of SYSCLK)
1 TCK cycle time 40 — ns
3 TCK rise and fall times 0 3 ns
4 TRST setup time to TCK falling edge 10 — ns
5 TRST assert time 10 — ns
6 Boundary-scan input data setup time 5 — ns
7 Boundary-scan input data hold time 15 — ns
8 TCK to output data valid 0 30 ns
9 TCK to output high impedance 0 30 ns
10 TMS, TDI data setup time 5 — ns
11 TMS, TDI data hold time 15 — ns
121 TCK to TDO data valid 0 15 ns
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105 Hardware Specifications 11
Figure 5 provides the JTAG clock input timing diagram. Figure 5. Clock Input Timing Diagram Figure 6 provides the TRST timing diagram. Figure 6. TRST Timing Diagram Figure 7 provides the boundary-scan timing diagram. Figure 7. Boundary-Scan Timing Diagram
131 TCK to TDO high impedance 0 15 ns
Table 8. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
105 Hardware Specifications 13
1.4 MPC105 Pinout Diagram
Figure 9 contains the pin assignments for the MPC105. Figure 10 provides a key to the shading in Figure 9. Figure 10. Pin Assignments Shading Key Figure 9. Pin Assignments Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Table 9 provides the pinout listing for the MPC105. Table 9. Pinout Listing1 Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
105 Hardware Specifications 15
Table 9. Pinout Listing1 (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
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105 Hardware Specifications 17
- Some signals have dual functions and are shown more than once in this table.
- This test signal is for factory use only. It must be pulled up to Vdd for normal machine
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18 105 Hardware Specifications Preliminary/Subject to Change without Notice
1.5 MPC105 Package Description
The following sections provide the package parameters and the mechanical dimensions for the MPC105.
1.5.1 Package Parameters
The package parameters are as provided in the following list. The package type is a 21 mm x 25 mm, 304- pin C4 ceramic ball grid array (CBGA). Package outline 21 mm x 25 mm Interconnects 303 Pitch 1.27 mm Solder attach 63/37 Sn/Pb Solder balls 10/90 Sn/Pb Maximum module height 3.16 mm Co-planarity specification 0.20 mm Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
105 Hardware Specifications 19
1.5.2 Mechanical Dimensions
Figure 11 shows the mechanical dimensions for the MPC105. Figure 11. MPC105 Mechanical Dimensions Note: All measurements are in mm. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.6 System Design Information
MPC105 PCI Bridge/Memory Controller.
1.6.1 PLL Configuration
configurations required for different ratios between the processor bus frequency and the PCI bus frequency. Table 10. PLL Configuration should not fall below 120 MHz, and should not exceed 200 MHz.
- In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, and the
- The PLL_CFG0–PLL_CFG1 signals select the CPU-to-bus ratio (1:1, 2:1) and the
PLL_CFG2–PLL_CFG3 signals select the PCI-to-PLL multiplier (x2, x4, x8).
- The level 2 cache and memory interfaces will function at the processor bus frequency.
1.6.2 PLL Power Supply Filtering
A Vdd pin to ensure it filters out as much noise as possible.
16.6 MHz
20 MHz
25 MHz
33.3 MHz
0011 PLL bypass
1111 Clock off
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105 Hardware Specifications 21
Figure 12. PLL Power Supply Filter Circuit
1.6.3 Decoupling Recommendations
resistance) rating to at least one Vdd pin of the MPC105. connections must be made to all external Vdd and GND pins of the MPC105.
1.6.4 Connection Recommendations
pull-up resistors for proper device operation.
1.6.5 MPC105 Thermal Management Information
Figure 13. Exploded Cross-Sectional View
10 Ohms
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1.6.5.1 Internal Package Conduction Resistance
- The die junction-to-case thermal resistance
- The die junction-to-lead thermal resistance These parameters are shown in Table 11. In this C4/CBGA package, the silicon chip is exposed; therefore, the package “case” is the top of the silicon. Figure 14 provides a simplified thermal network in which a C4/CBGA package is mounted to a printed- circuit board.
Figure 14. C4/CBGA Package Mounted to a Printed-Circuit Board
1.6.5.2 Board and System-Level Modeling
Table 11. Thermal Resistance Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
105 Hardware Specifications 23
CBGA thermal models are available within FLOTHERMÒ . These are available upon request. Table 12. Die Junction-to-Ambient Thermal Resistance Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. IBM is a registered trademark of IBM Corp. The PowerPC name, PowerPC logotype, PowerPC Architecture, PowerPC 603, and PowerPC 604 are trademarks of International Business Machines Corp. used by Motorola under license from IBM Corp. Motorola Literature Distribution Centers: USA: Motorola Literature Distribution, P.O. Box 20912, Phoenix, Arizona 85036; FAX (602) 994-6430. JAPAN: Nippon Motorola Ltd., 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd., Silicon Harbour Centre, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. Technical Information: Motorola Inc. Semiconductor Products Sector Technical Responsiveness Center; (800) 521-6274. Document Comments : FAX (512) 891-2638, Attn: RISC Applications Engineering. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.