MPC1055L1R0C

TPS51916_12 TI1 | Alldatasheet

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www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 CompleteDDR2,DDR3andDDR3LMemoryPowerSolutionSynchronousBuck Controller,2-ALDO,BufferedReference 1FEATURES DESCRIPTION The TPS51916 providesa completepower supplyfor 2• Synchronous Buck Controller(VDDQ) DDR2, DDR3 and DDR3L memory systems in the– Conversion VoltageRange: 3 V to28 V lowesttotalcostand minimum space.Itintegratesa – Output VoltageRange: 0.7V to1.8V synchronousbuck regulatorcontroller(VDDQ) witha 2-A sink/sourcetrackingLDO (VTT)and bufferedlow– 0.8% VREF Accuracy noisereference(VTTREF). The TPS51916 employs– SelectableControlArchitecture D-CAP ™ mode coupled with 300 kHz/400 kHz – D-CAP ™ Mode forFastTransient frequenciesfor ease-of-use and fast transient Response response or D-CAP2 ™ mode coupled with higher 500 kHz/670 kHz frequenciesto supportceramic– D-CAP2 ™ Mode forCeramic Output outputcapacitorwithoutan externalcompensationCapacitors circuit.The VTTREF tracksVDDQ/2 withinexcellent– Selectable300 kHz/400 kHz/500 kHz/ 0.8% accuracy. The VTT, which provides 2-A670 kHz SwitchingFrequencies sink/sourcepeak currentcapabilities,requiresonly – OptimizedEfficiencyatLightand Heavy 10-μF of ceramic capacitance.In addition,a dedicatedLDO supplyinputisavailable.Loads withAuto-skipFunction – Supports Soft-OffinS4/S5 States The TPS51916 providesrichusefulfunctionsas well as excellentpower supplyperformance.Itsupports– OCL/OVP/UVP/UVLO Protections flexiblepower statecontrol,placingVTT athigh-Zin– Powergood Output S3 and dischargingVDDQ, VTT and VTTREF (soft-

• 2-A LDO(VTT), BufferedReference(VTTREF) off)inS4/S5 state.Programmable OCL withlow-side MOSFET R DS(on) sensing, OVP/UVP/UVLO and– 2-A (Peak)Sink and Source Current thermalshutdownprotectionsarealsoavailable.– RequiresOnly 10-μF ofCeramic Output Capacitance The TPS51916 isavailablein a 20-pin,3 mm × 3 mm, QFN package and is specifiedfor ambient– Buffered,Low Noise,10-mA VTTREF temperaturefrom–40°C to85°C.Output – 0.8% VTTREF, 20-mV VTT Accuracy – Support High-ZinS3 and Soft-OffinS4/S5
• Thermal Shutdown
• 20-Pin,3 mm × 3 mm, QFN Package

APPLICATIONS

• DDR2/DDR3/DDR3L Memory Power Supplies
• SSTL_18, SSTL_15, SSTL_135 and HSTL Termination Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2D-CAP, D-CAP2 aretrademarksofTexas Instruments. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ORDERING INFORMATION (1) ORDERABLE DEVICE OUTPUT MINIMUMTA PACKAGE PINSNUMBER SUPPLY QUANTITY TPS51916RUKR Tape and reel 3000 –40°C to85°C PlasticQuad FlatPack (QFN) 20 TPS51916RUKT Minireel 250 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT MIN MAX VBST –0.3 36 VBST (3) –0.3 6 SW –5 30 Inputvoltagerange(2) VLDOIN, VDDQSNS, REFIN –0.3 3.6 V VTTSNS –0.3 3.6 PGND, VTTGND –0.3 0.3 V5IN,S3,S5,TRIP,MODE –0.3 6 DRVH –5 36 DRVH (3) –0.3 6 VTTREF, VREF –0.3 3.6 Outputvoltagerange(2) V VTT –0.3 3.6 DRVL –0.3 6 PGOOD –0.3 6 Junctiontemperaturerange,TJ 125 °C Storagetemperaturerange,TSTG –55 150 °C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagevaluesarewithrespecttothenetworkgroundterminalunlessotherwisenoted. (3) VoltagevaluesarewithrespecttotheSW terminal. THERMAL INFORMATION TPS51916 THERMAL METRIC UNITS QFN (20)PINS θJA Junction-to-ambientthermalresistance 94.1 θJCtop Junction-to-case(top)thermalresistance 58.1 θJB Junction-to-boardthermalresistance 64.3 °C/W ψJT Junction-to-topcharacterizationparameter 31.8 ψJB Junction-to-boardcharacterizationparameter 58.0 θJCbot Junction-to-case(bottom)thermalresistance 5.9

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www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Supplyvoltage V5IN 4.5 5.5 V VBST –0.1 33.5 VBST (1) –0.1 5.5 SW -3 28 SW (2) –4.5 28 Inputvoltagerange V VLDOIN, VDDQSNS, REFIN –0.1 3.5 VTTSNS –0.1 3.5 PGND, VTTGND –0.1 0.1 S3,S5,TRIP,MODE –0.1 5.5 DRVH –3 33.5 DRVH (1) –0.1 5.5 DRVH (2) –4.5 33.5 Outputvoltagerange VTTREF, VREF –0.1 3.5 V VTT –0.1 3.5 DRVL –0.1 5.5 PGOOD –0.1 5.5 TA Operatingfree-airtemperature –40 85 °C (1) VoltagevaluesarewithrespecttotheSW terminal. (2) Thisvoltageshouldbe appliedforlessthan30% oftherepetitiveperiod. Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3

SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com

ELECTRICAL CHARACTERISTICS

overoperatingfree-airtemperaturerange,VV5IN = 5 V,VLDOIN isconnectedtoVDDQ output,VMODE = 0 V,VS3= VS5= 5 V (unlessotherwisenoted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IV5IN(S0) V5IN supplycurrent,inS0 TA = 25°C, No load,VS3 = VS5 = 5 V 590 μA IV5IN(S3) V5IN supplycurrent,inS3 TA = 25°C, No load,VS3 = 0 V,VS5 = 5 V 500 μA IV5INSDN V5IN shutdowncurrent TA = 25°C, No load,VS3 = VS5 = 0 V 1 μA IVLDOIN(S0) VLDOIN supplycurrent,inS0 TA = 25°C, No load,VS3 = VS5 = 5 V 5 μA IVLDOIN(S3) VLDOIN supplycurrent,inS3 TA = 25°C, No load,VS3 = 0 V,VS5 = 5 V 5 μA IVLDOINSDN VLDOIN shutdowncurrent TA = 25°C, No load,VS3 = VS5 = 0 V 5 μA VREF OUTPUT IVREF = 30 μA,TA = 25°C 1.8000 VVREF Outputvoltage 0 μA ≤ IVREF <300 μA,TA = –10°C to85°C 1.7856 1.8144 V 0 μA ≤ IVREF <300 μA,TA = –40°C to85°C 1.7820 1.8180 IVREFOCL Currentlimit VVREF = 1.7V 0.4 0.8 mA VTTREF OUTPUT VVTTREF Outputvoltage VVDDQSNS /2 V |IVTTREF |<100 μA,1.2V ≤ VVDDQSNS ≤ 1.8V 49.2% 50.8% VVTTREF OutputvoltagetolerancetoVVDDQ |IVTTREF |<10 mA, 1.2V ≤ VVDDQSNS ≤ 1.8V 49% 51% IVTTREFOCLSRC Sourcecurrentlimit VVDDQSNS = 1.8V,VVTTREF = 0 V 10 18 mA IVTTREFOCLSNK Sinkcurrentlimit VVDDQSNS = 1.8V,VVTTREF = 1.8V 10 17 mA IVTTREFDIS VTTREF dischargecurrent TA = 25°C, VS3 = VS5 = 0 V,VVTTREF = 0.5V 0.8 1.3 mA VTT OUTPUT VVTT Outputvoltage VVTTREF V |IVTT |≤ 10 mA, 1.2V ≤ VVDDQSNS ≤ 1.8V,IVTTREF = 0 A –20 20 |IVTT |≤ 1 A,1.2≤ VVDDQSNS ≤ 1.8V,IVTTREF = 0 A –30 30 VVTTTOL OutputvoltagetolerancetoVTTREF mV |IVTT |≤ 2 A,1.4V ≤ VVDDQSNS ≤ 1.8V,IVTTREF = 0 A –40 40 |IVTT |≤ 1.5A,1.2V ≤ VVDDQSNS ≤ 1.4V,IVTTREF = 0 A –40 40 IVTTOCLSRC Sourcecurrentlimit VVDDQSNS = 1.8V,VVTT = VVTTSNS = 0.7V,IVTTREF = 0 A 2 3 A IVTTOCLSNK Sinkcurrentlimit VVDDQSNS = 1.8V,VVTT = VVTTSNS = 1.1V,IVTTREF = 0 A 2 3 IVTTLK Leakage current TA = 25°C ,VS3 = 0 V,VS5 = 5 V,VVTT = VVTTREF 5 IVTTSNSBIAS VTTSNS inputbiascurrent VS3 = 5 V,VS5 = 5 V,VVTTSNS = VVTTREF –0.5 0.0 0.5 μA IVTTSNSLK VTTSNS leakagecurrent VS3 = 0 V,VS5 = 5 V,VVTTSNS = VVTTREF –1 0 1 TA = 25°C, VS3 = VS5 = 0 V,VVDDQSNS = 1.8V,IVTTDIS VTT Dischargecurrent 7.8 mAVVTT = 0.5V,IVTTREF = 0 A VDDQ OUTPUT VVDDQSNS VDDQ sense voltage VREFIN VDDQSNS regulationvoltageVVDDQSNSTOL TA = 25°C –3 3 mVtolerancetoREFIN IVDDQSNS VDDQSNS inputcurrent VVDDQSNS = 1.8V 39 μA IREFIN REFIN inputcurrent VREFIN = 1.8V –0.1 0.0 0.1 μA VS3 = VS5 = 0 V,VVDDQSNS = 0.5V,MODE pinpulledIVDDQDIS VDDQ dischargecurrent 12 mAdown toGND through47kΩ (Non-tracking) VS3 = VS5 = 0 V,VVDDQSNS = 0.5V,MODE pinpulledIVLDOINDIS VLDOIN dischargecurrent 1.2 Adown toGND through100kΩ (Non-tracking) SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY VIN = 12 V,VVDDQSNS = 1.8V,R MODE = 100 kΩ 300 VIN = 12 V,VVDDQSNS = 1.8V,R MODE = 200 kΩ 400 fSW VDDQ switchingfrequency kHz VIN = 12 V,VVDDQSNS = 1.8V,R MODE = 1 kΩ 500 VIN = 12 V,VVDDQSNS = 1.8V,R MODE = 12 kΩ 670 tON(min) Minimum on time DRVH risingtofalling(1) 60 ns tOFF(min) Minimum offtime DRVH fallingtorising 200 320 450 (1) Ensuredby design.Not productiontested.

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www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,VV5IN = 5 V,VLDOIN isconnectedtoVDDQ output,VMODE = 0 V,VS3= VS5= 5 V (unlessotherwisenoted) PARAMETER TEST CONDITION MIN TYP MAX UNIT VDDQ MOSFET DRIVER Source,IDRVH = –50 mA 1.6 3.0 R DRVH DRVH resistance Sink,IDRVH = 50 mA 0.6 1.5 Ω Source,IDRVL = –50 mA 0.9 2.0 R DRVL DRVL resistance Sink,IDRVL = 50 mA 0.5 1.2 DRVH-offtoDRVL-on 10 tDEAD Dead time ns DRVL-offtoDRVH-on 20 INTERNAL BOOT STRAP SW VFBST ForwardVoltage VV5IN-VBST ,TA = 25°C, IF = 10 mA 0.1 0.2 V IVBSTLK VBST leakagecurrent TA = 25°C, VVBST = 33 V,VSW = 28 V 0.01 1.5 μA LOGIC THRESHOLD IMODE MODE sourcecurrent 14 15 16 μA MODE 0-1 109 129 149 MODE 1-2 235 255 275 MODE 2-3 392 412 432 VTHMODE MODE thresholdvoltage MODE 3-4 580 600 620 mV MODE 4-5 829 854 879 MODE 5-6 1202 1232 1262 MODE 6-7 1760 1800 1840 VIL S3/S5 low-levelvoltage 0.5 VIH S3/S5 high-levelvoltage 1.8 V VIHYST S3/S5 hysteresisvoltage 0.25 IILK S3/S5 inputleakcurrent –1 0 1 μA SOFT START Internalsoft-starttime,C VREF = 0.1μF,tSS VDDQ soft-starttime 1.1 msS5 risingtoVVDDQSNS > 0.99× VREFIN PGOOD COMPARATOR PGOOD infromhigher 106% 108% 110% PGOOD infromlower 90% 92% 94% VTHPG VDDQ PGOOD threshold PGOOD outtohigher 114% 116% 118% PGOOD outtolower 82% 84% 86% IPG PGOOD sinkcurrent VPGOOD = 0.5V 3 5.9 mA DelayforPGOOD in 0.8 1 1.2 ms tPGDLY PGOOD delaytime DelayforPGOOD out,with100 mV overdrive 330 ns tPGSSDLY PGOOD start-updelay C VREF = 0.1μF,S5 risingtoPGOOD rising 2.5 ms Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5

SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,VV5IN = 5 V,VLDOIN isconnectedtoVDDQ output,VMODE = 0 V,VS3= VS5= 5 V (unlessotherwisenoted) PARAMETER TEST CONDITION MIN TYP MAX UNIT PROTECTIONS ITRIP TRIP sourcecurrent TA = 25°C, VTRIP = 0.4V 9 10 11 μA TRIP sourcecurrenttemperatureTC ITRIP 4700 ppm/°Ccoefficient(2) VTRIP VTRIP voltagerange 0.2 3 V VTRIP = 3.0V 360 375 390 VOCL Currentlimitthreshold VTRIP = 1.6V 190 200 210 mV VTRIP = 0.2V 20 25 30 VTRIP = 3.0V –390 –375 –360 VOCLN Negativecurrentlimitthreshold VTRIP = 1.6V –210 –200 –190 mV VTRIP = 0.2V –30 –25 –20 VZC Zerocrossdetectionoffset 0 mV Wake-up 4.2 4.4 4.5 VUVLO V5IN UVLO thresholdvoltage V Shutdown 3.7 3.9 4.1 VOVP VDDQ OVP thresholdvoltage OVP detectvoltage 118% 120% 122% tOVPDLY VDDQ OVP propagationdelay With100 mV overdrive 430 ns VUVP VDDQ UVP thresholdvoltage UVP detectvoltage 66% 68% 70% tUVPDLY VDDQ UVP delay 1 ms tUVPENDLY VDDQ UVP enabledelay 1.2 ms VOOB OOB Thresholdvoltage 108% THERMAL SHUTDOWN Shutdown temperature(2) 140 TSDN Thermalshutdownthreshold °C Hysteresis(2) 10 (2) Ensuredby design.Not productiontested.

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www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 DEVICE INFORMATION RUK PACKAGE (TOP VIEW) PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. DRVH 14 O High-sideMOSFET gatedriveroutput. DRVL 11 O Low-sideMOSFET gatedriveroutput. GND 7 – Signalground. MODE 19 I ConnectresistortoGND toconfigureswitchingfrequency,controlmode and dischargemode. (See Table2) PGND 10 – Gate driverpower ground.R DS(on) currentsensinginput(+). PGOOD 20 O Powergood signalopen drainoutput.PGOOD goes highwhen VDDQ outputvoltageiswithinthetargetrange. ReferenceinputforVDDQ. Connecttothemidpointofa resistordividerfromVREF toGND. Add a capacitorforREFIN 8 I stableoperation. SW 13 I/O High-sideMOSFET gatedriverreturn.R DS(on) currentsensinginput(–). S3 17 I S3 signalinput.(See Table1) S5 16 I S5 signalinput.(See Table1) TRIP 18 I ConnectresistortoGND tosetOCL atVTRIP/8.Output10-μA currentatroom temperature,TC = 4700 ppm/°C. VBST 15 I High-sideMOSFET gatedriverbootstrapvoltageinput.Connecta capacitorfromtheVBST pintotheSW pin. VDDQSNS 9 I VDDQ outputvoltagefeedback.ReferenceinputforVTTREF. Alsoservesas power supplyforVTTREF. VLDOIN 2 I Power supplyinputforVTT LDO. ConnectVDDQ intypicalapplication. VREF 6 O 1.8-Vreferenceoutput. VTT 3 O VTT 2-A LDO output.Need toconnect10 μF orlargercapacitanceforstability. VTTGND 4 – Power groundforVTT LDO. VTTREF 5 O BufferedVTT referenceoutput.Need toconnect0.22μF orlargercapacitanceforstability. VTTSNS 1 I VTT outputvoltagefeedback. V5IN 12 I 5-V power supplyinputforinternalcircuitsand MOSFET gatedrivers. Thermal – – Thermalpad.ConnectdirectlytosystemGND planewithmultiplevias.pad Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7

15 VBST

12 V5IN

20 PGOOD

VREFIN +20% VDDQSNS

14 DRVH

11 DRVL

VREFIN –32% 16S5 Soft-Start NOC 8 R 6VREF R 7GND 17S3 5VTTREF 1VTTSNS

4 VTTGND

3 VTT

+ 2 VLDOIN 7 R R VTT Discharge VTTREF Discharge Mode Selection 15 /c63A

19 MODE

VREFIN +8/16 % VREFIN –8/16 % VDDQ Discharge V5OK 4.4 V/3.9 V UVP OVP G 1.8 V Σ D-CAP: Open, D-CAP2: Short TPS51916 SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM

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−50 −25 0 25 50 75 100 125 Junction Temperature (°C) OVP/UVP Threshold (%) OVP UVP −50 −25 0 25 50 75 100 125 Junction Temperature (°C) VDDQSNS Discharge Current (mA) −50 −25 0 25 50 75 100 125 Junction Temperature (°C) VLDOIN Suppy Current (µA) −50 −25 0 25 50 75 100 125 Junction Temperature (°C) TRIP Source Current (µA) 200 400 600 800 1000 −50 −25 0 25 50 75 100 125 Junction Temperature (°C) V5IN Suppy Current (µA) −50 −25 0 25 50 75 100 125 Junction Temperature (°C) V5IN Shutdown Current (µA) TPS51916 www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 TYPICAL CHARACTERISTICS Figure1.V5IN Supply Currentvs JunctionTemperature Figure2.V5IN Shutdown Currentvs JunctionTemperature Figure3.VLDOIN Supply Currentvs Junction Figure4.CurrentSense Currentvs JunctionTemperature Temperature Figure5.OVP/UVP Thresholdvs JunctionTemperature Figure6.VDDQSNS DischargeCurrentvs Junction Temperature Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9

Input Voltage (V) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 12 kΩ IVDDQ = 5 A 100 200 300 400 500 600 700 800 0 2 4 6 8 10 12 14 16 18 20 VDDQ Output Current (A) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 100 kΩ VIN = 12 V 200 300 400 500 600 700 800 6 8 10 12 14 16 18 20 22 Input Voltage (V) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 200 kΩ IVDDQ = 10 A 200 300 400 500 600 700 800 6 8 10 12 14 16 18 20 22 Input Voltage (V) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 1 kΩ IVDDQ = 5 A −50 −25 0 25 50 75 100 125 Junction Temperature (°C) VTT Discharge Current (mA) 200 300 400 500 600 700 800 6 8 10 12 14 16 18 20 22 Input Voltage (V) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 100 kΩ IVDDQ = 10 A TPS51916 SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure7.VTT DischargeCurrentvs JunctionTemperature Figure8.SwitchingFrequency vs InputVoltage Figure9.SwitchingFrequency vs InputVoltage Figure10.SwitchingFrequency vs InputVoltage Figure11.SwitchingFrequency vs InputVoltage Figure12.SwitchingFrequency vs Load Current

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1.45 1.46 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 6 8 10 12 14 16 18 20 22 Input Voltage (V) VDDQ Output Voltage (V) IVDDQ = 0 A IVDDQ = 20 A R MODE = 200 kΩ 0.730 0.735 0.740 0.745 0.750 0.755 0.760 0.765 0.770 −10 −5 0 5 10 VTTREF Current (mA) VTTREF Voltage (V) VVDDQ = 1.5 V 100 200 300 400 500 600 700 800 0 2 4 6 8 10 VDDQ Output Current (A) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 1 kΩ VIN = 12 V 1.45 1.46 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 0 2 4 6 8 10 12 14 16 18 20 VDDQ Output Current (A) VDDQ Output Voltage (V) R MODE = 200 kΩ VIN = 12 V 100 200 300 400 500 600 700 800 0 2 4 6 8 10 12 14 16 18 20 VDDQ Output Current (A) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 200 kΩ VIN = 12 V 100 200 300 400 500 600 700 800 0 2 4 6 8 10 VDDQ Output Current (A) Switching Frequency (kHz) VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V R MODE = 1 kΩ VIN = 12 V TPS51916 www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) Figure13.SwitchingFrequency vs Load Current Figure14.SwitchingFrequency vs Load Current Figure15.SwitchingFrequency vs Load Current Figure16. Load Regulation Figure17. LineRegulation Figure18.VTTREF Load Regulation Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11

0.560 0.570 0.580 0.590 0.600 0.610 0.620 0.630 0.640 VTT Current (A) VTT Voltage (V) VVDDQ = 1.2 V 100 0.001 0.01 0.1 1 10 100 VDDQ Output Current (A) Efficiency (%) VIN = 20 V VIN = 12 V VIN = 8 V VVDDQ = 1.5 V R MODE = 200 kΩ 0.710 0.720 0.730 0.740 0.750 0.760 0.770 0.780 0.790 VTT Current (A) VTT Voltage (V) VVDDQ = 1.5 V 0.635 0.645 0.655 0.665 0.675 0.685 0.695 0.705 0.715 VTT Current (A) VTT Voltage (V) VVDDQ = 1.35 V 0.650 0.655 0.660 0.665 0.670 0.675 0.680 0.685 0.690 0.695 −10 −5 0 5 10 VTTREF Current (mA) VTTREF Voltage (V) VVDDQ = 1.35 V 0.580 0.585 0.590 0.595 0.600 0.605 0.610 0.615 0.620 −10 −5 0 5 10 VTTREF Current (mA) VTTREF Voltage (V) VVDDQ = 1.2 V TPS51916 SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure19.VTTREF Load Regulation Figure20.VTTREF Load Regulation Figure21.VTT Load Regulation Figure22.VTT Load Regulation Figure23.VTT Load Regulation Figure24.Efficiency

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www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) Figure25. 1.5-VLoad TransientResponse Figure26. VTT Load TransientResponse Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13

10000 100000 1000000 10000000 −80 −60 −40 −20 −180 −135 −90 −45 135 180 Frequency (Hz) Gain (dB) Phase (°) Gain Phase IVTT = 1 A 100 1000 10000 100000 1000000 −80 −60 −40 −20 −180 −135 −90 −45 135 180 Frequency (Hz) Gain (dB) Phase (°) Gain Phase VIN = 12 V IVDDQ = 10 A 10000 100000 1000000 10000000 −80 −60 −40 −20 −180 −135 −90 −45 135 180 Frequency (Hz) Gain (dB) Phase (°) Gain Phase IVTT = −1 A TPS51916 SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure29.1.5-VSoft-StopWaveforms (Tracking Figure30.1.5-VSoft-StopWaveforms (Non-Tracking Discharge) Discharge) Figure31.VDDQ Bode Plot Figure32.VTT Bode Plot(Sink) Figure33.VTT Bode Plot(Source)

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700 /c109s400 /c109s 1.4 ms VREF VDDQ PGOOD UDG-10137 TPS51916 www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012

APPLICATION INFORMATION

VDDQ Switch Mode Power Supply Control The TPS51916 supportstwo SMPS controlarchitectures,D-CAP ™ mode and D-CAP2 ™ mode. Both control modes do notrequirecomplex externalcompensationnetworksand aresuitablefordesignswithsmallexternal components counts.The D-CAP ™ mode providesfasttransientresponsewithappropriateamount ofequivalent seriesresistance(ESR) on theoutputcapacitors.The D-CAP2 ™ mode isdedicatedfora configurationwithvery low ESR outputcapacitorssuch as multi-layerceramiccapacitors(MLCC). For thebothmodes, an adaptiveon- timecontrolscheme isused toachievepseudo-constantfrequency.The TPS51916 adjuststheon-time(tON ) to be inverselyproportionaltotheinputvoltage(VIN)and proportionaltotheoutputvoltage(VVDDQ ).Thismakes a switchingfrequencyfairyconstantoverthevariationofinputvoltageatthesteadystatecondition.These control modes and switchingfrequenciesareselectedby theMODE pindescribedinTable2. VREF and REFIN, VDDQ Output Voltage The partprovidesa 1.8-V,±0.8% accurate,voltagereferencefrom VREF. This outputhas a 300-μA (max) currentcapabilitytodrivetheREFIN inputvoltagethrougha voltagedividercircuit.A capacitorwitha valueof 0.1-μF orlargershouldbe attachedclosetotheVREF terminal. The VDDQ switch-modepower supply(SMPS) outputvoltageisdefinedby REFIN voltage,withinthe range between 0.7V and 1.8V,programmed by theresister-dividerconnectedbetween VREF and GND. (See External Components Selectionsection.)A few nano faradsof capacitancefrom REFIN to GND isrecommended for stableoperation. Soft-Startand Powergood Providea voltagesupplyto VIN and V5IN beforeassertingS5 to high.TPS51916 providesintegratedVDDQ soft-startfunctionsto suppress in-rushcurrentat start-up.The soft-startis achievedby controllinginternal referencevoltagerampingup.Figure34 shows thestart-upwaveforms.The switchingregulatorwaitsfor400μs afterS5 assertion.The MODE pinvoltageisreadinthisperiod.A typicalVDDQ ramp up durationis700μs. TPS51916 has a powergood open-drainoutputthatindicatestheVDDQ voltageiswithinthetargetrange.The targetvoltagewindow and transitiondelaytimesofthePGOOD comparatorare ±8% (typ)and 1-ms delayfor assertion(lowto high),and ±16% (typ)and 330-ns delayforde-assertion(highto low)duringrunning.The PGOOD start-updelayis2.5ms afterS5 isassertedtohigh.Note thatthetimeconstantwhichiscomposed of theREFIN capacitorand a resistordividerneeds tobe shortenough toreachthetargetvaluebeforePGOOD comparatorenabled. Figure34. TypicalStart-upWaveforms Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15

SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com Power StateControl The TPS51916 has two inputpins,S3 and S5, toprovidesimplecontrolscheme ofpower state.AllofVDDQ, VTTREF and VTT areturnedon atS0 state(S3=S5=high).InS3 state(S3=low,S5=high),VDDQ and VTTREF voltagesarekepton whileVTT isturnedoffand leftathighimpedance state(high-Z).The VTT outputfloatsand does notsinkorsourcecurrentinthisstate.InS4/S5 states(S3=S5=low),allofthethreeoutputsareturnedoff and dischargedtoGND accordingtothedischargemode selectedby MODE pin.Each statecode representsas follow;S0 = fullON, S3 = suspend toRAM (STR),S4 = suspend todisk(STD),S5 = softOFF. (See Table1) Table1.S3/S5 Power StateControl STATE S3 S5 VREF VDDQ VTTREF VTT S0 HI HI ON ON ON ON S3 LO HI ON ON ON OFF(High-Z) S4/S5 LO LO OFF OFF(Discharge) OFF(Discharge) OFF(Discharge) MODE Pin Configuration The TPS51916 readstheMODE pinvoltagewhen theS5 signalisraisedhighand storesthestatusina register. A 15-μA currentissourcedfromtheMODE pinduringthistimetoreadthevoltageacrosstheresistorconnected between thepinand GND. Table2 shows resistorvalues,correspondingcontrolmode, switchingfrequencyand dischargemode configurations. Table2.MODE Selection RESISTANCE BETWEEN CONTROL SWITCHINGMODE NO. DISCHARGE MODEMODE AND GND (kΩ) MODE FREQUENCY (kHz) 7 200 400 Tracking 6 100 300 D-CAP ™ 5 68 300 4 47 400 Non-tracking 3 33 500 2 22 670 D-CAP2 ™ 1 12 670 Tracking 0 1 500 DischargeControl In S4/S5 state,VDDQ, VTT, and VTTREF outputsare dischargedbased on the respectivedischargemode selectedabove. The trackingdischargemode dischargesVDDQ outputthroughthe internalVTT regulator transistorsenablingquickdischargeoperation.The VTT outputmaintainstrackingoftheVTTREF voltageinthis mode. (PleaserefertoFigure29)After4 ms oftrackingdischargeoperation,themode changes tonon-tracking discharge.The VDDQ outputmust be connectedto the VLDOIN pin in thismode. The non-trackingmode dischargesthe VDDQ and VTT pins using internalMOSFETs thatare connected to correspondingoutput terminals.The non-trackingdischargeisslow compared withthe trackingdischargedue to the lowercurrent capabilityoftheseMOSFETs. (PleaserefertoFigure30)

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/c61 /c163/c112 /c180 /c180 SW OUT f1f 2 ESR C 3 PWM VDDQSNS REFIN VREF Control Logic and DriverR1 DRVH DRVL 1.8 V VIN Lx ESR COUT RLOAD UDG-10136 High-Side MOSFET Low-Side MOSFET VDDQ TPS51916 www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 D-CAP ™ Mode Figure35 shows a simplifiedmodel ofD-CAP ™ mode architecture. Figure35. SimplifiedD-CAP ™ Model The VDDQSNS voltageiscompared withREFIN voltage.The PWM comparatorcreatesa setsignaltoturnon the high-sideMOSFET. The gainand speed of the comparatorishighenough to maintainthe voltageat the beginningof each on-cycle(orthe end of each off-cycle)to be substantiallyconstant.The DC outputvoltage monitoredatVDDQ may have lineregulationdue torippleamplitudethatslightlyincreasesas theinputvoltage increase.The D-CAP ™ mode offersflexibilityon outputinductanceand capacitanceselectionswithease-of-use withoutcomplex feedbackloopcalculationand externalcomponents.However, itdoes requirea sufficientlevel of ESR thatrepresentsinductorcurrentinformationforstableoperationand good jitterperformance.Organic semiconductorcapacitor(s)orspecialtypolymercapacitor(s)arerecommended. The requirementforloopstabilityissimpleand isdescribedinEquation1. The 0-dB frequency,f0 definedin Equation1,isrecommended tobe lowerthan1/3oftheswitchingfrequencytosecureproperphase margin. where

• ESR istheeffectiveseriesresistanceoftheoutputcapacitor
• C OUT isthecapacitanceoftheoutputcapacitor
• fsw isswitchingfrequency (1) Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17

/c180 /c179/c180 OUT SW X V ESR 20 mVf L VVDDQSNS VREFIN (1) (2) tON tOFF Slope (2) Jitter 20 mV Slope (1) Jitter UDG-10139 VREFIN +Noise TPS51916 SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com Jitterisanotherattributecaused by signal-to-noiseratioof the feedbacksignal.One of the major factorsthat determinejitterperformancein D-CAP ™ mode is the down-slope angle of the VDDQSNS ripplevoltage. Figure36 shows,inthesame noisecondition,thatjitterisimprovedby making theslopeanglelarger. Figure36. RippleVoltageSlope and JitterPerformance Fora good jitterperformance,use therecommended down slopeofapproximately20 mV perswitchingperiodas shown inFigure36 and Equation2. where

• VOUT istheVDDQ outputvoltage
• LX istheinductance (2)

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/c40 /c41 /c45/c61 /c180 /c180 /c180 IN OUT OUT LOAD(LL) X IN SW V V V 1I 2 L V f /c180/c61 /c163/c112 /c180 /c180 /c180 C C SW X OUT R C ff 2 G L C 3 Control Logic and Driver LX COUT RLOAD UDG -10198 CC 1 VIN 1 1 SW DRVH DRVL VDDQSNS G REFIN VREF + 1.8 V RC 1 CC 2 RC 2 TPS51916 VDDQ Σ PWM TPS51916 www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 D-CAP2 ™ Mode Operation Figure37 shows simplifiedmodel ofD-CAP2 ™ architecture. Figure37. SimplifiedModulatorUsing D-CAP2 ™ Mode The D-CAP2 ™ mode intheTPS51916 includesan internalfeedbacknetworkenablingtheuse ofverylow ESR outputcapacitor(s)such as multi-layerceramiccapacitors.The roleoftheinternalnetworkistosense theripple component oftheinductorcurrentinformationand combine itwithvoltagefeedbacksignal.Using R C1 =R C2 ≡R C and C C1 =C C2 ≡C C ,0-dB frequencyoftheD-CAP2 ™ mode isgivenby Equation3.Itisrecommended thatthe0- dB frequency(f0)be lowerthan1/3oftheswitchingfrequencytosecuretheproperphase margin where

• G isgainoftheamplifierwhichamplifiestheripplecurrentinformationgeneratedby thecompensation circuit (3) The typicalG valueis0.25,and typicalR C C C timeconstantvaluesfor500 kHz and 670 kHz operationare23 µs and 14.6µs,respectively. Forexample,when fSW =500 kHz and LX=1 µH, C OUT shouldbe largerthan88 µF. When selectingthe capacitor,pay attentionto itscharacteristics.For MLCC use X5R or betterdielectricand considerthederatingofthecapacitanceby bothDC biasand AC bias.When deratingby DC biasand AC bias are 80% and 50%, respectively,the effectivederatingis40% because 0.8 x 0.5 = 0.4.The capacitanceof specialtypolymer capacitorsmay change depending on the operatingfrequency.Consult capacitor manufacturersforspecificcharacteristics. Light-LoadOperation Inauto-skipmode, theTPS51916 SMPS controllogicautomaticallyreducesitsswitchingfrequencytoimprove light-loadefficiency.To achievethisintelligence,a zerocrossdetectioncomparatorisused topreventnegative inductorcurrentby turningoffthelow-sideMOSFET. Equation4 shows theboundaryloadconditionofthisskip mode and continuousconductionoperation. (4) Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19

0.22 /c109F AGND TPS51916 SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com VTT and VTTREF TPS51916 integratestwo high performance,low-drop-outlinearregulators,VTT and VTTREF, to provide completeDDR2/DDR3/DDR3L power solutions.The VTTREF has a 10-mA sink/sourcecurrentcapability,and tracks½ ofVDDQSNS with±1% accuracyusingan on-chip½ divider.A 0.22-μF (orlarger)ceramiccapacitor must be connectedclosetotheVTTREF terminaltoensurestableoperation.The VTT respondsquicklytotrack VTTREF within±40 mV atallconditions,and thecurrentcapabilityis2 A forbothsinkand source.A 10-μF (or larger)ceramiccapacitor(s)need tobe connectedclosetotheVTT terminalforstableoperation.To achievetight regulationwithminimum effectofwiringresistance,a remotesensingterminal,VTTSNS, shouldbe connectedto the positivenode of VTT outputcapacitor(s)as a separatetracefrom the high-currentlineto the VTT pin. (PleaserefertotheLayoutConsiderationssectionfordetails.) When VTT isnotrequiredinthedesign,followingtreatmentisstronglyrecommended.

• ConnectVLDOIN toVDDQ.
• TieVTTSNS toVTT, and remove capacitorsfromVTT tofloat.
• ConnectVTTGND toGND.
• SelectMODE2, 3,4 or5 shown inTable2 (SelectNon-trackingdischargemode).
• Maintaina 0.22-µF capacitorconnectedatVTTREF.
• Pulldown S3 toGND with1-kΩ resistance. Figure38. ApplicationCircuitWhen VTT IsNot Required VDDQ Overvoltageand UndervoltageProtection The TPS51916 setstheovervoltageprotection(OVP) when VDDQSNS voltagereachesa level20% (typ)higher thantheREFIN voltage.When an OV eventisdetected,thecontrollerchanges theoutputtargetvoltageto0 V. ThisusuallyturnsoffDRVH and forcesDRVL tobe on.When theinductorcurrentbeginstoflowthroughthe low-sideMOSFET and reachesthenegativeOCL, DRVL isturnedoffand DRVH isturnedon,fora minimum on- time. Aftertheminimum on-timeexpires,DRVH isturnedoffand DRVL isturnedon again.Thisactionminimizesthe outputnode undershootdue toLC resonance.When theVDDQSNS reaches0 V, thedriveroutputislatchedas DRVH off,DRVL on. VTTREF and VTT are turnedoffand dischargedusing the non-trackingdischarge MOSFETs regardlessofthetrackingmode.

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/c40 /c41 /c40 /c41 /c230 /c246 /c230 /c246 /c45/c231 /c247 /c231 /c247/c61 /c43 /c61 /c43 /c180 /c180/c231 /c247 /c231 /c247 /c180/c232 /c248 /c232 /c248 IND(ripple)OCTRIP OCTRIP IN OUT OUT OCL X SW INDS on DS on IV V V V V 1I R 2 R 2 L f V /c61 /c180 TRIP OCTRIP TRIP IV R 8 TPS51916 www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 The undervoltageprotection(UVP) latchissetwhen theVDDQSNS voltageremainslowerthan68% (typ)ofthe REFIN voltagefor1 ms or longer.In thisfaultcondition,the controllerlatchesDRVH low and DRVL low and dischargesthe VDDQ, VTT and VTTREF outputs.UVP detectionfunctionisenabled after1.2 ms of SMPS operationtoensurestartup. To releasethe OVP and UVP latches,toggleS5 or adjustthe V5IN voltagedown and up beyond the undervoltagelockoutthreshold. VDDQ Out-of-BoundOperation When theoutputvoltagerisesto8% above thetargetvalue,theout-of-boundoperationstarts.Duringtheout-of- bound condition,thecontrolleroperatesinforcedPWM-only mode. Turningon thelow-sideMOSFET beyond the zeroinductorcurrentquicklydischargestheoutputcapacitor.Duringthisoperation,thecycle-by-cyclenegative overcurrentlimitisalsovalid.Once theoutputvoltagereturnstowithinregulationrange,thecontrollerresumes toauto-skipmode. VDDQ OvercurrentProtection The VDDQ SMPS has cycle-by-cycleovercurrentlimitingprotection.The inductorcurrentismonitoredduringthe off-stateusingthelow-sideMOSFET R DS(on),and thecontrollermaintainstheoff-statewhen theinductorcurrent islargerthantheovercurrenttriplevel.The currentmonitorcircuitinputsarePGND and SW pinsso thatthose shouldbe properlyconnectedtothesourceand drainterminalsoflow-sideMOSFET. The overcurrenttriplevel, VOCTRIP ,isdeterminedby Equation5,where R TRIP isthevalueoftheresistorconnectedbetween theTRIP pin and GND, and ITRIP isthecurrentsourcedfrom theTRIP pin.ITRIP is10 μA typicallyatroom temperature,and has 4700ppm/°C temperaturecoefficienttocompensate thetemperaturedependency ofthelow-sideMOSFET R DS(on). (5) Because thecomparisonisdone duringtheoff-state,VOCTRIP setsthevalleyleveloftheinductorcurrent.The loadcurrentOCL level,IOCL ,can be calculatedby consideringtheinductorripplecurrentas shown inEquation6. where

• IIND(ripple)isinductorripplecurrent (6) Inan overcurrentcondition,thecurrenttotheloadexceeds thecurrenttotheoutputcapacitor,thustheoutput voltagetendstofalldown. Eventually,itcrossestheundervoltageprotectionthresholdand shutsdown. VTT OvercurrentProtection The LDO has an internallyfixedconstantovercurrentlimitingof3-A (typ)forbothsinkand sourceoperation. V5IN UndervoltageLockout Protection The TPS51916 has a 5-V supplyundervoltagelockoutprotection(UVLO) threshold.When theV5IN voltageis lowerthanUVLO thresholdvoltage,typically3.9V, VDDQ, VTT and VTTREF are shutoff.Thisisa non-latch protection. Thermal Shutdown The TPS51916 includesan internaltemperaturemonitor.Ifthetemperatureexceeds thethresholdvalue,140°C (typ),VDDQ, VTT and VTTREF areshutoff.The stateofVDDQ isopen,and thatofVTT and VTTREF arehigh impedance (high-Z)atthermalshutdown.The dischargefunctionsofalloutputsaredisabled.Thisisa non-latch protectionand the operationisrestartedwithsoft-startsequence when the devicetemperatureisreduced by 10°C (typ). Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21

/c180 /c179/c180 OUT SW X V ESR 20 mVf L /c163/c112 /c180 /c180 SW OUT

2 ESR C 3

/c40 /c41 /c40 /c41 /c40 /c41 /c230 /c246 /c230 /c246 /c45/c231 /c247/c180 /c45 /c180 /c180 /c231 /c247 /c231 /c247/c231 /c247 /c180 /c180/c232 /c248/c232 /c248/c61 IN OUT OUT OCL DS(on) X SW IN TRIP TRIP V V V8 I R2 L f V R I /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c45 /c180/c180/c61 /c43 /c180 /c180 /c180 IN OUT OUTmaxTRIP TRIP IND peak SW INDS on max V V VR I 1I 8 R L f V /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c45 /c180 /c45 /c180 /c61 /c180 /c61 /c180 /c180 /c180 IN OUT OUT IN OUT OUTmax max X SW IN O SW ININD ripple max max max V V V V V V1 3L I f V I f V /c40 /c41 /c61 /c230 /c246 /c231 /c247 /c231 /c247 /c231 /c247 /c45/c180/c230 /c246/c231 /c247 /c231 /c247/c45/c231 /c247 /c231 /c247/c231 /c247 /c232 /c248/c232 /c248 IND ripple OUT R1R2 1.8 1I ESR V 2 TPS51916 SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com ExternalComponents Selection The externalcomponents selectionissimpleinD-CAP ™ mode. 1.DETERMINE THE VALUE OF R1 AND R2 The outputvoltageisdeterminedby thevalueofthevoltage-dividerresistor,R1 and R2 as shown inFigure35. R1 isconnectedbetween VREF and REFIN pins,and R2 isconnectedbetween theREFIN pinand GND. Setting R1 as 10-kΩ isa good startingpoint.DetermineR2 usingEquation7. (7) 2.CHOOSE THE INDUCTOR The inductancevalueshouldbe determinedtoyielda ripplecurrentofapproximately¼ to½ ofmaximum output current.Largerripplecurrentincreasesoutputripplevoltageand improvesthe signal-to-noiseratioand helps stableoperation. (8) The inductorneeds a low directcurrentresistance(DCR) toachievegood efficiency,as wellas enough room above peak inductorcurrentbeforesaturation.The peak inductorcurrentcan be estimatedinEquation9. (9) 3.CHOOSE THE OCL SETTING RESISTANCE, R TRIP CombiningEquation5 and Equation6,R TRIP can be obtainedusingEquation10. (10) 4.CHOOSE THE OUTPUT CAPACITORS D-CAP ™ Mode Organicsemiconductorcapacitor(s)orspecialtypolymercapacitor(s)arerecommended. DetermineESR tomeet small signalstabilityand recommended ripplevoltage.A quick referenceis shown in Equation 11 and Equation12. (11) (12) D-CAP2 ™ Mode Determineoutputcapacitancetomeet smallsignalstabilityas shown inEquation13.

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6 VREF

0.1 /c109F 10 /c109F 10 /c109F C10 10 /c109F VIN

8 V to 20 V

0.1 /c109F R7 0 /c87 L1 0.56 /c109H FDMS8670AS FDMS8670AS C11 330 /c109F VDDQ_GND PGNDR5 49 k/c87 10 k/c87 0.1 /c109F 10 nF 0.22 /c109F 10 /c109F C12 10 /c109F PGND VTT

0.75 V/2 A

0.75 V VTTGND 100 k/c87 R2 200 k /c87 R3 36 k/c87 V5IN 4.5 V to 5.5 V FDMS8680 VDDQ

1.5 V/20 A

/c180 /c163/c112 /c180 /c180 /c180 C C SW X OUT R C f

2 G L C 3

www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 where

• R C ×C C timeconstantis23 µs for500 kHz operation(or14.6µs for670 kHz operation)
• G = 0.25 (13) TPS51916 ApplicationCircuits Figure39. DDR3, D-CAP ™ 400-kHz ApplicationCircuit,TrackingDischarge Table3.DDR3, D-CAP ™ 400-kHz ApplicationCircuit,ListofMaterials REFERENCE QTY SPECIFICATION MANUFACTURE PART NUMBERDESIGNATOR C8, C9, C10 3 10 µF,25 V TaiyoYuden TMK325BJ106MM C11 1 330 µF,2V,6 m Ω Panasonic EEFSX0D331XE L1 1 0.56µH, 21 A,1.56m Ω Panasonic ETQP4LR56WFC Q1 1 30 V,35 A,8.5m Ω Fairchild FDMS8680 Q2, Q3 2 30 V,42 A,3.5m Ω Fairchild FDMS8670AS Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23

0.1 /c109F 10 /c109F 10 /c109F VIN 0.1 /c109F R7 0 /c87 L1 1 /c109H FDMS8670AS C10 4 x 47 /c109F VDDQ_GND PGNDR5 49.9 k/c87 10 k/c87 0.1 /c109F 10 nF 0.22 /c109F 10 /c109F C12 10 /c109F PGND VTT 0.75 V VTTGND 100 k/c87 R2 1 k /c87 R3 36 k/c87 V5IN 4.5 V to 5.5 V FDMS8680 VDDQ

1.5 V/10 A

SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com Figure40. DDR3, DCAP-2 ™ 500-kHz ApplicationCircuit,TrackingDischarge Table4.DDR3, DCAP-2 ™ 500-kHz ApplicationCircuit,ListofMaterials REFERENCE QTY SPECIFICATION MANUFACTURE PART NUMBERDESIGNATOR C8, C9 2 10 µF,25 V TaiyoYuden TMK325BJ106MM C10 4 47 µF,6.3V TDK C2012X5R0J476M L1 1 1 µH, 18.5A,2.3m Ω NEC Tokin MPC1055L1R0C Q1 1 30 V,35 A,8.5m Ω Fairchild FDMS8680 Q2 1 30 V,42 A,3.5m Ω Fairchild FDMS8670AS

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12 VOUT

0.22 /c109F VTTREF 10 /c109F 10 nF 0.1 /c109F VTT VTTGND VLDOIN 1 /c109F PGND AGND TPS51916 www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 Layout Considerations Certainissuesmust be consideredbeforedesigninga layoutusingtheTPS51916. Figure41. DC/DC ConverterGround System

• VIN capacitor(s),VOUT capacitor(s)and MOSFETs arethepower components and shouldbe placedon one sideofthePCB (solderside).Othersmallsignalcomponents shouldbe placedon anotherside(component side).At leastone innersystem GND planeshouldbe inserted,inordertoshieldand isolatethesmallsignal tracesfromnoisypower lines.
• Allsensitiveanalogtracesand components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF and TRIP shouldbe placedaway from high-voltageswitchingnodes such as SW, DRVL, DRVH or VBST to avoid coupling.Use internallayer(s)as system GND plane(s)and shieldfeedbacktracefrom power tracesand components.
• The DC/DC converterhas severalhigh-currentloops.The areaoftheseloopsshouldbe minimizedinorderto suppressgeneratingswitchingnoise. – The most importantlooptominimizetheareaofisthepathfromtheVIN capacitor(s)throughthehighand low-sideMOSFETs, and back tothenegativenode oftheVIN capacitor(s).Connect thenegativenode of theVIN capacitor(s)and thesourceofthelow-sideMOSFET as closeas possible.(Refertoloop#1 of Figure41) – The second importantloop is the path from the low-sideMOSFET through inductorand VOUT capacitor(s),and back tosourceofthelow-sideMOSFET. Connect thesourceofthelow-sideMOSFET and negativenode ofVOUT capacitor(s)as closeas possible.(Refertoloop#2 ofFigure41) – The thirdimportantloop isof gate drivingsystem forthe low-sideMOSFET. To turnon the low-side MOSFET, highcurrentflowsfromV5IN capacitorthroughgatedriverand thelow-sideMOSFET, and back tonegativenode ofthecapacitor.To turnoffthelow-sideMOSFET, highcurrentflowsfrom gateofthe low-sideMOSFET throughthegatedriverand PGND pin,and back tosourceofthelow-sideMOSFET. Connect negativenode of V5IN capacitor,sourceof the low-sideMOSFET and PGND pinas closeas possible.(Refertoloop#3 ofFigure41)
• Connect negativenodes oftheVTTREF outputcapacitor,VREF capacitorand REFIN capacitorand bottom- sideresistanceof VREF voltage-dividerto GND pinas closeas possible.The negativenode of the VTT Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25

SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 www.ti.com outputcapacitor(s),VTTGND, GND and PGND pinsshouldbe connectedto system GND planenear the deviceas shown inFigure41.

• Because the TPS51916 controlsoutputvoltagereferringto voltageacross VOUT capacitor,VDDQSNS shouldbe connectedto the positivenode of VOUT capacitorusingdifferenttracefrom thatforVLDOIN. Remember thatthissensingpotentialisthereferencevoltageofVTTREF. Avoidany noisegenerativelines. GND pinreferstothenegativenode ofVOUT capacitor.
• Connect the overcurrentsettingresistorfrom TRIP pinto GND pinand make the connectionsas closeas possibletothedevicetoavoidcouplingfroma high-voltageswitchingnode.
• Connect the frequencyand mode settingresistorfrom MODE pin to GND pin ground,and make the connectionsas closeas possibletothedevicetoavoidcouplingfroma high-voltageswitchingnode.
• Connectionsfromgatedriverstotherespectivegateofthehigh-sideorthelow-sideMOSFET shouldbe as shortas possibletoreducestrayinductance.Use 0.65mm (25mils)orwidertraceand via(s)ofatleast0.5 mm (20mils)diameteralongthistrace.
• The PCB tracedefinedas SW node,whichconnectstothesourceofthehigh-sideMOSFET, thedrainofthe low-sideMOSFET and thehigh-voltagesideoftheinductor,shouldbe as shortand wideas possible.
• VLDOIN shouldbe connectedto VOUT withshortand wide traces.An inputbypass capacitorshouldbe placedas closeas possibletothepinwithshortand wide connections.The negativenode ofthecapacitor shouldbe connectedtosystemGND plane.
• The outputcapacitorforVTT shouldbe placedclosetothepinswitha shortand wide connectioninorderto avoidadditionalESR and/orESL ofthetrace.
• VTTSNS shouldbe connectedtothepositivenode oftheVTT outputcapacitor(s)usinga separatetracefrom the high-currentpower line.When remote sensingisrequiredattachthe outputcapacitor(s)at thatpoint. Also,itisrecommended tominimizeany additionalESR and/orESL ofground tracebetween GND pinand theoutputcapacitor(s).
• Consideraddinga low pass filter(LPF)atVTTSNS incase theESR oftheVTT outputcapacitor(s)islarger than2 m Ω.
• In orderto effectivelyremove heat from the package,preparea thermallandand solderto the package thermalpad.Wide traceofthecomponent-sidecopper,connectedtothisthermalland,helpsheatspreading. Numerous viaswitha 0.3-mm diameterconnectedfrom the thermallandto the internal/solder-sideground plane(s)shouldbe used tohelpdissipation.The thermallandcan be connectedtoeitherAGND orPGND but isrecommended tobe connectedtoPGND, thesystemGND plane(s),whichhas betterheatradiation.

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www.ti.com SLUSAE1D –DECEMBER 2010–REVISED JUNE 2012 Changes from RevisionB (AUGUST 2011)toRevisionD Page Copyright© 2010–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27

www.ti.com 23-Aug-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS51916RUKR ACTIVE WQFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS51916RUKT ACTIVE WQFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 22-Aug-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51916RUKR WQFN RUK 20 3000 367.0 367.0 35.0 TPS51916RUKT WQFN RUK 20 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 22-Aug-2012 Pack Materials-Page 2

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