MP9840GL-P

MP9840 MPS | Alldatasheet

Document overview

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Technical content

36V, 3.5A, Low IQ, Synchronous Step-Down Converter

DESCRIPTION

The MP9840 is a high-frequency, synchronous, rectified, step -down, switch- mode converter with built -in power MOSFETs. It offers a very compact solution that achieves 3.5A of continuous output current with excellent load and line regulati on over a wide 3.3V to 36V input supply range. The switching frequency can be programmed or synchronized to an external clock in the range of 350kHz to 2.5MHz. The synchronous operation and ultra- low 14μA sleep mode quiescent current provide high efficiency o ver the output current load range, allowing the MP9840 to be used in a variety of step- down applications in automotive input environment s and battery -powered applications. Peak-current-mode operation provides fast transient response and eases loop stabilization. The excellent low dropout performance allows the MP9840 to be use d in high duty cycle applications. Full protection features include over -current protection (OCP), short-circuit protection (SCP), and thermal shutdown. An open- drain power good (PG) signal indicates when the output is within 10% of its nominal voltage. The MP9840 is available in a space -saving QFN-16 (3mmx4mm) package.

FEATURES

• 2μA Low Shutdown Supply Current
• 14μA No-Load Quiescent Current
• Internal 125mΩ High-Side and 55mΩ Low- Side MOSFET
• 350kHz to 2.5MHz Programmable Switching Frequency
• Power Good (PG) Output
• External Soft Start (SS)
• 80ns Minimum On Time
• Selectable Forced CCM and AAM
• Hiccup Over-Current Protection (OCP)
• Available in a QFN-16 (3mmx4mm) Package

APPLICATIONS

• Automotive Systems
• Industrial Power Systems All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VOUT SW EN VIN BSTPGND MP9840 AGND PHASE SS FREQ SYNC FB VCC PG BIAS VIN GND OFF ON MP9840 Rev. 1.01 www.MonolithicPower.com 1 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER

ORDERING INFORMATION

Part Number* Package Top Marking MP9840GL QFN-16 (3mmx4mm) See Below * For Tape & Reel, add suffix –Z (e.g. MP9840GL–Z) TOP MARKING MP: MPS prefix Y: Year code W: Week code 9840: First four digits of the part number LLL: Lot number PACKAGE REFERENCE TOP VIEW PHASE VIN SW 4PGND 13141516 AGNDSSFBFREQ 5 6 7 8 EN SYNC PG BIAS PGND SW BST VCC QFN-16 (3mmx4mm) MP9840 Rev. 1.01 www.MonolithicPower.com 2 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25°C) (2) Recommended Operating Conditions Operating junction temp. (TJ) ...-40°C to +125°C Thermal Resistance (3) θJA θJC NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temper ature T J(MAX), the junction- to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)- TA)/ θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Measured on JESD51-7, 4-layer PCB. MP9840 Rev. 1.01 www.MonolithicPower.com 3 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER

ELECTRICAL CHARACTERISTICS

VIN = 12V, VEN = 2V, TJ = -40°C to +125°C (4), unless otherwise noted. Typical values are at T J = +25°C. Parameter Symbol Condition Min Typ Max Units VIN quiescent current IQ VFB = 0.85V, no load, no switching, TJ = +25°C 14 21 µA VFB = 0.85V, no load, no switching 29 VIN shutdown current ISHDN VEN = 0V 2 6 µA VIN under-voltage lockout threshold rising INUVRISING 2.4 2.8 3.2 V VIN under-voltage lockout threshold hysteresis INUVHYS 150 mV EN rising threshold VEN_RISING 0.9 1.05 1.2 V EN threshold hysteresis VEN_HYS 120 mV Feedback reference voltage VREF 784 800 816 mV TJ = 25°C 792 800 808 mV HS switch on resistance RON_HS VBST - VSW = 5V 125 165 mΩ LS switch on resistance RON_LS 55 85 mΩ Switching frequency FSW RFREQ = 180kΩ or from sync clock 400 475 550 kHz RFREQ = 82kΩ or from sync clock 850 1000 1150 kHz RFREQ = 27kΩ or from sync clock 2250 2500 2750 kHz Minimum on time (5) TON_MIN 80 ns SYNC input low voltage VSYNC_LOW 0.4 V SYNC input high voltage VSYNC_HIGH 1.8 V Current limit ILIMIT_HS Duty cycle = 40% 4.6 5.6 7.4 A ZCD current IZCD 0.1 A Reverse current limit ILIMIT_REVERSE 3 A Switch leakage current ISW_LKG 0.01 1 µA Soft-start current ISS VSS = 0.8V 5 10 15 µA VCC regulator VCC 5 V VCC load regulation ICC = 5mA 3.5 % Thermal shutdown (5) TSD 170 °C Thermal shutdown hysteresis (5) TSD_HYS 20 °C PG rising threshold (VFB/VREF) PGRISING VFB rising 85 90 95 % VFB falling 105 110 115 PG falling threshold (VFB/VREF) PGFALLING VFB falling 79 84 89 % VFB rising 113.5 118.5 123.5 % PG deglitch timer TPG_DEGLITCH PG from low to high 30 µs PG from high to low 50 µs PG output voltage low VPG_LOW ISINK = 2mA 0.2 0.4 V NOTE: 4) Not tested in production and guaranteed by over-temperature correlation. 5) Not tested in production and guaranteed by design and characterization. MP9840 Rev. 1.01 www.MonolithicPower.com 4 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL CHARACTERISTICS VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 5 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 6 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 7 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 8 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 9 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 10 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 11 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 12 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 13 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted. MP9840 Rev. 1.01 www.MonolithicPower.com 14 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER PIN FUNCTIONS Pin # QFN-16 (3mmx4mm) Name Description 1 PHASE Selectable in-phase or 180° out-of-phase of SYNC input. Pull PHASE high to be in-phase. Pull PHASE low to be 180° out-of-phase.

2 VIN

Input supply. VIN supplies power to a ll of the internal control circuitr ies and the power switch connected to SW. Place a decoupling capacitor to ground close to VIN to minimize switching spikes. 3, 10 SW Switch node. SW is the output of the internal power switch. 4, 9 PGND Power ground. PGND is the reference ground of the power device and requires careful consideration during PCB layout. For best results, connect PGND with copper pours and vias. 5 EN Enable. Pull EN below the specified threshold to shut the chip down. Pull EN above the specified threshold to enable the chip.

6 SYNC

Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the internal oscillator frequency to the external clock. The external clock should be at least 250kHz larger than the RFREQ set frequency. SYNC can also be used to select forced CCM or AAM. Drive SYNC high before the chip starts up to choose forced CCM; drive SYNC low or leave SYNC floating to choose AAM. 7 PG Power good output. The output of PG is an open drain.

8 BIAS

Bias input. Connect BIAS to an external power supply (5V ≤ VBIAS ≤ 18V) to reduce power dissipation and increase efficiency. If not in use, float BIAS or connect BIAS to ground. 11 BST Bootstrap. BST is the positive power supply for the high-side MOSFET driver connected to SW. Connect a bypass capacitor between BST and SW. 12 VCC Bias supply. VCC supplies power to the internal control circuit and gate drivers. A decoupling capacitor (≥1µF) to ground is required close to VCC. 13 AGND Analog ground. AGND is the reference ground of the logic circuit. 14 SS Soft-start input. Place a capacitor from SS to AGND to set the soft-start period. The MP9840 sources 10µA from SS to the soft -start capacitor during start-up. As the SS voltage rises, the feedback threshold voltage increases to limit inrush current durin g start-up. 15 FB Feedback input. Connect FB to the center point of the external resistor divider. The feedback threshold voltage is 0.8V. Place the resistor divider as close to FB as possible. Avoid placing vias on the FB traces. 16 FREQ Switching frequency program. Connect a resistor from FREQ to ground to set the switching frequency. MP9840 Rev. 1.01 www.MonolithicPower.com 15 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER BLOCK DIAGRAM Oscillator PLL Reference Error Amplifier Control Logic, OCP, OTP, BST Refresh FB PGND SW BST VIN EN PG 90%xVREF ISW SS Vref VCCVFB VFB VCC VCC VCC Regulator Ireverse BIAS FREQ SYNC PHASE AGND VC 460kΩ 52pF 0.2pF VCC VREF VFB 110%xVREF Logic Figure 1: Functional Block Diagram MP9840 Rev. 1.01 www.MonolithicPower.com 16 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER PHASE is used when two or more MP9840 devices are in parallel with the same SYNC clock. Pulling PHASE high forces the MP9840 to operate in- phase of the SYNC clock. Pulling PHASE low forces the device to be 180° out -of- phase of the SYNC clock. By setting different voltages for PHASE, two devices can operate 180° out -of-phase to reduce the total input current ripple, so a s maller input bypass capacitor can be used (see Figure 4) . The PHASE rising threshold is about 2.5V with a 400mV hysteresis. SYNC CLK SW1 SW2 t SW1, 2 has a 180o phase shift SW1: Phase high SW2: Phase low Figure 4: In-Phase and 180° Out-of-Phase Soft Start (SS) Soft start (SS) is implemented to prevent the converter output voltage from overshooting during start -up. When the soft -start period begins, an internal current source charg es the external soft-start capacitor. When the soft-start voltage (SS) is lower than the internal reference (REF), SS overrides REF, so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. C SS can be calculated with Equation (2): ×= µ SS REF SS SS C (nF) V (V)t (ms) I ( A) (2) Where CSS is the external SS capacitor, V REF is 0.8V, and I SS is the internal 10 μA SS charge current. SS can be used for tracking and sequencing. Pre-Bias Start-Up During start-up, if FB is greater than SS - 150mV, which means the output has a pre-bias voltage, then neither the HS -FET nor LS-FET turn on until SS is higher than FB. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from running away thermally. When the silicon die temperature is higher than its upper threshold, the power MOSFETs are shut down. When the temperature is lower than its lower threshold, t hermal shutdown is removed and the chip is enabled again. Current Comparator and Current Limit The power MOSFET current is accurately sensed via a current sense MOSFET. The current is then fed to the high- speed current comparator for current-mode control purposes . The current comparator takes this sensed current as one of its inputs. When the HS-FET is turned on, the comparator is first blanked until the end of the turn -on transition to avoid noise. Then the compar ator compares the power switch current with V COMP. When the sensed current is higher than V COMP, the comparator outputs low to turn off the HS -FET. The maximum current of the internal power MOSFET is limited cycle-by-cycle internally. Hiccup Protection When the output is shorted to ground, causing the output voltage to drop below 55% of its nominal output, the IC is shut down momentarily and begins discharging the soft - start capacitor. The IC restarts with a full soft start when the soft -start capacitor is fully discharged. This hiccup process is re peated until the fault is removed. Start-Up and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current , and then the internal regulat or is enabled. The regulator provides a stable supply for the rest of the circuitries. While the internal supply rail is up, an internal timer holds the power MOSFET off for about 50µs to blank any start-up glitches. When the soft-start block is enabled, the SS output is held low to ensure that the rest of the circuitries are ready before slowly ramping up. MP9840 Rev. 1.01 www.MonolithicPower.com 19 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER Three events can shut down the chip: EN low, VIN low, and thermal shutdown. In the shutdown procedure, the signaling path is blocked first to avoid an y fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to t his shutdown command, but its charging path is disabled. Power Good (PG) Output The MP9840 includes an open- drain power good (PG) output that indicates whether the regulator output is within ±10% of its nominal output range. When the output voltage moves outside of this range, the PG output is pulled to ground. MP9840 Rev. 1.01 www.MonolithicPower.com 20 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER

APPLICATION INFORMATION

Setting the Output Voltage The external resistor divider connected to FB sets the output voltage (see Figure 5). RFB1 VoutFB MP9840 RFB2 Figure 5: Feedback Network Choose RFB1 to be around 40 kΩ. RFB2 can then be calculated with Equation (3): 10.8V V RR OUT FB1 FB2 = (3) Table 1 lists the recommended feedback resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) RFB1 (kΩ) RFB2 (kΩ) Selecting the Inductor A 1µH to 10µH inductor with a DC current rating at least 25% higher than the maximum load current is recommended for most applications. For higher efficiency, choose an inductor with a lower DC resistance. A larger -value inductor results in less ripple current and a lower output ripple voltag e, but also has a larger physical size, hig her series resistance, and lower saturation current. A good rule for determining the inductor value is to allow the inductor ripple current to be approximately 30% of the maximum load current. The inductance value can then be calculated with Equation (4): = ×−×∆ OUT OUT SW L IN VVL (1 )fI V (4) Where ∆IL is the peak -to-peak inductor ripple current. Choose the inductor ripple current to be approximately 30% o f the maximum load current. The maximum inductor peak current can be calculated with Equation (5): = + ×− × OUT OUT LP LOAD SW IN VVI I (1 )2f L V (5) Selecting the Input Capacitor The input current to the step- down converter is discontinuous and therefore requires a capacitor to supply AC current to the converter while maintaining the D C input voltage. For the best performance, use low ESR capacitors. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, use a 4.7µF to 10µF capacitor. It is strongly recommended to use another lower-value capacitor (e.g.: 0.1µF) with a small package size (0603) to absorb high - frequency switching noise. Place the small er capacitor as close to VIN and GND as possible. Since C IN absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (6): = × ×− OUT OUT CIN LOAD IN IN VVI I (1 )VV (6) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (7): = LOAD CIN II 2 (7) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high -quality ceramic capacitor (e.g. : 0.1μF) as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at the input. MP9840 Rev. 1.01 www.MonolithicPower.com 21 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER PCB Layout Guidelines (6) Efficient PCB layout , is critical for stable operation, especially for the input capacitor placement. A four -layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 8 and follow the guidelines below. 1. Place the symmetric input capacitors as close to VIN and GND as possible. 2. Use a large ground plane to connect to PGND directly. 3. Add vias near PGND if the bottom layer is a ground plane. 4. Ensure that the high-current paths at GND and VIN have short, direct, and wide traces. 5. Place the ceramic input capacitor s, especially the small package size (0603) input bypass capacitor , as close to V IN and PGND as possible to minimize high - frequency noise. 6. Keep the connection of the input capacitor and VIN as short and wide as possible. 7. Place the VCC capacitor as close to VCC and GND as possible. 8. Route SW and BST away from sensitive analog areas such as FB. 9. Place the feedback resistors close to the chip to ensure that the trace connect ing to FB is as short as possible. 10. Use multiple vias to connect the power planes to the internal layers. NOTE: 6) The recommended PCB layout is based on Figure 9. Top Layer Inner Layer 1 Inner Layer 2 Bottom Layer Figure 8: Recommended PCB Layout MP9840 Rev. 1.01 www.MonolithicPower.com 23 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.

MP9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER

PACKAGE INFORMATION

QFN-16 (3mmx4mm) SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-220. 4) DRAWING IS NOT TO SCALE. TOP VIEW RECOMMENDED LAND PATTERN PIN 1 ID MARKING PIN 1 ID INDEX AREA PIN 1 ID 0.15x45°TYP. 0.15x45° NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP9840 Rev. 1.01 www.MonolithicPower.com 27 1/23/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.