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24V, 3A, 500kHz, High-Efficiency, Synchronous, Step-Down Converter MP92325 Rev. 1.0 www.MonolithicPower.com 1 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. The Future of Analog IC Technology
DESCRIPTION
The MP92325 is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built-in, internal power MOSFETs. It offers a very compact solution that achieves 3A of continuous output current with excellent load and line regulation over a wide input supply range. The MP92325 uses synchronous mode operation for higher efficiency over the output current load range. Current-mode operation provides a fast transient response and eases loop stabilization. Full protection features include over-current protection (OCP) and thermal shutdown. The MP92325 requires a minimum number of readily available, standard, external components and is available in a space-saving, 8-pin TSOT23 package.
FEATURES
Wide 4.5V to 24V Operating Input Range 90m Ω/40mΩ Low RDS(ON) Internal Power MOSFETs Low Quiescent Current High-Efficiency Synchronous Mode Operation Fixed 500kHz Switching Frequency Frequency Sync from 200kHz to 2MHz External Clock Power Save Mode at Light Load Internal Soft Start Power Good Indicator Over-Current Protection (OCP) and Hiccup Thermal Shutdown Output Adjustable from 0.8V Available in an 8-Pin TSOT-23 Package
APPLICATIONS
Notebook Systems and I/O Power Digital Set-Top Boxes Flat-Panel Televisions and Monitors All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 0. 1µF 40.2k 12.7k 4.9µH 44µF 0.1µFC1 22µF 3.3V/3A Rt 33k MP92325 100k
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 2 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking MP92325GJ TSOT23-8 AKE * For Tape & Reel, add suffix –Z (e.g. MP92325GJ–Z) PACKAGE REFERENCE PG IN SW GND FB VCC EN/SYNC BST TOP VIEW TSOT23-8 ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25°C) (2) RECOMMENDED OPERATING CONDITIONS (3) Operating junction temp (TJ). ... -40°C to +125°C Thermal Resistance (4) θJA θJC NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 3 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Supply current (shutdown) I IN V EN = 0V 5.5 μA Supply current (quiescent) I q V EN = 2V, VFB = 1V 130 180 240 μA HS switch on resistance HS RDS-ON V BST-SW = 5V 90 m Ω LS switch on resistance LS RDS-ON V CC = 5V 40 m Ω Switch leakage SW LKG V EN = 0V, VSW = 12V 1 μA Current limit(5) I LIMIT Duty cycle = 40% 4.5 5.5 6.5 A Oscillator frequency f SW V FB = 750mV 420 500 620 kHz Foldback frequency f FB V FB = 200mV 0.5 f SW Maximum duty cycle D MAX V FB = 750mV 90 95 % Minimum on time(5) T ON MIN 60 ns Sync frequency range f SYNC 0.2 2 MHz Feedback voltage V FB T A = 25°C 783 791 799 mV Feedback current I FB V FB = 820mV 10 50 nA EN rising threshold V EN RISING 1.2 1.4 1.6 V EN hysteresis V EN HYS 80 150 220 mV EN input current I EN VEN = 2V 1.5 2 2.5 μA VEN = 0 0 50 nA EN turn off delay EN Td-off 6 10 14 μs Power good rising threshold PG VTH-Hi 0.9 V FB Power good falling threshold PG VTH-LO 0.85 V FB Power good delay PG Td 40 μs Power good sink current capability VPG Sink 1mA 0.4 V Power good leakage current I PG-LEAK 1 μA VIN under-voltage lockout threshold rising INUVVth 3.7 3.9 4.1 V VIN under-voltage lockout threshold hysteresis INUVHYS 550 650 750 mV VCC regulator V CC 4.65 4.9 5.15 V VCC load regulation I CC = 5mA 0 1 3 % Soft-start period T SS 0.8 1.5 2.2 ms Thermal shutdown(5) 150 °C Thermal hysteresis(5) 20 °C NOTE: 5) Guaranteed by design.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 4 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 4.9μH, TA = 25°C, unless otherwise noted.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 5 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 4.9μH, TA = 25°C, unless otherwise noted. VOUT/AC 10mV/div. VIN/AC 200mV/div. VSW 5V/div. IL 1A/div. VOUT/AC 20mV/div. VIN/AC 200mV/div. VSW 5V/div. IL 2A/div. VOUT 2V/div. VIN 5V/div. VSW 5V/div. IL 1A/div. VOUT 2V/div. VIN 5V/div. VSW 5V/div. IL 2A/div. VOUT 2V/div. VEN 5V/div. VSW 5V/div. IL 1A/div. VOUT 2V/div. VEN 5V/div. VSW 5V/div. IL 2A/div. VOUT 2V/div. VEN 5V/div. VSW 5V/div. IL 2A/div. VOUT 2V/div. VIN 5V/div. VSW 5V/div. IL 2A/div. VOUT 2V/div. VIN 5V/div. VSW 5V/div. IL 2A/div.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 6 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) VIN = 12V, VOUT = 3.3V, L = 4.9µH, TA = 25°C, unless otherwise noted. VOUT 2V/div. VPG 5V/div. VSW 5V/div. IL 5A/div. VOUT 2V/div. VPG 5V/div. VSW 5V/div. IL 5A/div. VOUT 2V/div. VPG 5V/div. VSW 5V/div. IL 5A/div. VOUT 2V/div. VEN 5V/div. VPG 5V/div. IL 1A/div. VOUT 2V/div. VEN 5V/div. VPG 5V/div. IL 2A/div. VOUT 2V/div. VEN 5V/div. VPG 5V/div. IL 2A/div. VOUT 2V/div. VEN 5V/div. VPG 5V/div. IL 2A/div. VOUT/AC 200mV/div. IOUT 1A/div. VOUT 2V/div. VEN 5V/div. VSW 5V/div. IL 2A/div.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 7 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. PIN FUNCTIONS Package Pin # Name Description 1 PG Power good output. The output of PG is an open drain. PG is pulled up to VCC by an external resistor when the out put voltage exceeds 90% of the normal voltage. There is a 40µs delay between the detection that FB ≥ 90% and PG going high. 2 IN Supply voltage. IN supplies power to the internal MOSFET and regulator. The MP92325 operates from a +4.5V to +24V input rail. Requires a low ESR, low-inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to IN and connect it with wide PCB traces and multiple vias. 3 SW Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to VIN by the high-side switch during the PWM dut y cycle on time. The inductor current drives SW negative during the off time. The on resistan ce of the low-side switch and the internal body diode fixes the negative voltage. Connect using wide PCB traces and multiple vias.
4 GND
System ground. GND is the reference ground of the regulated output voltage and requires careful consideration during PCB layout. Connect GND to PCB ground with coppers and vias. 5 BST Bootstrap. A capacitor and a 20 Ω resistor connected between SW and BST are required to form a floating supply across the high-side switch driver.
6 EN/SYNC
Set EN/SYNC = 1 to enable the MP92325. An external clock can be applied to EN/SYNC to change the switching frequency. For automat ic start-up, connect EN to VIN with a 100kΩ resistor. 7 VCC Bias supply. Decouple with a 0.1 μF-0.22μF capacitor. The capacitance should be no more than 0.22μF. 8 FB Feedback. An external resistor divider from t he output to GND tapped to FB sets the output voltage. To prevent a current-limit runaway during a short-circuit fault condition, the frequency foldback comparator lowers the oscillator frequency when the FB voltage is below 400mV.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 8 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. BLOCK DIAGRAM 50pF 1MEG6.5V BST RSEN IN Oscillator VCC Regulator Bootstrap Regulator VCC Currrent Sense Amplifer VCCCurrent Limit Comparator Error Amplifier Ref Reference EN/SYNC FB PG SW GND LS Driver HS Driver Comparator On Time Control Logic Control 1pF 400k Figure 1: Functional Block Diagram
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 10 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. The EN/SYNC logic high voltage should be higher than 2V. The EN/SYNC logic low voltage should be lower than 400mV. The EN/SYNC logic high pulse width must be less than 1.6µs; otherwise, the internal clock may turn on the high-side MOSFET again. The EN/SYNC logic low pulse width must be less than 6µs; otherwise the MP92325 may shut down. Power Good Indicator The MP92325 uses an open drain for the power good indicator. When FB is higher than 90% of the regulation voltage, PG is pulled up to VCC by the external resistor. If the FB voltage drops down to 85% of the regulation voltage, PG is pulled down to ground by an internal MOSFET. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at an insufficient supply voltage. The MP92325’s UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 3.9V, while its falling threshold is consistent at 3.25V. Internal Soft Start (SS) The soft start is implemented to prevent the converter output voltage from overshooting during start-up. When the chip starts, the internal circuitry generates a soft-start (SS) voltage that ramps up from 0V. The soft-start period lasts until the voltage on the soft-start capacitor exceeds the reference voltage of 0.8V. At this point, the reference voltage takes over. The soft-start time is set to around 1.5ms internally. Over-Current Protection (OCP) and Hiccup The MP92325 uses a cycle-by-cycle over- current limit when the inductor current peak value exceeds the set current limit threshold. The output voltage begins to drop until FB is below the under-voltage (UV) threshold, typically 50% below the reference. Once UV is triggered, the MP92325 enters hiccup mode to restart the part periodically. This protection mode is especially useful when the output is dead-shorted to ground. The average short- circuit current is greatly reduced to alleviate thermal issues and protect the regulator. The MP92325 exits hiccup mode once the over- current condition is removed. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, the entire chip shuts down. When the temperature is below its lower threshold (typically 130°C), the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. The UVLO rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by V IN through D1, R5, C5, L1, and C2 (see Figure 4). If V IN-VSW is more than 5V, U1 regulates M1 to maintain a 5V BST voltage across C5. Figure 4: Internal Bootstrap Charging Circuit Start-Up and Shutdown If both V IN and EN/SYNC are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating a stable reference voltage and current, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: EN/SYNC low, V IN low, and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. V COMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 11 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
APPLICATION INFORMATION
SETTING THE OUTPUT VOLTAGE The external resistor divider is used to set the output voltage (see the Typical Application on page 1). The feedback resistor (R1) also sets the feedback loop bandwidth with the internal compensation capacitor. R2 can then be calculated with Equation (1): OUT V 0.8V (1) The T-type network (see Figure 5) is highly recommended. Rt FB Cf VOUT Figure 5: T-Type Network Table 1 lists the recommended T-type resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) R1 (k Ω) R2 (kΩ) Rt (k Ω) L (µH) Cf (µF) 1 20.5 76.8 100 1.8 15 1.2 20.5 39.2 100 1.8 15 1.8 40.2 31.6 56 3.3 15 2.5 40.2 18.7 56 3.3 15 3.3 40.2 12.7 33 4.9 15 5 40.2 7.5 33 4.9 15 Selecting the Inductor A 1µH-to-22µH inductor with a DC current rating at least 25% percent higher than the maximum load current is recommended for most applications. For the highest efficiency, the inductor’s DC resistance should be less than 15m Ω. For most designs, the inductance value can be derived from Equation (2): OUT IN OUT IN L OSC V( V V )L VI f Where ∆IL is the inductor ripple current. Choose the inductor current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (3): III L LOAD)MAX(L (3) Under light-load conditions below 100mA, a larger inductance is recommended for improved efficiency. Selecting the Input Capacitor The input current to the step-down converter is discontinuous and therefore requires a capacitor to supply AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 22µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (4): IN OUT IN OUTLOAD1C V V1V VII (4) The worse case condition occurs at VIN = 2VOUT, shown in Equation (5): II LOAD 1C (5) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, a small, high-quality ceramic capacitor (i.e.: 0.1μF) should be placed as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at the input. The input voltage ripple caused by capacitance can be estimated with Equation (6): LOAD OUT OUT IN INSI N IV VV1 fC 1V V
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 12 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Selecting the Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred for keeping the output voltage ripple low. The output voltage ripple can be estimated with Equation (7): OUT OUT OUT ESR S1 I N S VV 1V1 R fL V 8 fC 2 Where L1 is the inductor value and R ESR is the equivalent series resistance (ESR) value of the output capacitor. For ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated with Equation (8): OUT OUT OUT 2 INS1 VV∆V1 V8f L C 2 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (9): OUT OUT OUT ESR INS1 VV∆V1 R fL V The characteristics of the output capacitor also affect the stability of the regulation system. The MP92325 can be optimized for a wide range of capacitance and ESR values. External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of the external BST diode are: VOUT is 5V or 3.3V Duty cycle is high: D = IN OUT V V > 65% In these cases, an external BST diode is recommended to be placed between VCC and BST (see Figure 6). Figure 6: Optional External Bootstrap Diode Added to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is recommended to be 0.1μF - 1μF.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP92325 Rev. 1.0 www.MonolithicPower.com 13 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. PCB Layout Guidelines (6) Efficient PCB layout is critical for stable operation. For best results, refer to Figure 7 and follow the guidelines below. 1. Keep the connection of the input ground and GND as short and wide as possible. 2. Keep the connection of the input capacitor and IN as short and wide as possible. 3. Ensure that all feedback connections are short and direct. 4. Place the feedback resistors and compensation components as close to the chip as possible. 5. Route SW away from sensitive analog areas such as FB. NOTE: 6) The recommended layout is based on Figure 8: Typical Application Circuit on page 14. Figure 7: Sample Board Layout Design Example Table 2 is a design example following the application guidelines for the specifications below. Table 2: Design Example VIN 19V VOUT 5V IO 3A The detailed application schematics are shown in Figure 8 through Figure 13. The typical performance and circuit waveforms are shown in the Typical Performance Characteristics section. For more device applications, please refer to the related evaluation board datasheets.
MP92325 – 24V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP92325 Rev. 1.0 www.MonolithicPower.com 16 3/24/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.