MP8020 MPSIND | Alldatasheet
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IEEE 802.3af/at/bt-Compliant, PoE, Powered Device Interface MP8020 Rev. 1.0 MonolithicPower.com 1 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.
DESCRIPTION
The MP8020 is an IEEE 802.3af/at/bt- compliant, Power over Ethernet (PoE), powered device (PD). The device supports all the functions of IEEE 802.3af/at/bt, including detection, 5-event classification, input current IN) control, and an internal 100V hot-swap MOSFET. The MP8020 provides configurable inrush current limiting during start-up and operation current limiting when the internal MOSFET is fully turned on. The GATE1 driver supports the use of an external low on resistance (R DS(ON)) MOSFET for high-power design. A high power good (PG) signal enables the use of a downstream DC/DC converter. The MP8020 also provides automatic maintain power signature functionality under light loads. An auxiliary power input detector (AUX) and GATE2 driver provide a smooth power switch from the power-sourcing equipment (PSE) to an auxiliary wall adapter with low power loss. The MP8020 also features a built-in detection resistor, thermal protection, and a wide input under-voltage lockout (UVLO) hysteresis. The MP8020 is available in a QFN-18 (3mmx5mm) package.
FEATURES
Compliant with 802.3af/at/bt Specifications Internal Detection Resistor Supports Up to 71.3W Powered Device (PD) Operation Internal Hot-Swap MOSFET for ≤51W Design External MOSFET with GATE1 for >51W Design Auxiliary Power Supply from >8.8V Adapter GATE2 N-Channel MOSFET Driver for Adapter Supply Configurable Current Limit Automatic Maintain Power Signature PG and Allocated Power Type Indicators 150°C Over-Temperature Protection (OTP) Available in a QFN-18 (3mmx5mm) Package
APPLICATIONS
IEEE 802.3 af/at/bt-Compliant Devices Security Cameras Video and VoIP Phones WLAN Access Points Internet of Things (IoT) Devices Pico Base Stations All MPS parts are lead-free, halogen-free, and adhere to the RoH S directive. For MPS green status, please visit the MPS website u nder Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION From PSE MP8020 GATE1 SRC GATE2VADP VDD VOUT AUX PRI CLSB CLSA TYP1 BT TYP2 ILIM DUTY R_MPS GND R1 R2 From Adapter SENSE PG D1 C1 PSE Start-Up CH2: VDD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH4: BT/TYP1/TYP2 20V/div. 200ms/div.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 2 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number Package Top Marking MSL Rating MP8020GQV* Q F N - 1 8(3mmx5mm) See Below 1 * For Tape & Reel, add suffix -Z (e.g. MP8020GQV-Z). TOP MARKING MP: MPS prefix Y: Year code W: Week code 8020: First four digits of the part number LLL: Lot number PACKAGE REFERENCE TOP VIEW 987 17 16 QFN-18 (3mmx5mm)
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 3 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 VDD Positive power supply terminal from the Power over Ethernet (PoE) input power rail. 2 GND Negative power supply terminal. 3 GATE2 External N-channel MOSFET GATE driver for the adapter power supply. 4 VADP Positive power supply terminal from the adapter.
5 AUX
Adapter power input detector pin. The AUX pin configures the adapter’s auxiliary power under-voltage lockout (UVLO) voltage. Pull down AUX internally to GND via a resistor. If this pin is not used, pull it to GND externally. 6 R_MPS Automatic maintain power signature load resistor connection . The R_MPS pin generates a 24V output pulse when the maintain power signature function is triggered. 7 ILIM I n t e r n a l h o t - s w a p M O S F E T c u r r e n t l i m i t c o n f i g u r a t i o n. See the Hot-Swap MOSFET and Current Limit section on page 17 for more details. 8 DUTY Automatic maintain power signature output duty setting pin. See the Automatic Maintain Power Signature section on page 19 for more details.
9 PRI
Power-sourcing equipment (PSE) power and adapter power priority setting pin. Pull up this pin internally to the internal 5V power source via a re sistor. If PRI is low, then the PSE power source has a higher priority. 10 CLS A Power class signature pin. CLSA is used during the first two class events. 11 CLSB Power class signature pin. CLSB is used during the third class event and all subsequent class events. 12 BT PSE type indicator. BT is an open-drain output. 13 TYP2 Allocated PSE power type indicator. TYP2 is an open-drain output. 14 TYP1 Allocated PSE power type indicator. TYP1 is an open-drain output. 15 PG Power good (PG) indicator. PG is an open-drain output. Pull this pin active high. 16 SRC Hot-swap MOSFET source pin. SRC is the power output f rom both the internal and external hot-swap MOSFETs. 17 GATE1 External, parallel N-channel MOSFET GATE driver for the PSE power supply. 18 SENSE External MOSFET current-sense pin. If not used, connect this pin to VDD.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 4 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) VDD, SENSE, SRC, TYP1, TYP2, PG, AUX, Continuous power dissipation (TA = 25°C) (2)….. Recommended Operating Conditions (3) Operating junction temp (T Thermal Resistance θJA θJC QFN-18 (3mmx5mm) Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature, T J (MAX), the junction-to- ambient thermal resistance, θ JA, and the ambient temperature, T A. The maximum allowable continuous powe r dissipation at any ambient temperature is calculated by P D ( M A X ) = ( TJ ( M A X ) - TA) / θ JA. Exceeding the maximum allowable power dissipation can produce an excessive die temperature, which may cause the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on the EV8020-QV-00A, a 1oz, 2-laye r (63mmx63mm) PCB. 5) The value of θ JA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51-7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 5 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VDD = 54V, TJ = -40°C to +125°C (6), typical values are tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Detection Detection on V DET-ON V DD rising 1 1.4 V Detection off V DET-OFF V DD rising 10.1 11 V Bias current I BIAS VDD = 10.1V, not in mark event, measure ISUPPLY 1 2 μ A Detection resistance R DET VDD from 1.5V to 10.1V, calculate with ΔV / ΔI 24.1 25 26.1 kΩ Classification Classification stability time Stable output voltage (VOUT) from VCL-ON to CLSA or CLSB 0 . 4 1 m s CLSA and CLSB class voltage (VCLASS) output voltage VCLSA 13V < VDD < 21V, 1mA < ICLASS < 44mA 1.11 1.16 1.21 V VCLSB Classification current for CLSA and CLSB ICLASS Measure input current, 13 ≤ VDD ≤ 21V, guaranteed by VCLSA and VCLSB RCLASS = 578Ω, 13 ≤ VDD ≤ 21V 1.8 2 2.4 mA RCLASS = 110Ω, 13 ≤ VDD ≤21V 9.9 10.55 11.3 RCLASS = 62Ω, 13 ≤ VDD ≤ 21V 17.7 18.7 19.8 RCLASS = 41.2Ω, 13 ≤ VDD ≤21V 26.6 28.15 29.7 RCLASS = 28.7Ω, 13 ≤ VDD ≤21V 38.2 40.4 42.6 Long first class event tLCE Determine type 3 and type 4 PoE from trigger VCL-ON 76 81.5 87 ms Classification lower threshold V CL-ON Regulator turns on, V DD rising 12 12.5 13 V Classification lower threshold hysteresis VCL-L-HYS Low threshold hysteresis 1.3 1.5 1.7 V Classification upper threshold VCL-OFF Regulator turns off, V DD rising 21 22 23 V Classification upper threshold hysteresis VCL-H-HYS High threshold hysteresis 0.5 V Mark event reset threshold V MARK-L 4 . 5 5 5 . 5 V Max mark event voltage V MARK-H 10.5 11 11.5 V Mark event current I MARK 0 . 5 1 . 1 2 m A Mark event resistance R MARK 2-point measurement at 5.5V and 10.1V, calculate with ΔV / ΔI 1 2 k Ω IC supply current during classification IIN-CLASS VDD = 17.5V, float CLSA and CLSB 180 300 μA Class leakage current I LEAKAGE VCLSA = VCLSB = 0V, VDD = 57V, test both CLSA and CLSB 1 μ A
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 6 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD = 54V, TJ = -40°C to +125°C (6), typical values are tested at TJ = 25°C, unless otherwise noted. Parameter S ymbol Condition Min T yp Max Units Under-Voltage Lockout (UVLO) VDD turn-on threshold V DD_R V DD rising 37 38.5 40 V VDD turn-off threshold V DD_F V DD falling 30 31.5 33 V VDD UVLO hysteresis V DD_HYS 5 7 V IC supply current during operation IIN No load and no R_MPS resistor 1 1.5 mA Input leakage current V DD = 29.5V 150 250 μ A Hot-Swap MOSFET and Current Limit Internal MOSFET on resistance RDS(ON) I SRC = 500mA 0.35 Ω Leakage current I SRC-LK VDD = 57V, VSRC = 0V, AUX = high, PRI = high 1 1 5 μ A ILIM detection period 270 μs ILIM detection current 130 165 180 μ A ILIM voltage threshold 0.9A settin g voltage range 0 . 8 V 1.6A settin g voltage range1 2 . 2 V Internal MOSFET current limit ILIMIT VSRC drops from VDD, VDD -V SRC = 1V ILIM = 0V 0.75 0.9 1.05 A Connect ILIM to GND via a 7.15kΩ resistor 1.4 1.6 1.8 A Internal MOSFET inrush limit IINRUSH VSRC ramps up from low to high, VDD -V SRC = 1V ILIM = 0V 70 130 190 m A Connect ILIM to GND via a 7.15kΩ resistor 170 230 290 mA Inrush current termination I TERM V SRC rising, ITERM / IINRUSH 75% I INRUSH Inrush to operation mode delay tDELAY 80 90 100 ms Current foldback threshold V SRC falling, VDD -V SRC 8.2 10 11.8 V Foldback deglitch time (7) VSRC falling to inrush current foldback 1 m s GATE1 source current V GATE1 -V SRC = 4V 10 μ A GATE1 sink current V GATE1 -V SRC = 4V 30 μ A GATE1 max driving voltage 6 V External MOSFET current limit V DD - VSENSE 2 2 2 6 3 0 m V SENSE leakage current V SENSE = VDD = 54V 0.1 μ A PG, BT, TYP1, TYP2 Output low voltage I SINK = 1mA 0.2 0.4 V Leakage current Lo gic = high, connect to 57V 1 μ A
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 7 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD = 54V, TJ = -40°C to +125°C (6), typical values are tested at TJ = 25°C, unless otherwise noted. Parameter S ymbol Condition Min T yp Max Units Maintain Power Signature Automatic maintain power signature current enable threshold I PORT-MPS Load current drops 36 mA Automatic maintain power signature current threshold hysteresis Load current rises to disable the maintain power signature current again 1 0 m A R_MPS output voltage 1mA to 20m A 23 24 25 V Type 1 and type 2 power sourcing equipment (PSE), R_MPS output duty cycle D u t y 3 7 On period 75 85 95 ms Off period 115 140 165 ms Type 3 and type 4 PSE, R_MPS output duty cycle with DUTY short to GND D u t y 6 On period 14 16 18 ms Off period 210 250 290 ms Type 3 and type 4 PSE, R_MPS output duty cycle with DUTY to GND via a 7.15kΩ resistor D u t y 11.5 % On period 26 31 36 ms Off period 200 235 270 ms Type 3 and type 4 PSE, R_MPS output duty cycle with DUTY floating Duty 17 % On period 39 45 52 ms Off period 190 221 260 ms External MOSFET voltage drop control threshold V DS = VSENSE - VSRC 2 6 m V DUTY detection current 130 165 180 μ A DUTY detection period 130 μs DUTY voltage threshold 6% dut y setting voltage range 0 . 8 V 11.5% duty setting voltage range 1 2.2 V 17% dut y setting voltage range2 . 5 V Adapter Supply VADP UVLO rising threshold ADPUV-R 7.8 8.3 8.8 V VADP UVLO falling threshold ADPUV-F 6 . 5 7 7 . 5 V AUX high threshold voltage V AUX-H 1.92 2 2.08 V AUX threshold hysteresis V AUX-HYS 0.15 V AUX leakage current VAUX = 2V 1 μ A VAUX = 57V 2.5 μ A GATE2 source current V GATE2 -V ADP = 4V 20 μ A GATE2 sink current V GATE2 -V ADP = 4V 200 μ A GATE2 max driving voltage GATE2 to VADP 6 V GATE2 turn-on threshold VADP - VSRC voltage after adapter supply is enabled 0 0.45 V
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 8 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD = 54V, TJ = -40°C to +125°C (6), typical values are tested at TJ = 25°C, unless otherwise noted. Parameter S ymbol Condition Min T yp Max Units Power Priority PRI input high voltage 2 V PRI input low voltage 0.4 V PRI internal pull up resistor Pull up to internal 5V V CC 1 mΩ Thermal Shutdown Thermal shutdown temperature TSD 150 °C Thermal shutdown hysteresis THYS 2 0 ° C Notes: 6) Guaranteed by over-temperature correlation. Not tested in pr oduction. 7) Guaranteed by characterizati on. Not tested in production.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 9 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VDD = 54V, VADP = 24V, TA = 25°C, unless otherwise noted. -50 0 50 100 150 VDD UVLO (V) TJ (°C) VDD UVLO vs. Junction Temperature Rising Falling 120 180 240 300 -50 0 50 100 150 IINRUSH (mA) TJ (°C) Inrush Current Limit vs. Junction Temperature ILIM=7.15K ILIM=GND -50 0 50 100 150 ITERM (%) TJ (°C) Inrush Current Termination vs. Junction Temperature 100 -50 0 50 100 150 tDELAY (mS) TJ (°C) Inrush to Operation Mode Delay vs. Junction Temperature 0.4 0.8 1.2 1.6 -50 0 50 100 150 ILIMIT (A) TJ (°C) Operation Current Limit vs. Junction Temperature ILIM=7.15K ILIM=GND 0.5 1.5 -50 0 50 100 150 IIN (mA) TJ (°C) IC Supply Current during Operation vs. Junction Temperature
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 10 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VDD = 54V, VADP = 24V, TA = 25°C, unless otherwise noted. -50 0 50 100 150 RDET (kΩ) TJ (°C) Detection Resistance vs. Junction Temperature 0.2 0.4 0.6 0.8 -50 0 50 100 150 RDS(ON) (Ω) TJ (°C) Internal MOSFET On Resistance vs. Junction Temperature 1.08 1.12 1.16 1.2 1.24 -50 0 50 100 150 VCLASS (V) TJ (°C) Class Voltage vs. Junction Temperature 20.5 21.5 22.5 -50 0 50 100 150 VCL-OFF (V) TJ (°C) Class Upper Threshold vs. Junction Temperature Upper_OFF Upper_ON 9.5 10.5 11.5 12.5 -50 0 50 100 150 VCL-ON (V) TJ (°C) Class Lower Threshold vs. Junction Temperature Lower_ON Lower_OFF 4.6 4.8 5.2 5.4 -50 0 50 100 150 VMARK-L (V) TJ (°C) Mark Event Reset Threshold vs. Junction Temperature
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 11 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VDD = 54V, VADP = 24V, TA = 25°C, unless otherwise noted. 0.9 1.1 1.2 1.3 -50 0 50 100 150 IMARK (mA) TJ (°C) Mark Event Current vs. Junction Temperature -50 0 50 100 150 RMARK (kΩ) TJ (°C) Mark Event Resistance vs. Junction Temperature 6.5 7.5 8.5 -50 0 50 100 150 VADP UVLO (V) TJ (°C) VADP UVLO vs. Junction Temperature Rising Falling 1.6 1.7 1.8 1.9 2.1 2.2 -50 0 50 100 150 AUX UVLO (V) TJ (°C) AUX UVLO vs. Junction Temperature Rising Falling -50 0 50 100 150 EXTERNAL MOSFET ILIMIT (mV) TJ (°C) External MOSFET Current Limit vs. Junction Temperature -50 0 50 100 150 IPORT-MPS (mA) TJ (°C) Automatic Maintain Power Signature Current Enable Threshold vs. TJ
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 12 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VDD = 54V, VADP = 24V, TA = 25°C, unless otherwise noted. Steady State IOUT = 0A Steady State IOUT = 1.35A CH2: V DD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH4: IVDD 50mA/div. CH2: V DD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH4: IVDD 1A/div. 100ms/div. 100ms/div. Start-Up through VDD IOUT = 0A Start-Up through VDD IOUT = 0.1A CH2: V DD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH2: V DD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. 40ms/div. 40ms/div. Shutdown through VDD IOUT = 0A Shutdown through VDD IOUT = 1.35A CH2: VDD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH4: IVDD 50mA/div. CH2: VDD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH4: IVDD 2A/div. 100ms/div. 100ms/div.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 13 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD = 54V, VADP = 24V, TA = 25°C, unless otherwise noted. Load Transient IOUT = 0A to 0.675A, IRAMP = 50mA/µs Load Transient IOUT = 0.675A to 1.35A, IRAMP = 50mA/µs CH1: V OUT 20V/div. CH4: IOUT 1A/div. CH1: V OUT 20V/div. CH4: IOUT 1A/div. 4ms/div. 4ms/div. PSE Start-Up Class 1 PSE Start-Up Class 4 CH1: VDD 20V/div. CH2: BT 20V/div. CH3: TYP1 20V/div. CH4: TYP2 20V/div. CH1: VDD 20V/div. CH2: BT 20V/div. CH3: TYP1 20V/div. CH4: TYP2 20V/div. 200ms/div. 200ms/div. PSE Start-Up Class 6 PSE Start-Up Class 8 CH1: V DD 20V/div. CH2: BT 20V/div. CH3: TYP1 20V/div. CH4: TYP2 20V/div. CH1: V DD 20V/div. CH2: BT 20V/div. CH3: TYP1 20V/div. CH4: TYP2 20V/div. 200ms/div. 200ms/div.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 14 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD = 54V, VADP = 24V, TA = 25°C, unless otherwise noted. Adapter Start-Up IOUT = 0A Adapter Start-Up IOUT = 3A CH2: V ADP 10V/div. CH1: VOUT 10V/div. CH3: PG 10V/div. CH4: IVADP 200mA/div. CH2: V ADP 10V/div. CH1: VOUT 10V/div. CH3: PG 10V/div. CH4: IVADP 2A/div. 100ms/div. 100ms/div. Adapter Shutdown IOUT = 0A Adapter Shutdown IOUT = 3A CH2: V ADP 10V/div. CH1: VOUT 10V/div. CH3: PG 10V/div. CH4: IVADP 200mA/div. CH2: V ADP 10V/div. CH1: VOUT 10V/div. CH3: PG 10V/div. CH4: IVADP 2A/div. 100ms/div. 100ms/div. S C P E n t r y IOUT = 1.35A to short SCP Recovery IOUT = short to 0A CH2: VDD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH4: IVDD 2A/div. CH2: VDD 20V/div. CH1: VOUT 20V/div. CH3: PG 20V/div. CH4: IVDD 200mA/div. 4ms/div. 40ms/div.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 15 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM From PSE Control Logic and Gate Driver VDD GATE1 SRC RDET DET Maintain Power Signature R_MPS VAUX-H AUX Classification 14.5V to 20.5VCLSB CLSA RCLSA RCLSB TYP2 PG VOUT GND CVDD DUTY RMPS From Adapter RDUTY VADP GATE2 Drive COUT PRI TYP1 RILIM ILIM RSENSE SENSE Drive SENSE BT CADP Figure 1: Functional Block Diagram
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 16 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. OPERATION The MP8020 is an IEEE802.3af/at/bt-compliant, Power over Ethernet (PoE), powered device (PD). The device includes all the functions of IEEE 802.3af/at/bt, including detection, classification, input current (I IN) control, a 100V hot-swap MOSFET, and automatic maintain power signature functionality. Detection The MP8020 integrates an internal detection resistor. When the power-sourcing equipment (PSE) applies two safe voltages between 2.7V and 10.1V to the MP8020, the MP8020 typically shows a 25kΩ resistance between the VDD and GND pins. Classification The PSE distributes power to the PDs based on the classification result s. Classification mode is active between 14.5V and 20.5V. The MP8020 presents different currents in classification mode (see Table 1). Table 1: Different Classification Power Rating and Setting with the MP8020 PD Class Power Rating (W) Class Cycle with Max Power CLSA Signature CLSB Signature CLSA Resistor CLSB Resistor 0 0.44 to 12.95 1 0 0 578 578 1 0.44 to 3.84 1 1 1 110 110 2 3.84 to 6.49 1 2 2 62 62 3 6.49 to 12.95 1 3 3 41.2 41.2 4 12.95 to 25.5 2, 3 4 4 28.7 28.7 5 25.5 to 40 4 4 0 28.7 578 6 40 to 51 4 4 1 28.7 110 7 51 to 62 5 4 2 28.7 62 8 62 to 71.3 5 4 3 28.7 41.2 IEEE802.3bt supports an 8-level class power rating, with up to 5 classification cycle operations. These classification cycles have the below functions: All PSEs perform one cycle classification for the class 0, class 1, class 2, and class 3 PDs. Type 2 PSEs perform 2-cycle classification if a class 4 signature is detected during the first class cycle. Type 3 and type 4 PSEs start their third cycle classification if a class 4 signature is detected during the first and second class- cycle. Based on the third cycle classification result, the Type 3 and Type 4 PSEs follow one of the operations listed below: o If the third classification result is a class 4 signature, classification stops and there is a class 4 PD. o If the third classification results in a class 0 or class 1 signature, the devices continue to the fourth cycle classification. o If the third classification result is class 2 or class 3 signature, the type 4 PSE performs a fourth and fifth cycle classification. The MP8020 performs a class signature signal with the CLSA pin during the first and second class cycles. The device performs a class signature signal with the CLSB pin in the remaining class cycles, unless V DD drops to the mark event reset threshold. Both CLSA and CLSB use the same output voltage (V OUT) for classification. The maximum output current (IOUT) is limited for self-protection. Under-Voltage Lockout (UVLO) and the Power Supply Voltage The MP8020 integrates one under-voltage lockout (UVLO) circuit with a large hysteresis. The UVLO block ensures that the MP8020 starts up when V DD exceeds 40V and shuts down when VDD drops below 30V. The MP8020 also has an inrush current limit function during start-up. This current is about 1/7 of the steady state current limit, which is configured by the ILIM pin.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 19 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. Table 3: PSE and Allocated Power Indicator PSE Type PD Class PSE Allocated Powe r Number of Class Cycles BT TYP1 TYP2 Type 1 Type 2 Class 0 Class 1 Class 2 Class 3 12.95W 3.84W 6.49W 12.95W
1 High High High
Type 2 Class 4 25.5W 2 Hi gh Hi gh Low Type 3 Type 4 Class 0 Class 1 Class 2 Class 3 12.95W 3.84W 6.49W 12.95W
1 Low High High
Class 4 25.5W 2, 3 Low Hi gh Low Class 5 Class 6 40W 51W 4 Low Low High Type 4 Class 7 Class 8 62W 71.3W 5 Low Low Low Table 4: Power Demotion Cases PSE Type PD Class PSE Allocated Powe r Number of Class Cycles BT TYP1 TYP2 Type 2 Class 4 12.95W 1 High High High Type 3 Type 4 Classes 4~8 12.95W 1 Low High High Type 3 Type 4 Classes 5~8 25.5W 2, 3 Low High Low Type 3 Type 4 Classes 7~8 51W 4 Low Low High Automatic Maintain Power Signature To maintain the PSE power supply, the MP8020 supports automatic maintain power signature, and the current is configured by a resistor on the R_MPS pin. The MP8020 also has one DUTY pin to configure the R_MPS pin’s voltage duty cycle, which can compensate the effects of the long cable and bulk bus capacitors. After V DD reaches the UVLO rising threshold, the DUTY pin sources one pulse current to detect the maintain power signature function duty cycle setting. Table 5 shows the DUTY pin’s configuration options. Once V DD falls to the VDD UVLO falling threshold, the DUTY signal resets. Table 5: DUTY Configurations DUTY to GND Resistance (kΩ) R_MPS Duty Cycle (%) Min T yp Max 0 0 1.4 6 5.76 7.15 9.09 11.5
17.4 Float Float 17
With type 1 and type 2 PSE inputs, the MP8020 generates a voltage on the R_MPS pin with a fixed 37% duty cycle. Wall Adapter Power Supply For applications where an auxiliary power source such as a wall adapter is used to power the device, the MP8020 features wall power adapter detection. Once the adapter voltage ADP) exceeds about 8.3V, the MP8020 enables wall adapter detection. The resistor divider connected from VADP to AUX detects the adapter status. Once the AUX voltage exceeds the internal reference voltage, the MP8020 switches the power source from the PSE to the adapter if the adapter has higher priority. GATE2 drives the external N-channel MOSFET and provides a smooth switch between the PSE and auxiliary wall adapter with less power loss than a traditional diode input. After the adapter supply is enabled, the PG signal is high, the TYP1 and TYP2 pins output low, and the BT pin remains high.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 20 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. When PRI is high, pull AUX high to disable the DET, CLS, and maintain power signature functions. When PRI is low, pulling AUX high cannot disable DET, CLS, and maintain power signature functions. If an adapter is available, the PG signal is pulled high under all conditions. If the adapter has a higher priority and replaces the PSE power supply, then BT, TYP1, and TYP2 are updated once the AUX and ADP_UV signals are working. If the PSE has a higher priority and replaces the adapter supply, then the MP8020 changes the BT, TYP1, and TYP2 statuses to Hi-Z once PSE UVLO occurs. The statuses change to indicate the PSE power type after inrush is complete and the 90ms delay has finished. Power Priority The adapter is available when both AUX and V ADP exceed the threshold. The MP8020 can source a current from the adapter or PSE if both the adapter and PSE are connected. This is determined by the PRI and AUX pin settings. The PRI pin is internally pulled up to the internal VCC. If the PRI pin is floating (the adapter has higher priority) and V ADP/AUX exceed their thresholds, the MP8020 disables the PSE power supply, and enables the adapter power source. If AUX is below its falling threshold, then the PSE supplies power to the output even when PRI is floating. If the PRI pin is connected to GND, the PSE has the higher priority. Regardless of the AUX signal, the PSE outputs power unless V DD i s below UVLO. If the PSE has a higher priority and the adapter is connected before PSE plug-in, a reverse blocking MOSFET must be added to reverse block the power from the adapter during PoE detection and classification (see Figure 4). At the same time, the output downstream DC/DC converter should lower the power rating so that the inrush current charges the MP8020’s output capacitor (C OUT) quickly. If C OUT is not charged quickly, then the current limit is triggered and the device fails to start up. From PSE MP8020 GATE1 SRC GATE2 From Adapter VADP VDD VOUT AUX CLSB CLSA TYP1 PG TYP2 SENSE ILIM DUTY R_MPS GND Q1 Q3 R1 R2 PRI R3 R4 COUT Figure 4: Reverse Block Solution Thermal Protection Thermal shutdown prevents the IC from operating at exceedingly high temperatures. If the die temperature exceeds 150°C, the IC shuts down. Once the die temperature drops to 20°C, the device resumes normal operation.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 22 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. The MP8020 also has an inrush current limit function after start-up, which is about 1/7 of the steady state current limit. Selecting the PoE Power MOSFET The MP8020 internal hot-swap MOSFET has a maximum 1.6A current limit. For type 1, 2, and
3 PDs (≤51W), the internal hot-swap MOSFET
is sufficient. For type 4 PDs (>51W), an external MOSFET must be placed in parallel with the internal hot-swap MOSFET. The GATE1 pin can drive one external N-channel MOSFET. The MOSFET should be selected to meet the following specifications: The voltage rating should be at least 100V for high-voltage surge environments. The on resistance (R DS(ON)) should be below 200mΩ for power dissipation and for light- load shutdown functions. A 100mΩ R DS(ON) is typically recommended. The gate charge (Q G) should be as small as possible to provide faster response times under overload conditions. It is typically recommended for Q G to be below 15nC (VGATE = 4.5V). The gate threshold voltage should be below 4V to fully drive the GATE1 and GATE2 voltages. SENSE Pin Setting The external parallel MOSFET current limit is configured by a resistor (R SENSE) between the VDD and SENSE pins. It is typically recommended for R SENSE to be 18mΩ. The total current limit (I IN_LIM) can be calculated using Equation (1): IN _ LIM INNER SENSE 26mVII R (1) Where IIN_LIM is the PD current limit, and I INNER is the MP8020 internal hot-swap MOSFET current limit. When the external MOSFET is connected, it is recommended to set I INNER to 0.9A. Selecting the Adapter MOSFET The GATE2 pin is designed to drive one external N-channel MOSFET for the adapter supply. Select the adapter MOSFET using the same guidelines as the PoE power MOSFET. Design Example Table 6 shows a design example following the application guidelines for the specifications below. Table 6: Design Example VDD Class Level VADP 54V Class 8 24V For the detailed application schematic, see Figure 8 on page 24. For the typical performance and circuit waveforms, see the Typical Performance Characteristics section on page 12. For more device applications, refer to the related evaluation board datasheet.
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 24 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUIT 20kΩ 200kΩ GND 0.1µF 47µF C2B 41.2Ω GND 28.7Ω GND GND VDD GND Adapter GND 1.2kΩ VOUT GND GND 18mΩ 200kΩ GND 2.2µF SMAJ58A SI4100DY GND VDD1 GND GATE2 3 VADP AUX 5 R_MPS 6 ILIM 7DUT Y 8 PRI9 CLSA10 CLSB11 BT 12 TYP2 13TYP1 14 PG 15SRC 16 GATE1 17 SENSE18 MP8020 SI2392 0.1µF C2A GND Figure 8: Class-8 PD Solution with PSE and Adapter Supplies
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 25 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.
PACKAGE INFORMATION
QFN-18 (3mmx5mm) SIDE VIEW BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID 0.30X45°TYP
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE MP8020 Rev. 1.0 MonolithicPower.com 26 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package (3mmx5mm) 5000 N/A N/A 13in 12mm 8mm
MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE Notice: The information in this document is subject to change without notice. Users should warrant and guarantee that third- party Intellectual Property rights are not infringed upon when integrating MPS products int o any application. MPS will not assume any legal responsibility for any said applications. MP8020 Rev. 1.0 MonolithicPower.com 27 2/17/2022 MPS Proprietary Information. Patent Protected. Unauth orized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved.
REVISION HISTORY
Revision # Revision Date Description Pages Updated 1.0 2/17/2022 Initial Release -