MP8007GV-P

MP8007 MPS | Alldatasheet

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Technical content

MP8007 Fully-Integrated 802.3af-Compatible PoE PD Interface with 13W Primary-side Regulated Flyback or Buck Converter MP8007 Rev.1.0 www.MonolithicPower.com 1 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. The Future of Analog IC Technology

DESCRIPTION

The MP8007 is an integrated IEEE 802.3af compatible PoE Powered Device with PD interface and power converter. It is targeted for isolated or non-isolated 13W PoE application. The PD interface has all the functions of IEEE 802.3af, including detection, classification, 120mA inrush current, 840mA operation current limit as well as 100V Hot-swap MOSFET. The DCDC converter uses fixed peak current and variable frequency discontinuous conduction mode (DCM) to regulate constant output voltage. The primary-side regulation without opto-coupler feedback in flyback mode simplifies the design while buck mode continues minimizes the solution size for non- isolated applications. A 180V integrated power MOSFET optimizes the device for various wide voltage applications. The MP8007 features protection including over current protection, over voltage protection, open circuit protection and thermal shutdown. The MP8007 can support a front-end solution for PoE-PD application with minimum external component, it is available in QFN-28 (4mmX5mm) package.

FEATURES

 Compatible with 802.3af Specifications  Support 13W PoE Power Application  100V 0.48 Ω PD Integrated Pass Switch  120mA PD Inrush Current  840mA PD Operation Current Limit  Auxiliary Adaptor ORing Power Supply  Integrated 180V Switching Power MOSFET  Supports Primary-Side Regulated Flyback without Opto-Coupler Feedback  Supports Low-side Switch Buck Converter  Up to 3A Programmable Switching Current Limit  OLP, OVP, Open-Circuit, and Thermal Protection  Minimal External Components  Available in QFN-28 (4mmx5mm) Package

APPLICATIONS

 IEEE 802.3af-Compliant Devices  Security Camera  VoIP Phones  WLAN Access Points  IoT Devices All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 10 100 1000

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 2 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MP8007GV QFN-28 (4mm X 5mm) See blew * For Tape & Reel, add suffix –Z (e.g. MP8007GV–Z) TOP MARKING MPS: MPS prefix: Y: year code; WW: week code: MP8007: part number; LLLLLL: lot number; PACKAGE REFERENCE TOP VIEW

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 3 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Pins Voltage Respects to VSS: (2) VDD, RTN, DET, T2P, AUX, GND, AGND Pins Voltage Respects to GND (2): (3) Pins Voltage Respects to VDD: Pins Current: Continuous Power Dissipation (TA=+25)(6) Recommended Operating Conditions (7) Operating Junction Temp. (T J). -40°C to +125°C Thermal Resistance (8) θJA θJC QFN-28 (4mmx5mm) …… . … .… 40 9 °C/W Notes: 1) Exceeding these ratings may damage the device. 2) GND and AGND must be connected to RTN 3) Refer to the “Converter Output Voltage Setting” section. 4) VCC voltage can be pulled higher than this rating, but the external pull-up current should be limited. Refer to “VCC sinking current” rating and “VCC Power Supply Setting” section. 5) When VDD to Adapter-ground voltage is high, AUX-VDD voltage may exceed -6.5V if the divider resistor is not appropriate, in this condition VDD will clamp the -6.5V voltage on AUX pin, but the current should be limited by external resistor. 6) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 7) The device is not guaranteed to function outside of its operating conditions. 8) Measured on JESD51-7, 4-layer PCB.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 4 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; R DET = 24.9kΩ, RCLASS =41.2 Ω. T J = -40°C to +125°C, typical values are tested at T J = 25 C, unless otherwise noted. PD Interface Section Parameter Symbol Condition Min Typ Max Units Detection Detection on V DET-ON V DD Rising 1.9 V Detection off V DET-OFF V DD Rising 11 V DET Leakage Current V DET-LK V DET=VDD=57V, Measure IDET 0.1 5 μA Bias Current VDD=10.1V, float DET pin, not in Mark event, Measure ISUPPLY 12 μA VDD=2.5V, Measure ISUPPLY 96 99 102 μA Detection Current I DET VDD=10.1V, Measure ISUPPLY 395 410 425 μA Classification Classification Stability Time 90 μs VCLASS Output Voltage V CLASS 13V<VDD< 21V 1mA<ICLASS< 42mA 1.1 1.16 1.21 V 13≤VVDD≤21V, Guaranteed by VCLASS RCLASS=578Ω, 13V≤VDD≤21V 1.8 2 2.4 RCLASS=110Ω, 13V≤VDD≤21V 9.9 10.55 11.3 RCLASS=62Ω, 13V≤VDD≤21V 17.7 18.7 19.8 RCLASS=41.2Ω, 13V≤VDD≤21V 26.6 28.15 29.7 Classification Current I CLASS RCLASS=28.7Ω, 13V≤VDD≤21V 38.2 40.4 42.6 mA Classification Lower Threshold VCL-ON Class Regulator Turns on, VDD Rising 11.8 12.5 13 V Classification Upper Threshold VCL-OFF Class Regulator Turns off, VDD Rising 21 22 23 V Low side Hysteresis 0.8 Classification Hysteresis V CL-HYS High side Hysteresis 0.5 V Mark Event Reset Threshold V MARK-L 4.5 5 5.5 V Max Mark Event Voltage V MARK-H 11 11.5 12 V Mark Event Current I MARK 0.5 1.5 2 mA Mark Event Resistance R MARK 2-point Measure at 7V and 10V 12 k Ω IC Supply Current during Classification IIN-CLASS V DD = 17.5V, CLASS Floating 220 300 μA Class Leakage Current I LEAKAGE V CLASS = 0 V, VDD = 57V 1 μA PD UVLO VDD Turn on Threshold V DD-VSS-R V DD Rising 35 37.5 40 V VDD Turn off Threshold V DD-VSS-F V DD Falling 29 31 33 V VDD UVLO Hysteresis VDD-VSS- HYS 4.9 V IC Supply Current during Operation IIN 450 μA

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 5 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; R DET = 24.9kΩ, RCLASS =41.2 Ω. T J = -40°C to +125°C, typical values are tested at T J = 25 C, unless otherwise noted. PD Interface Section Parameter Symbol Condition Min Typ Max Units Pass Device and Current Limit On Resistance R ON-RTN I RTN=600mA 0.48 Ω Leakage Current IRTN-LK VDD=VRTN=57V 1 15 μA Current Limit I LIMIT V RTN=1V 720 840 920 mA Inrush Current Limit I INRUSH V RTN=2V 120 mA Inrush Current Termination V RTN Falling 1.2 V Inrush to Operation Mode Delay TDELAY 80 100 ms Current Fold-back Threshold V RTN Rising 10 V Fold-back Deglitch Time VRTN Rising to Inrush Current Fold-back 1 ms T2P T2P Output Low Voltage I T2P=2mA, respect to VSS 0.1 0.3 V T2P Output High Leakage Current V T2P=48V 1 μA AUX AUX High Threshold Voltage(9) Respect to VDD -2.3 V AUX Low Threshold Voltage(9) Respect to VDD -0.6 V AUX Leakage Current V DD -VAUX=6V 2 μA PG PG Output High Voltage PG pin floating 5.5 V Source Current Capability PG is logic high, pull down PG pin to 0V 30 μA PG Pull Down Resistance PG is logic low, pull up PG pin to 1V 460 k Ω PG High-Level Voltage to Enable DCDC Converter VPG-EN-H 3.9 V PG Low-Level Voltage to Disable DCDC Converter VPG-EN-L 1.3 V PD Thermal Shutdown Thermal Shut down Temperature(10) TPD-SD 150 ºC Thermal Shut down Hysteresis(10) TPD-HYS 20 ºC

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 6 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; R DET = 24.9kΩ, RCLASS =41.2 Ω. T J = -40°C to +125°C, typical values are tested at T J = 25 C, unless otherwise noted. DCDC Converter Section Parameter Symbol Condition Min Typ Max Units Converter Power Supply and UVLO Converter VDD UVLO Rising Threshold VDD-RTN-R PG-RTN=5V, Test VDD-RTN 10.5 11.6 12.8 V Converter VDD UVLO Falling Threshold VDD-RTN-F PG-RTN=5V, Test VDD-RTN 7.4 8.2 9 V VCC Regulation(11) V CC Load = 0mA to 10mA 4.8 5.4 5.9 V VCC UVLO Rising Threshold(11) VCC-R VDD is higher than UVLO, VCC rising 4.3 4.7 5.1 V VCC UVLO Falling Threshold(11) VCC-F VDD is higher than UVLO, VCC falling 4 4.5 4.8 V Quiescent Current I Q VFB1 = 2.2 V, VFB2 = VDD, Test supply from VDD to VSS 0.87 mA Voltage Feedback Respect to GND, TJ = 25°C 1.94 1.99 2.04 V FB1 Reference Voltage V REF1 Respect to GND, TJ = -40°C to +125°C 1.93 1.99 2.05 V FB1 Leakage Current I FB1 Respect to GND, V FB1 = 2V 10 50 nA Flyback Mode DCM Detect Threshold on FB1 VDCM1 Respect to GND 25 50 75 mV FB1 Open-circuit Threshold V FB1OPEN -90 -60 -20 mV FB1 OVP Threshold V FB1OVP 120% 125% 130% V REF1 Minimum Diode Conduction Time for FB1 Sample TSAMPLE 1.4 2.2 3 μs Respect to VDD, TJ = 25°C -1.955 -1.88 -1.805 V FB2 Reference Voltage V REF2 Respect to VDD, TJ = -40°C to FB2 Leakage Current I FB2 Respect to VDD, V FB2 = -2V 10 50 nA Buck Mode DCM Detect Threshold on SW VDCM2 Respect to VDD 0 0.14 V Switching Power Device On Resistance R ON-SW V CC = 5.4V 0.8 Ω Current Sense Switching Current Limit I LIMIT R ILIM = 53.6kΩ, L = 47μH 1.85 2.05 2.25 A Switching Current Leading- edge Blanking Time TLEB 450 ns

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 7 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; R DET = 24.9kΩ, RCLASS =41.2 Ω. T J = -40°C to +125°C, typical values are tested at T J = 25 C, unless otherwise noted. DCDC Converter Thermal Shutdown Thermal Shutdown Temperature(10) TSD 150 ºC Thermal Shutdown Hysteresis(10) THYS 20 ºC 9) If VDD-AUX>2.3V, IC enable adapter input, if VDD-AUX<0.6V , IC enable PSE input. Refer to "Wall adaptor detection and operati on" section for AUX setting. 10) Guaranteed by characterization, not tested in production. 11) The maximum VCC UVLO rising threshold is higher than the minimum VCC regulation in the EC table due to production distribut ion. However, for one unit, VCC regulation is higher than the VCC UVLO rising threshold. The VCC UVLO rising threshold is about 87 p ercent of the VCC regulation voltage, and the VCC UVLO falling threshold is about 83 percent of the VCC regulation voltage in one unit.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 8 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 9 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 10 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 11 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted. IPRI 2A/div. VSW 50V/div. VOUT 5V/div. VFB1 2V/div. IPRI 2A/div. VSW 50V/div. VOUT 5V/div. VFB1 2V/div. IPRI 2A/div. VSW 50V/div. VOUT 5V/div. VIN 50V/div. IOUT 500mA/div. VOUT/AC 200mV/div. IOUT 500mA/div. VOUT/AC 1V/div. IOUT = 1AIOUT = 10mA IPRI 2A/div. VSW 50V/div. VOUT 5V/div. VIN 50V/div. IPRI 2A/div. VSW 50V/div. VOUT 5V/div. VIN 50V/div.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 12 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. PIN FUNCTIONS PIN# Name Description

1 AUX

Auxiliary power input detector. Use this pin for adaptor power supply application. Drive VDD-AUX higher than 2.3V to disable hot-swap MOSFET and CLASS pin function, and force T2P and PG active. 2 DET Connect 24.9k Ω resistor between VDD and DET for PoE detection. 3, 11, 14, 15, 19, 22, N/C Not connected internally, can be connected to GND pin and exposed thermal pad in layout. 4 VDD Positive power supply terminal from PoE input power rail. 5 FB2 Feedback pin for non-isolated buck soluti on. Connect FB2 to VDD in flyback application

6 MODE

Buck mode or flyback mode select pin. MO DE is pulled up internally to VCC through a 1.5µA current source. Float MODE for buck application mode; connect MODE to GND for flyback application mode. 7 FB1 Feedback for fly-back solution. Conn ect FB1 to GND in buck application 8 ILIM DCDC converter switching current limit program pin. Connect ILIM to GND through a resistor to program the peak current limit. 9 AGND Analog power return for DCDC converter control circuit. Connect to GND through single point. 10 VCC Supply bias voltage pin, powered through internal LDO from VIN. It is recommended to connect a capacitor (no less than 1µF) between VCC and GND. 12,13 SW Drain of converter switching MOSFET. 16,17 GND Switching converter power return. Connect to RTN for PoE power supply. Exposed thermal pad can be connected to GND plane for heat sink. 18 PG PD supply power good indicator. This signal will enable the DCDC converter internally. It is pulled up by internal curr ent source in output high condition, suggest float it in application. 20,21 RTN Drain of PD Hot-swap MOSFET , connect GND and AGND to this pin. 23,24 VSS Negative power supply terminal from PoE input power rail. 25 FTY Factory use only, must be connected to VSS in application. 26 CLASS Connect resistor from CLASS to VSS to program classification current. 27 T2P Type 2 PSE indicator, open-drain output. Pulled low to VSS indicates the presence of a Type-2 PSE or AUX is enabled.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 13 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. FUNCTION DIAGRAM SW Current Sense GND Driver Management FB1 DCM Detection Protection Feedback Sampling FB2 AGND ILIM ILIMT Program MODE Detection 2.7V - 10.1V Classification 14.5V – 20.5V Mark Event 6.9V – 10.1V VDD DET CLASS Inrush and Current Limit Control Logic and Gate Driver VSS RTN Startup Delay Control AUX PG Current / Voltage Sense 5.5V 0/30μA T2P VCC Power Supply Management DCDC Enable VSS Figure 1: Functional Block Diagram

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 16 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Wall Power Adaptor Detection and Operation For applications where an auxiliary power source such as a wall adapter is used to power the device, the MP8007 features wall power adapter detection as showing in figure 4. Once the input voltage (V DD - V SS) exceeds about 11.5V, the MP8007 enable wall adapter detection. The wall power adapter detection resistor divider is connected from VDD to negative terminal of adaptor, and D ADP3 is added for more accurate hysteresis. There is a -2.3V reference voltage from AUX to VDD for adaptor detection. The adaptor is detected when AUX voltage triggers: ADPUP DD AUX ADP DADP3 ADPUP ADPDOWN RVV ( V V ) 2 . 3 V RR     (1) Where, V ADP is adaptor voltage, V DADP3 is the zener voltage, R ADPUP and R ADPDOWN are the AUX divider resistors from adaptor power. If applied adapter voltage is much higher than the design adapter voltage, VDD-VAUX voltage will be high, if it is higher than 6.5V, the MP8007 inner circuit will clamp the VDD-VAUX voltage at 6.5V, then a current will flow out through the AUX pin, the current should be limited lower than 3mA by external resistor ADPUP/RADPDOWN or RT resistor from the resistor divider to AUX PIN.) To make MP8007 work stable with adaptor power, one Schottky diode D APD1 (D4 in schematic on page 1) is required between negative terminal of adaptor and VSS. D APD2 (D5 in schematic on page 1) is used to block reverse current between adaptor and PSE power source. When a wall adapter is detected, the internal MOSFET between RTN and VSS turns off, classification current is disabled and T2P becomes active. The PG signal is active when adaptor power is detected, so that it can enable the downstream DCDC converter even input hot-swap MOSFET is disabled. Figure 4: Adaptor Power Detection Power Good Indicator (PG) The PG signal is driven by internal current source. After T DELAY from UVLO starting and RTN drops to 1.2V, or a wall power adapter is detected, the PG signal will be pulled high to indicate power condition and enable the downstream DCDC converter. Figure 3 shows the PG logic when powering from PSE, PG will be high if adaptor is detected. DCDC Converter Startup and Power Supply Once PD input overrides its UVLO, it will charge DCDC converter’s input capacitor (between VDD and RTN) with PD inrush current limit. DCDC converter has an internal start-up circuit. When voltage between VDD and GND is higher than 4.3 V, the capacitor at VCC is charged through the internal LDO. Normally V CC is regulated at 5.4 V (if VDD is high enough). With the exception of PD interface UVLO, the DCDC converter has an additional V IN UVLO (11.6V) and V CC UVLO (4.7V). When VDD-GND is higher than the 11.6V UVLO, V CC is charged higher than the 4.7V UVLO, and PG pin is pulled high by PD interface, DCDC converter starts switching. V CC can be powered from the transformer auxiliary winding to save IC power loss. Refer to the “Vcc Power Supply Setting” section for more details. Flyback and Buck Mode Converter The DCDC converter supports both flyback and buck topology applications. Connect MODE to GND to set the DCDC converter in flyback mode, and float MODE to set the DCDC converter in buck mode. MODE is pulled up internally to V CC through a 1.5µA current source. Do not connect MODE to VDD externally in

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 18 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Output Voltage Control In flyback application, the DCDC converter detects the auxiliary winding voltage from FB1 during the secondary-side diode conduction period. Assume the secondary winding is the master, and the auxiliary winding is the slave. When the secondary-side diode conducts, the FB1 voltage is calculated with Equation (7): FB1 OUT D1F S1 2 (7) Where: VD1F is the output diode forward-drop voltage. VOUT is the output voltage. NA and NS are the turns of the auxiliary winding and the secondary-side winding, respectively. R1 and R2 are the resistor dividers for sampling. The output voltage differs from the secondary- winding voltage due to the current-dependant diode forward voltage drop. If the secondary- winding voltage is always detected at a fixed secondary current, the difference between the output voltage and the secondary-winding voltage is a fixed V D1F. DCDC converter starts sampling the auxiliary-winding voltage after the internal power MOSFET turns off for 0.7 μs and finishes the sampling after the secondary-side diode conducts for 3 μs. This provides good regulation when the load changes. However, the secondary diode conducting period must be longer than 3 μs in each cycle, and the FB1 signal must be smooth in 0.7 μs after the switch turns off. With a buck solution, there is one FB2 pin referred to VDD. It can be used as the reference voltage for the buck application. The output voltage is referred to VDD and does not have the same GND as the input power. Programming the Switching Current Limit The switching converter current limit is set by an external resistor (R3 in schematic on page 1) from ILIM to ground. The value of R3 can be estimated with Equation (8): L LIM V0 . 1 8100I R3 L  (8) Where I LIM is the current limit in A, V L is the voltage applied on the inductor when the MOSFET turns on, R3 is the setting resistor in kΩ, and L is the inductor in μH. The current limit cannot be programmed higher than 3A. If Input voltage is very low, the inductor current may increase slowly, it will take a long time to meet the setting current limit. MP8007 integrates a ~7us max on time. After the max on time, MOSFET will turn off, even the inductor current doesn\`t meet the setting current limit. Converter Leading-Edge Blanking Transformer parasitic capacitance induces a current spike on the switching power FET when the power switch turns on. The DCDC converter includes a 450 ns leading-edge blanking period to avoid falsely terminating the switching pulse. During this blanking period, the current sense comparator is disabled, and the gate driver cannot switch off. DCDC Converter DCM Detection The DCDC switching regulator operates in discontinuous conduction mode in both flyback and buck modes. In flyback mode, the DCDC converter detects the falling edge of the FB1 voltage in each cycle. The second cycle switching will not start unless the chip detects a 50 mV falling edge on FB1. In buck mode, the DCDC converter detects the falling edge of the SW voltage in each cycle. The second cycle switching will not start unless the chip detects 0.14 V falling edge between V SW-VDD. Over-Voltage & Open-Circuit Protection In flyback mode, the DCDC converter includes over-voltage protection (OVP) and open-circuit protection. If the voltage at FB1 exceeds 125 percent of V REF1, or FB1’s -60 mV falling edge cannot be detected because the feedback resistor is removed, immediately the DCDC converter shuts off the driving signal and enters hiccup mode by re-charging the internal capacitor. The DCDC converter resumes normal operation when the fault is removed.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 19 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. In buck mode, if the voltage at FB2 is higher than the reference voltage, the DCDC converter stops switching immediately. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from thermally running away. MP8007 has separated temperature monitor circuit for PD and switching devices, DC converter thermal protection won't affect PD interface but PD temperature protection will turn off both PD and DC converter. When the temperature is lower than its recovery threshold, thermal shutdown is gone and the chip is enabled.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 20 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

APPLICATION INFORMATION

In the Detection Mode, a resistor connected between DET and VDD pin is needed as a load to the PSE. The resistance is calculated as a ΔV/ΔI, with an acceptable range of 23.7k Ω to 26.3kΩ. Use a typical value of 24.9k Ω as detection resistor. Classification Resistor In order to distribute power to as many loads as possible from PSE, a resistor between CLASS and VSS pins is used to classify the PD power level, which draws a fixed current set by classification resistor. The power supplied to PD set by classification resistor is shown in Table 1. Typical voltage on CLASS pin is 1.16V 0.1μF, 100V ceramic capacitor is used. recommended to reduce conduction power-loss. disable the DCDC regulator of MP8007.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 22 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. GND FB1 Na Figure 10: Feedback in isolation application When the primary-side power MOSFET turns off, the auxiliary-winding voltage is sampled. The output voltage is estimated: SREF1 1 2 OUT D1F NV( R R )VV RN Where, NS is the transformer secondary-side winding turns. N A is the transformer auxiliary winding turns. VD1F is the rectifier diode forward drop. VREF1 is the reference voltage of FB1 (1.99V, typically). When the primary-side power MOSFET turns on, the auxiliary winding forces a negative voltage to FB1. The FB1 voltage is clamped to less than -0.7V internally, but the clamp current should be limited to less than -0.5mA by R1. For example, if the auxiliary winding forces -11V to R1, to make the current flowing from FB1 to R1 lower than -0.5mA, R1 resistance must be higher than 22k Ω (if ignoring R2 current). Generally, select R2 with a 10k Ω to 50k Ω resistor to limit noise and provide an appropriate R1 for the -0.5mA negative current limit. In buck application, the feedback pin is FB2. The output voltage can be estimated: OUT REF2 RRVV R   (13) Where, V REF2 is the reference voltage of FB2 -1.88V, typically. Maximum Switching Frequency When DCDC converter works in DCM, the frequency reaches its maximum value during a full-load condition. The maximum frequency is affected by the peak current limit, the inductance, and the input/output voltage. Generally, design the maximum frequency must be lower than 200kHz. In buck mode, the maximum frequency occurs when the buck runs in critical continuous conduction mode. The frequency can be calculated: IN OUT OUT SW _ MAX LIM IN (V V ) VF IL V (14) Where, I LIM is the I PK set by the current limit resistor. With a lighter load, the frequency is lower than the maximum frequency above. In flyback mode, design the maximum frequency with the minimum input voltage and the maximum load condition. Calculate the frequency with Equation: SW ON CON DELAY 1F TT T  (15) Where: TON is the MOSFET one pulse turn-on time determined with Equation: LIM M ON IN ILT V  (16) LM is the transformer primary-winding inductance. TCON is the rectifier diode current conducting time and can be calculated: SL I M M CON PO U T D 1 F NI LT N( V V ) (17) Where, N S is the transformer secondary-side winding turns. N P is the transformer primary- side winding turns. TDELAY is the resonant delay time from the rectifier diode current drop to 0A to the auxiliary-winding voltage drop to 0V. The resonant time can be tested on the board (estimate around 0.5μs). In flyback mode, the DCDC converter samples the feedback signal within 3μs after the primary-

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 23 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. side MOSFET turns off. The secondary-side diode conduction time in Equation (17) should be higher than 3 μs. This time period, combined with the duty cycle, determines the maximum frequency. Converter Input Capacitor Selection An input capacitor is required to supply the AC ripple current to the inductor while limiting noise at the input source. A low ESR capacitor is required to keep the noise to the IC at a minimum. Ceramic capacitors are preferred, but tantalum or low ESR electrolytic capacitors will suffice. For ceramic capacitors, the capacitance dominates the impedance at the switching frequency. The ripple will be the worst at light load. The required input capacitance can be estimated: LIM ON INP _ P

0.5 I TC V

 (18) Where C 1 is the DCDC converter input bulk capacitor value, V INP-P is the expected input ripple, and TON is the MOSFET turn-on time. In an isolated application, TON is calculated: LIM M ON IN ILT V  (19) In a non-isolation application, TON is calculated: LIM ON IN OUT ILT VV   (20) Where L is the buck\`s inductor value. Converter Output Capacitor Selection The output capacitor maintains the DC output voltage. For best results, use ceramic capacitors or low ESR capacitors to minimize the output voltage ripple. For ceramic capacitors, the capacitance dominates the impedance at the switching frequency. In flyback application, the worst output ripple occurs under a light-load condition; the worst output ripple can be estimated: PL I M C O N OUTP _P S

0.5 N I TV NC 2

Where, C2 is the output capacitor value. VOUTP-P is the output ripple. Normally, a 44μF or higher ceramic capacitor is recommended as the output capacitor. This allows a small Vo ripple and stable operation. In buck application, the worst Vout ripple can be estimated with Equation (22): LIM IN D1F OUTP _ P IN OUT OUT D1F

0.5 I L (V V )V C2 (V V ) (V V )

(22) Leakage Inductance The transformer’s leakage inductance decreases system efficiency and affects the output current and voltage precision. Optimize the transformer structure to minimize the leakage inductance. Aim for a leakage inductance less than 3 percent of the primary- winding inductance. RCD Snubber for Flyback The transformer leakage inductance causes spikes and excessive ringing on the MOSFET drain voltage waveform, affecting the output voltage sampling 0.7µs after the MOSFET turns off. The RCD snubber circuit limits the SW voltage spike (see Figure 11). Figure 11: RCD snubber The power dissipation in the snubber circuit is estimated with Equation (23): SN K LIM S Where, LK is the leakage inductance. Since R4 consumes the majority of the power, R4 is estimated with Equation (24): SN SN VR4 P (24) Where, VSN is the expected snubber voltage on C4. The snubber capacitor C4 can be designed to get appropriate voltage ripple on the snubber using Equation (25): SN SN S VV R4 C4 F  (25)

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER MP8007 Rev.1.0 www.MonolithicPower.com 24 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Generally, a 15 percent ripple is acceptable. Buck Inductor Selection The inductor is required to transfer the energy between the input source and the output capacitors. Unlike normal application where inductors determine the inductor ripple, the DCDC converter always works in DCM while V IN, V OUT, and I LIM are constant. The inductor only determines the speed of the current rising and falling, which determines the switching period. The expected maximum frequency can determine the inductor value using Equation (26): IN OUT OUT D1F IN D1F PEAK SW (V V ) (V V ) 1L (V V ) I F (26) FSW is the expected maximum switching frequency, which should be lower than 200kHz in general setting. Converter Output Diode Selection The output rectifier diode supplies current to the output capacitor when the internal MOSFET is off. Use a Schottky diode to reduce loss due to the diode forward voltage and recovery time. In isolation application, the diode should be rated for a reverse voltage greater than Equation (27): IN S D1 OUT PD1 P VNVV V N   (27) VPD1 can be selected at 40 percent to 100 percent of V OUT + V IN x N S/NP. An RC or RCD snubber circuit for the output diode D1 is recommended. In buck mode, the diode reverse voltage equates to the input voltage. A 20 percent ~ 40 percent margin is recommended. In both applications, the current rating should be higher than the maximum output current. Converter Dummy Load When the system operates without a load in flyback mode, the output voltage rises above the normal operation voltage because of the minimum switching frequency limitation. Use a dummy load for good load regulation. A large dummy load decreases efficiency, so the dummy load is a tradeoff between efficiency and load regulation. For applications using Figure 14, a minimum load of around 10mA is recommended. PCB Layout Guide A good layout of the PoE front-end and high- frequency switching power supply is critical. Poor layout may result in reduced performance, excessive EMI, resistive loss, and system instability. For best results, refer to Figure 12 and Figure 13 and follow the guidelines in below: For PD interface circuit: 1. All components place must follow power flow, from RJ-45, Ethernet transformer, diode bridges, TVS, to 0.1- μF capacitor and DCDC converter input bulk capacitor. 2. Make all leads as short as possible with wide power traces. 3. The spacing between V DD (48V) and V SS must comply with safety standards like IEC60950. 4. Place the PD interface circuit ground planes referenced to VSS, while place the switching converter ground planes referenced to RTN/GND. 5. The exposed PAD must be connected to GND, it can not be connected to VSS. 6. If adaptor power detection is enabled, the AUX divider resistor should be close to AUX pin. And diode D5 (between VSS and RTN) should be placed close to VSS and RTN. For flyback circuit: 1. Keep the input loop as short as possible between the input capacitor, transformer, SW, and GND plane for minimal noise and ringing. 2. Keep the output loop between the rectifier diode, the output capacitor, and the transformer as short as possible. 3. Keep the clamp loop circuit between D2, C4, and the transformer as small as possible. 4. Place the VCC capacitor close to VCC for the best decoupling. The current setting resistor R3 should be placed as close to ILIM and AGND as possible.

MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8007 Rev.1.0 www.MonolithicPower.com 27 6/27/2016 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN28 (4mmX5mm)

Summary

Fully-Integrated 802.3af-Compatible PoE PD Interface with 13W Primary-side Regulated Flyback or Buck Converter 6/27/2016 Rev.1.0

Description