MP8005

MP8005 MPS | Alldatasheet

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Technical content

13W 802.3af PoE Powered Device (PD) Interface and PWM Controller MP8005 Rev. 1.0 www.MonolithicPower.com 1 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.

DESCRIPTION

The MP8005 is a complete integrated IEEE 802.3af POE compliant Powered Device (PD) power supply solution. It includes the PD control function and an isolated/non isolated synchronous regulator controller. Thermal protection is built in to accommodate both transient and/or overload conditions, shutting the part down and protecting the input source as well as the output load depending on the particular fault conditions. Inrush current limiting is included to slowly charge the input capacitor without interruption due to die heating, a problem encountered without the current limit foldback feature. The desired output voltage is user programmable through the selection of an external resistor divider. EVALUATION BOARD REFERENCE Board Number Dimensions EV8005DF-00A 5.33”x1.75”x0.8” ( LxWxH)

FEATURES

• Meets IEEE 802.3af Specifications
• 100V, 1 Ω Integrated switch
• 460mA max, Temperature Compensated Current Limit
• Isolated Synchronous Controller
• 20 pin TSSOP Package

APPLICATIONS

• VoIP Telephones
• Network Cards
• Security Camera Systems
• Safety Backup Power
• Remote Internet Power All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithi c Power Systems, Inc. TYPICAL ISOLATED APPLICATION

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 2 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking Temperature MP8005DF TSSOP-20-EP MP8005DF –40°C to +85°C For Tape & Reel, add suffix –Z (e.g. MP8005DF–Z). For Lead Free, add suffix –LF (e.g. MP8005DF–LF–Z) PACKAGE REFERENCE AGND ISENSE RDELAY VFB NC VDD PG RTN RTN COMP VCC MAINGATE SYNCGATE CSS ENABLE ILIM CLASS DET VSS NC ABSOLUTE MAXIMUM RATINGS (1) V Continuous Power Dissipation (T A = +25°C) (2) Recommended Operating Conditions (3) Thermal Resistance (4) θJA θJC Notes: 1) Exceeding “Absolute Ma ximum Ratings” may cause permanent damage to the device. Functional operation at or above these conditions is not implied Exposure to these conditions for extended periods may affect device reliability. 2) The maximum allowable powe r dissipation is a function of the maximum junction temperature. T J(MAX) the junction-to- ambient thermal resistance. θJA and the ambient temperature, TA the maximum allowable power dissipation at any ambient temperature is calculated using: PD(MAX)=(TJ(MAX)-TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circ uitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 3 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VDD = 48V, all voltages with respect to VSS, VSS = 0V; RDET = 26.1kΩ, RCLASS = 4.42KΩ, RILIM = 178kΩ, TA = 25°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units VCC Undervoltage Lockout Internal Divider (I Q) 4.5 4.7 V VCC On/Off Voltage Hysteresis 1 V Shutdown Current I S EN/SS =0V, V IN=9V 50 μA Quiescent Current I Q Output not switching, no load, VFB=1V, VCC=9V 270 320 μA Main Gate Driver Impedance (Sourcing) V CC=9V, VGATE=5V 16 Ω Main Gate Driver Impedance (Sinking) V CC=9V, IGATE=5mA 5.0 Ω Synchronous Gate Driver Impedance (Sourcing) V CC=9V, VSYNCGATE=5V 16 Ω Synchronous Gate Driver Impedance (Sinking) V CC=9V, IGATE=5mA 5.0 Ω Delay after Synchronous Gate R DELAY=100KΩ 50 ns Error Amplifier Transconductance VFB connected to VCOMP/RUN. Force ± ± 10μA to VCOMP/RUN. 0.26 0.38 0.46 mA/V Maximum comp Current Sourcing and Sinking 40 μA Error Amplifier Translator Gain (5) AET 0.28 0.32 0.36 V/V Switching Frequency f S 220 260 300 kHz Thermal Shutdown 150 °C Maximum Duty Cycle 76 81 86 % Minimum On Time t ON 200 ns ISENSE Limit 165 190 215 mV FB Voltage V FB 0.794 0.818 0.847 V FB Bias Current I FB Current flowing out of part 50 nA ISENSE Bias Current I SENSE Current flowing out of part 50 nA Enable On Threshold V EN High-to-Low 1.15 1.25 1.35 V Enable Hystersis V EN 50 mA Soft Start Current I SS 4 μA

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 4 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD = 48V, all voltages with respect to VSS, VSS = 0V; RDET = 26.1kΩ, RCLASS = 4.42KΩ, RILIM = 178kΩ, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Detection Detection on VDET_ON VDD=VRTN=VPG=1.9V 1.9 V Detection off VDET_OFF VDD=VRTN=VPG=11V 11 V Detection on/off Hysteresis VDET_H Falling below 11V on Threshold 0.2 V DET Leakage Current V DET_LK V DET=VVDD=57V, Measure IDET 0.1 5 μA VDD= 3V 135 140 145 μA Detection Current I DET VVDD=VRTN RDET=26.1kΩ, Measure IVDD+IRTN+IDET VDD= 10.1V 405 420 435 μA Classification VCLASS Output Voltage V CL Over a Load Range of 1mA to 41.2 mA 9.6 10 10.3 V RCLASS=4420Ω, 13≤VVDD≤21V (guar by VCL) 2.2. 2.4 2.8 RCLASS=953Ω, 13≤VVDD≤21V (guar by VCL) 10.3 10.6 11.3 RCLASS=549Ω, 13≤VVDD≤21V (guar by VCL) 17.7 18.3 19.5 RCLASS=357Ω, 13≤VVDD≤21V (guar by VCL) 27.1 28 29.5 Classification Current I CLASS RCLASS=255Ω, 13≤VVDD≤21V (guar by VCL) 38 39.4 41.2 mA Classification Lower Threshold VCL_ON Regulator Turns on, V VDD Rising 10.2 11.3 13 V Classification Upper Threshold VCU_OFF Regulator Turns off, V VDD Rising 21 21.9 23 V V CU_H Hysteresis 0.4 V IC Supply Current during Classification IIN_CLASS VDD = 17.5V, CLASS Floating, RTN Tied to VSS 300 500 μA Leakage Current I LEAKAGE V CLASS = 0 V, VVDD = 57V 1 μA Pass Device On Resistance R DS(ON) I RTN=300mA 1.0 1.2 Ω Leakage Current ISW_LK VVDD=VRTN=57V 1 15 μA Current Limit I LIMIT V RTN=1V 360 400 460 mA Inrush Limit I INRUSH V RTN=2V, RILM=178kΩ 120 150 180 mA Inrush Current Termination VRTN Falling, RIPEAK = 178kΩ, Inrush StateÆNormal Operation 85 90 100 %

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 5 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VDD = 48V, all voltages with respect to VSS, VSS = 0V; RDET = 26.1kΩ, RCLASS = 4.42KΩ, RILIM = 178kΩ, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units PG Latchoff Voltage Threshold Rising V RTN Rising (5) 9.5 10 10.5 V Latchoff Voltage Threshold Falling V RTN Falling 1.2 V PG Deglitch Delay Rising and Falling PDG (5) 75 150 225 μs Output Low Voltage I PG = 400 μA 0.12 0.4 V Leakage Current V PG = 57 V, VRTN = 0 V 0.1 1 μA UVLO Voltage at VVDD V VDD Rising (including 1.4V Diode drop) 38 40 42 V V VDD Falling (including 1.4V Diode drop) 30.2 31.5 32.8 Thermal Shutdown Thermal Counter Reset Voltage VCRST Must Drop below Classification Range 10.8 V Bias Current Operating Current I Q (VDD) VDD = 48V, Pins 5, 6 Floating Measure IVDD 240 450 μA Notes: 5) Guaranteed by Design.

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 6 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description

1 VCC 10V Shunt Supply Voltage used for the switching regulator controller

2 MAINGATE Output drive to the Main Gate

3 SYNCGATE Output drive to the Synchronous Gate

4 CSS Soft-start ramping capacitor

5 ENABLE On/Off control input to the switching regulator

6 ILIM Startup I LIM Value Setting Resistor terminal (optional at this point). 7 CLASS Classification Resistor terminal. 8 DET 26.1k Ω Detection Resistor terminal 9 VSS Ground return to the Ethernet negative supply.

10 No Connection

11 No Connection

12 RTN Powered Device Negative Power Terminal. 13 RTN Powered Device Negative Power Terminal. 14 PG Active low power good indication. 15 VDD Positive Power Supply Terminal for the Ethernet PD control function. 16 COMP Switching regulato r compensation terminal. 17 VFB Switching regulator voltage feedback terminal.

18 RDELAY Resistor programming for setting the delay from the Sync gate going low to the Main gate

going high. 19 ISENSE Main Switch cu rrent sensing terminal. 20 AGND Switching regulator controller ground return; Returns to the RTN pin.

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 7 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS 100 VCC Regulator Line Regulation EFFICIENCY (%) LOAD CURRENT (A) LOAD CURRENT (A) Output Voltage vs. Load Current VDD=40V VDD=60V Efficiency vs. Load Current -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00 DIFFERENCE (%)VDD=40V VDD=60V 0 1 02 03 04 05 06 0 VDD(V) IIN (mA) VDD Increasing VDD Decreasing Output Ripple VDD=60V, ILOAD=4A VRTN 50V/div VPG 5V/div VOUT 5V/div IIN 0.5A/div VRTN 1V/div VPG 5V/div VDD 20V/div VPG-VRTN IRTN 0.5A/div 20ms/div Start Up VDD=48V, ILOAD=2.6A Shut Down VDD=48V, ILOAD Transient Response VDD=48V, ILOAD=2.6A, 0 to 2.6A Load Slew:1.0A/1uS 200ms/div 200us/div 2us/div VOUT/AC 200mV/div IOUT 1A/div VOUT/AC 200mV/div VSW 5V/div

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 8 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. BLOCK DIAGRAM DET ILIM CLASS VSS VDD RTN MP8005 MAINGATE SYNCGATE RDELAY ISENSE CSS COMP Vfb PG ENABLE VCC DETECTION CLASSIFICATION STARTUP CONTROL LOGIC 1.2v OSCILLATOR PWM CONTROL LOGIC DELAY 1.2v AGND Figure 1— Block Diagram

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 9 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. OPERATION The MP8005 operates in the manner described here and in the IEEE 802.3af Powered Device (PD) Specification. This device (along with the power sourcing element (PSE)) operates as a safety device to supply potentially lethal voltages only when the power sourcing element recognizes a unique, tightly specified resistance at the end of an unknown length of Ethernet cable. A 25kΩ resistance is presented as a load to the PSE in Detection Mode, when the PSE applies two “safe” voltages of less than 10.1V each while measuring the change in current drawn in order to determine the load resistance. If the PSE “sees” the correct load, then it may either further increase the applied voltage to enter the “classification” range of operation or switch on the nominal 48V power to the load. The classification mode can further specify to the PSE the expected load range of the device under power so that the PSE can intelligently distribute power to as many loads as possible (within its maximum current capabilities). If a classification resistance is not present, the PD load is assumed to be the maximum of approximately 13 Watts. The classification mode is active between 14.5V and 20.5V. The main power switch will pass a limited current above 31V, charging the external DC-to-DC converter’s input capacitor in a controlled manner. The charging will continue until the controlled current drops below either an externally programmed limiting level or 450mA, depending upon the Rlim current setting resistor. The main power switch is internally thermally protected to 100V by reducing the output current using a foldback technique. The required power dissipation of the IC drops from the allowed peak value of 26W (450mA x 57V) to 0.16W ((450mA) x R ON) during the normal operation at turn-on. The minimum allowed capacitance of 5µF will charge in 500µs. A larger capacitor will take a proportionally longer time to charge due to the constant current charging method. A capacitor that is too large will overheat the part and force it into thermal shutdown. The IC will reattempt charging for a number of cycles but ultimately will be shut down until the input voltage from the PSE is recycled. This is the way the IC protects itself under overload and/or shorted conditions. Once the capacitor tied between Vdd, Ethernet input positive supply and the RTN pin is charged to within a volt of the applied Ethernet input supply potential, the PG output is driven low to enable the switching regulator controller. This delay prior to turning on the switching regulator is required in order to minimize the power dissipation incurred during the startup of the controller. The capacitance tied across the Vdd and RTN lines provide the inductor ripple current while maintaining a small voltage differential such that the average current flowing in the RTN line is under the current limit level. Without a storage capacitance at this point, instantaneous current peaks, required by the switching regulator during normal operation, would send the main PD switch (at the RTN pin) in and out of current limit resulting in high power dissipation due to the resultant voltage across the “switch”. A current greater than the current limit value would increase the voltage on the RTN pin to the Ehternet Input supply voltage immediately resulting in power dissipation levels that would immediately shut down the PD switch without the required storage capacitor. The soft-start capacitor, CSS, slows the rate of current delivery to the switching regulator to a value that can be delivered by the storage capacitor/PD switch. A resistor tied between the Rdelay pin and AGND sets a time delay between the falling edge of the synchronous gate and the rising edge of the main gate. This delay can be set to compensate for system delays caused by architectural structures of the circuit being used. An isolated secondary type power supply having a transformer in the feedback loop may require extra time due to the electrical path incurred. The delay time is adjustable from as little as 40nSec to over 200nSec through the choice of resistance value. A smaller resistance will result in a shorter delay. Nominal values range from 0 - 200 k Ω for time delays from 40nSec to 200nSec. The delay

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER MP8005 Rev. 1.0 www.MonolithicPower.com 10 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. is very important in that it prevents cross conduction of the switching MOSFETS that either severely reduces efficiency or even worse, a switching MOSFET failure. The output drive levels of the main and synchronous gate are in the hundreds of mA through a 0 to 10V voltage potential. A “normal” threshold MOSFET (Vth typ. 3.5V) having low gate charge (less than 10 nano-Coulombs @ 10V drive) is recommended. The nominal range of the ISENSE pin is set to a maximum of 200mV but should be designed such that 100mV across the sense resistor provides the maximum current that is expected for the nominal load. This will provide enough “headroom” for typical applications.

MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8005 Rev. 1.0 www.MonolithicPower.com 11 9/26/2013 MPS Proprietary Information. Patent Protec ted. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.

PACKAGE INFORMATION

(EXPOSED PAD) NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION ACT. 6) DRAWING IS NOT TO SCALE. 0.19 0.30 6.40 6.60 SEATING PLANE

0.65 BSC

4.30 4.50 6.20 6.60 11 0 1120 0.80 1.05 1.20 MAX 0.00 0.15 TOP VIEW FRONT VIEW SIDE VIEW 0.09 0.20 BOTTOM VIEW 2.60 3.10 3.80 4.30 RECOMMENDED LAND PATTERN 5.80 TYP 1.60 TYP 0.40 TYP 0.65 BSC 3.20 TYP 4.40 TYP DETAIL A 0.45 0.75 0o-8o

0.25 BSC

SEE DETAIL "A"