MP7651AS

MP7651 EXAR | Alldatasheet

Document overview

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Technical content

Rev. 2.00 8-Channel, Voltage Output

10 MHz Input Bandwidth 8-Bit Multiplying

DACs with Serial Digital Data Port and Chip Select Decoder

FEATURES

• 8 Independent 2-Quadrant Multiplying 8-Bit DACs
• Serial Digital Input Data and Address Port (3-Wire Standard) plus Internal Chip Address Decoder
• Dual Supplies (+5 V typ.)
• High Speed:

12.5 MHz Digital Clock Rate

VREF to VOUT Settling Time: 150ns to 8-bit (typ) Voltage Reference Input Bandwidth:

10 MHz (typ)

• Low Power: 150mW (typ)
• Low AC Voltage Reference Feedthrough
• Excellent Channel-to-Channel Isolation
• DNL = +0.8 LSB, INL = +1 LSB (typ)
• DACs Matched to +0.5% (typ)
• Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz
• VREF/2 Output Preset Level
• Latch-Up Proof
• Greater than 2000 V ESD Protection

APPLICATIONS

• ATE
• Process Control (Low Noise)
• Convergence Adjustment for High Resolution Monitors (Work Stations)
• Digital Gain/Attenuation/Offset Control
• Trimmer Replacement GENERAL DESCRIPTION The MP7651 is ideal for direct gain control of video, compos- ite video, CCD and other high frequency analog signals. The de- vice includes 8-channels of high speed, high bandwidth, two quadrant, multiplying, 8-bit accurate digital-to-analog converter. It includes an output drive buffer per channel capable of driving +1mA (typ) to a load. DNL of better than +0.8 LSB is achieved with a channel-to-channel matching of better than 0.5%. Stabil- ity, matching, and precision of the DACs is achieved by using EXAR’s thin film technology. Also, excellent channel-to-channel isolation is achieved with EXAR’s BiCMOS process which can- not be achieved using a typical CMOS technology. An open loop architecture (patent pending) provides wide small signal bandwidth from VREF to output up to 10 MHz (typ), fast output settling time, and VREF feedthrough isolation of –65dB or better. In addition, low distortion in the order of 0.25% with a 1 V p–p, 1 MHz signal. A specified and constant input impedance of each VREF+ in- put gives flexibility for optimal system design. The serial data 3-wire standard µ-processor logic interface reduces pin count, package size (28 pin), and board wire (space). Additionally, the internal chip select decoder allows for easy daisy chaining with- out the addition of separate control logic. MP7651 is fabricated on a junction isolated, high speed, dual metal, linear compatible BiCMOS (BiCMOS IVTM) thin film resis- tors. This process enables precision high speed analog/digital (mixed-mode) circuits to be fabricated on the same chip.

Rev. 2.00 SIMPLIFIED BLOCK DIAGRAM GND SDO CLK RST 1-Bit Latch SDI 16-Bit Shift Register DB0 to DB7 4-Bit CH Address LD VEE VCC VO0 VO7 DAC 0 DAC 7 DAC 1 8-Bit Latch 8-Bit Latch 8-Bit Latch 4-8 DEC 3-State Buffer VO1 LD 4-Bit CS Address COMP CS0P to CS3P 1-Bit Latch VR0 VR1 VR7 LD LD

ORDERING INFORMATION

Part No. SOIC –40 to +85°C MP7651AS +0.8 +1.5 Plastic Dip –40 to +85°C MP7651AN +0.8 +1.5 INL (LSB) Gain Error (% FSR) DNL (LSB)

Rev. 2.00 PIN CONFIGURATIONS See Packaging Section for Package Dimensions 28 Pin PDIP (0.300”) NN28 VR1 VO1 VO2 VR2 GND VO4 VR4 VR5 VO5 VO6 VR0 VO0 CS3P CS2P SDI CS1P SDO CLK CSOP VO7 VR7 VR6 VCC VR3 VO3 VEE VR0 28 Pin SOIC (EIAJ, 0.335”) R28 VO0 CS3P CS2P SDI CS1P SDO CLK CSOP VO7 VR7 VR6 VR1 VO1 VO2 VR2 GND VO4 VR4 VR5 VO5 VO6 VR3 VO3 VCC VEE RST LD RST LD PIN OUT DEFINITIONS VR1 DAC 1 Reference Input VO1 DAC 1 Output VO2 DAC 2 Output VR2 DAC 2 Reference Input VR3 DAC 3 Reference Input VO3 DAC 3 Output VCC Positive Supply VEE Negative Supply GND Ground VO4 DAC 4 Output VR4 DAC 4 Reference Input VR5 DAC 5 Reference Input VO5 DAC 5 Output VO6 DAC 6 Output VR6 DAC 6 Reference Input PIN NO. NAME

DESCRIPTION

Chip Select Bit 0 (LSB) CS1P Chip Select Bit 1 SDI Serial Data/Address Input SDO Serial Data Output CLK Shift Register Clock LD Load Signal; Load Data to Selected DACs RST Reset Signal; Reset all DACs to VREF/2 CS2P Chip Select Bit 2 CS3P Chip Select Bit 3 (MSB) VO0 DAC 0 Output VR0 DAC 0 Reference Input PIN NO. NAME

Rev. 2.00 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Noted: VCC = +5 V, VEE = –5 V and –3 V, VREF = 3 V and –3 V, T = 25°C, Output Load = Open 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments DC CHARACTERISTICS Resolution (All Grades) N Bits Differential Non-Linearity DNL +0.8 LSB Integral Non-Linearity INL LSB Monotonicity Guaranteed Guaranteed Gain Error GE +1.5 +1.5 % FSR FSR = Full Scale Range (1) Zero Scale Offset ZOFS +20 +75 +75 mV Output Drive Capability IO mA REFERENCE INPUTS Impedance of VREF REF kΩ Voltage Range VR VEE +1.5 VCC–1.8 V VREF Max Swing is AGND +3 V DYNAMIC CHARACTERISTICS2 RL = 5 k, CL = 20 pF Input to Output Bandwidth MHz VR = 1.6 V p–p, RL = 5k to VEE Input to Output Settling Time5 150 ns VR = 1.6 V p–p, RL = 5k to VEE Small Signal Voltage Reference ƒtr MHz VOUT=50mV p-p above code 16 Input to Output Bandwidth Small Signal Voltage Reference ƒtr MHz VOUT=50mV p-p for all codes Input to Output Bandwidth Voltage Settling from VREF to tsr 275 300 325 ns VR=0 to VR = 3V Step (6) VDAC Out to 1 LSB Voltage Settling from Digital tsd 275 300 325 ns ZS to FS to 1 LSB Code to VDAC Out VREF Feedthrough FDT –65 dB Codes=0 @ 1 MHz Group Delay GD ns Harmonic Distortion THD 0.5 VREF=1MHz Sine 3V p-p Channel-to-Channel Crosstalk CT –75 dB @ 1 MHz, single channel Digital Feedthrough Q nVs CLK to VOUT Power Supply PSRR 0.02 %/% ∆ V = +5% Rejection Ratio POWER CONSUMPTION Positive Supply Current ICC mA VREF = 0 V Negative Supply Current IEE mA VREF = 0 V Power Dissipation PDISS 150 250 300 mW VREF = 0 V, Codes = all 1 DIGITAL INPUT CHACTERISTICS Logic High3 VIH 2.4 2.4 V Logic Low3 VIL 0.8 0.8 V Input Current IL +10 +10 µA Input Capacitance2 CL pF

Rev. 2.00 ELECTRICAL CHARACTERISTICS TABLE SPECIFICATIONS2, 4 Input Clock Pulse Width tCH, tCL ns Data Setup Time tDS ns Data Hold Time tDH ns CLK to SDO Propagation Delay tPD ns DAC Register Load Pulse Width tLD 100 100 ns Reset Pulse Width tRST ns Clock Edge to Load Rising Edge tCKLD1 100 100 ns Clock Edge to Load Falling Edge tCKLD2 ns Load Falling Edge to SDO tHZ1 ns 3-state Enable Load Rising Edge to SDO tHZ2 ns 3-state Disable Load Falling Edge to CLK Disable tLDCK1 ns Load Rising Edge to CLK Enable tLDCK2 ns LD Set-up Time with Respect tLDSU ns to CLK CS0-CS3 Set-Up Time with tCSLD ns Respect to LD 25°C Tmin to Tmax NOTES: Full Scale Range (FSR) is 3V. Guaranteed but not production tested. Digital Input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See Figures 2 and 3. For reference input pulse: tR = tF > 100 ns. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VCC to GND +6.5 V VEE to GND –6.5 V VRi to GND VCC to VEE VOi to GND VCC to VEE Digital Input & Output Voltage to GND GND –0.5 to VCC +0.5 V Operating Temperature Range Extended Industrial –40°C to +85°C Maximum Junction Temperature 150°C Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 sec) +300°C Package Power Dissipation Rating @ 75°C PDIP, SOIC 1000mW Derates above 75°C 6mW/°C NOTES: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATIONS INFORMATION Refer to Section 8 for Applications Information

Table 1. Digital Function Truth Table Table 2. DAC Transfer Function

4 To 16

Figure 4. Internal Chip Address Decoder Plus Logic Interface

Figure 9. Simplified Diagram

Figure 10. 8085 Interface (Simplified Diagram) write instruction to address 4000. Serial data must be present in the right justified format in registers H & L of the microprocessor. Figure 1. Crosstalk Measurement Set-Up

1.6 Vp–p

Rev. 2.00 PERFORMANCE CHARACTERISTICS Channel-to-Channel Crosstalk (Gain vs. Frequency; All DACs set to full scale; VREF=1.6 Vp-p) DAC 0 Driven MHz dB Graph 1. Output DACs shown below are: DAC 7, 1, 2, 5, 6, 3 and 4 DAC 7 DAC 1 Driven MHz dB Graph 2. Output DACs shown below are: DAC 2, 0, 3, 4, 7, 5 and 6 DAC 2 DAC 2 Driven MHz dB Graph 3. Output DACs shown below are: DAC 1, 3, 4, 5, 0, 6 and 7 DAC 1 DAC 3 Driven MHz dB Graph 4. Output DACs shown below are: DAC 4, 2, 1, 7, 0, 5 and 6 DAC 4 DAC 4 Driven MHz dB Graph 5. Output DACs shown below are: DAC 5, 3, 6, 7, 0, 1 and 2 DAC 5 DAC 5 Driven MHz dB Graph 6. Output DACs shown below are: DAC 6, 4, 7, 0, 3, 1 and 2 DAC 6 DAC 6 Driven MHz dB Graph 7. Output DACs shown below are: DAC 5, 7, 0, 4, 3, 1 and 2 DAC 5 DAC 7 Driven MHz dB Graph 8. Output DACs shown below are: DAC 0, 6, 5, 4, 3, 1 and 2 DAC 0

Rev. 2.00 Graph 9. Linearity Error vs. Digital Input Code DACs 0 to 3 Graph 10. Linearity Error vs. Digital Input Code DACs 4 to 7 Graph 11. Preset Voltage vs. Temperature Graph 12. PSRR vs. Frequency Graph 13. Gain & Phase vs. Frequency Graph 14. Feedthrough vs. Frequency VR = 1.6 V p-p VR = 500 mV p-p Digital Input Code Digital Input Code Gain Phase

Rev. 2.00 Graph 15. Gain (VO/VR) vs. Frequency Open Loop/Unloaded Output* Graph 16. THD vs. Frequency Graph 17. ICC vs. Temperature Graph 18. IEE vs. Temperature Graph 19. Reference Input Voltage Range vs. Supply Voltages Graph 20. All Channel Crosstalk vs. Frequency All DACs driven, measured DAC @ zero scale and other DACs @ full scale All DACs except monitored driven, all DACs @ full scale A B VR = 6 V p-p

3 V p-p

1.5 V p-p

1 V p-p

0.5 V p-p

GE = +1.5% FSR VRR Negative VRR Positive – V * A 2K or 5K resistor across output and VEE will remove peaking (See graph 26).

Rev. 2.00 Graph 21. Digital Settling LD (5 V/DIV) VR = 3 V Digital Code = 255→0→255 VO (2 V/DIV) 2µs/DIV Graph 22. Pulse Response (tR = tF = 100 ns for VR) VR (2 V/DIV) Digital Code = All Ones VO (2 V/DIV) 2µs/DIV Graph 23. 128 kHz Sawtooth Waveform Response VR (2 V/DIV) VO (2 V/DIV) 2µs/DIV Graph 24. Clock and SDI Feedthrough LD (5 V/DIV) VO (10mV/DIV) 2µs/DIV Graph 25. Clock/SDI Feedthrough LD (5 V/DIV) VO (10mV/DIV) 2µs/DIV Graph 26. Typical Gain and Group Delay vs. Frequency (with 5K resistor across output to VEE) MHz Gain (5 dB/DIV) Group Delay (20 ns/DIV)

Rev. 2.00

28 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP) NN28 SYMBOL MIN MAX MIN MAX INCHES A 0.130 0.230 3.30 5.84 0.015 0.381 B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.340 1.485 34.04 37.72 E 0.290 0.325 7.37 8.26 0.240 0.310 6.10 7.87 e

0.100 BSC

2.54 BSC

L 0.115 0.150 2.92 3.81 α 15° 15° 0.055 0.070 1.40 1.78 S 0.020 0.100 0.508 2.54 MILLIMETERS Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. D e A L B Seating Plane α C E S

Rev. 2.00 SYMBOL MIN MAX MIN MAX A 2.60 2.80 0.102 0.110 0.2 (typ.) 0.008 (typ.) B 0.3 0.5 0.012 0.020 C 0.10 0.20 0.004 0.008 D 17.6 18.0 0.693 0.709 E 8.3 8.5 0.327 0.335 e 1.27 (typ.) 0.050 (typ.) H 11.5 12.1 0.453 0.477 L 0.8 1.2 0.031 0.047 INCHES MILLIMETERS e

28 LEAD SMALL OUTLINE

(335 MIL EIAJ SOIC) R28 A L C D E H B Seating Plane

Rev. 2.00 Notes

Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.