MP7636 EXAR | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Rev. 2.00

FEATURES

  • Four Quadrant Multiplication
  • 16-Bit Monotonicity
  • Lower Data Bus Feedthrough @ CS = 1
  • Low Feedthrough Error
  • Low Power Consumption
  • TTL/5 V CMOS Compatible
  • Double Buffered
  • Decoded DAC Approach
  • Latch-Up Free

15 V CMOS Microprocessor Compatible

Double-Buffered, Multiplying 16-Bit Digital-to-Analog Converter BENEFITS

  • High Accuracy Performance at Low Cost
  • Easy Interface with 8-Bit Microprocessors
  • Simple Upgrade of MP1230A Family to High Accuracy (Pin Compatible)
  • Reduced Board Space
  • 16-Bit Bus Version: MP7626 GENERAL DESCRIPTION The MP7636A is manufactured using advanced thin film resistors on a double metal CMOS process. The MP7636A incorporates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 16-bit differential non-linearity is achieved with minimal laser trim. The MP7636A is packaged in a 20-pin 300 mil wide DIP and is a direct 16-bit replacement for the 12-bit DAC1230 series. Full pin-for-pin compatibility allows existing systems to be upgraded to 16 bits without hardware modification. The MP7636A provides 16-bit data loading through 8 input data lines for direct interface to 8-bit data buses. All data loading and data transfer operations are identical to the WRITE cycle of a static RAM. The MP7636A uses a unique circuit which significantly reduces transients in the supplies during DATA bus transitions at CS = 1. SIMPLIFIED BLOCK DIAGRAM DGND AGND DB15 (MSB) (DB7) DB14 (DB6) DB13 (DB5) DB12 (DB4) DB11 (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0, LSB) BYTE1/BYTE2 CS WR1 XFER WR2 8-Bit Input Latch 16-Bit Register 16-Bit MDACLE LE When LE = 1 latch outputs follow inputs When LE = 0 Latch outputs are latched R FB IOUT1 IOUT2 VDD VREF 8-Bit Input Latch

Rev. 2.00

ORDERING INFORMATION

Range Part No. SOIC SOIC –40 to +85°C +2+ 2 MP7636AJS + 4+ 4 MP7636AKS 0.1 –40 to +85°C 0.1 INL (LSB) Gain Error (% FSR) DNL (LSB) *Contact factory for non-compliant military processing PIN CONFIGURATION 201 1110 DB12 (DB4) DB13 (DB5) DB14 (DB6) DB15 (MSB) (DB7) VDD IOUT2 IOUT1 AGND DB11 (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0, LSB) DGND R FB VREF 20 Pin SOIC (Jedec, 0. 300”) S20 See Packaging Section for Package Dimensions CS WR1 BYTE1/BYTE2 WR2 XFER PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION 1C S Chip Select (Active Low)

2 WR1 Write1 (Active Low)

3 AGND Analog Ground

4 DB11 Data Input Bit 11 (MSB)

(DB3) Data Input Bit 3

5 DB10 Data Input Bit 10

(DB2) Data Input Bit 2

6 DB9 Data Input Bit 9

(DB1) Data Input Bit 1

7 DB8 Data Input Bit 8

(DB0) Data Input Bit 0 (LSB) REF Reference Input Voltage 9R FB Internal Feedback Resistor

10 DGND Digital Ground

12 I OUT2 Current Output 2

13 DB15 (MSB) Data Input Bit 15

(DB7) (Most Significant Bit) Data Input Bit 7

14 DB14 Data Input Bit 14

(DB6) Data Input Bit 6

15 DB13 Data Input Bit 13

(DB5) Data Input Bit 5

16 DB12 Data Input Bit 12

(DB4) Data Input Bit 4

17 XFER Transfer Control Signal

(Active Low)

18 WR2 Write 2 (Active Low)

19 BYTE1/ Byte Sequence Control

20 V DD Power Supply

PIN NO. NAME DESCRIPTION

Rev. 2.00

ELECTRICAL CHARACTERISTICS

(VDD = + 15 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 FSR = Full Scale Range Resolution (All Grades) N 16 16 Bits Integral Non-Linearity INL LSB Best Fit Straight Line Spec. (Relative Accuracy) (Max INL – Min INL) / 2 J, S + 4+ 4 K, L, T + 2+ 2 Differential Non-Linearity DNL LSB All grades guaranteed J, S + 4+ 4 monotonic over full K, T + 2+ 2 operating temperature L+ 1+ 2 range. Gain Error GE + 0.1 + 0.1 % FSR Using Internal R FB Gain Temperature Coefficient2 TC GE +2 ppm/ °C ΔGain/ΔTemperature Power Supply Rejection Ratio PSRR + 50 + 50 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Output Leakage Current I OUT +10 + 200 nA I OUT1 only DYNAMIC PERFORMANCE 2 Current Settling Time t S 2 µs To 1/2 LSB R L=100Ω , CEXT =13pF AC Feedthrough at IOUT1 FT 2 mV p-p V REF = 20 V p-p Sine wave @ 10kHz REFERENCE INPUT Input Resistance R IN 2.5 7.5 2.5 7.5 k Ω LOGIC INPUTS 3 Input High Voltage V INH 3.0 2.4 3.0 V Input Low Voltage V INL 0.8 0.8 V Input Current I LKG +1+ 1 µA Input Capacitance Data C IN 5p F Control C IN 5p F ANALOG OUTPUTS 2 Output Capacitance C OUT1 280 pF DAC all 1’s C OUT1 120 pF DAC all 0’s C OUT2 100 pF DAC all 1’s C OUT2 240 pF DAC all 0’s

Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments POWER SUPPLY 5 Functional Voltage Range2 VDD 4.5 16.5 5.0 16.5 V Supply Current I DD 1 1 mA All digital inputs 0 V or V DD SWITCHING CHARACTERISTICS 2, 4 CS to WR Set-Up Time t CS 150 ns CS to WR Hold Time t CH 10 ns Data Valid to WR Set-Up Time t DS 70 ns Data Valid to WR Hold Time t DH 70 ns WR , XFER Pulse Width t W 150 ns NOTES: Specifications are subject to change without notice 25°C Tmin to Tmax (1) Full Scale Range (FSR) is 10V for unipolar mode. (2) Guaranteed but not production tested. (3) Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. (4) See timing diagram. (5) Specified values guarantee functionality. Refer to other parameters for accuracy. ABSOLUTE MAXIMUM RATINGS (T A = +25°C unless otherwise noted)1, 2, 3 DC Voltage Applied to IOUT1 or IOUT2 GND –0.5 V to +17 V (Functionality Guaranteed +0.5 V) Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 GND refers to AGND and DGND. APPLICATION NOTES Refer to Section 8 for Applications Information

Rev. 2.00 TIMING DIAGRAM 50%50% 50% 50% 50% 50% SETTLED TO +0.01% CS , BYTE1/BYTE2 WR DATA BITS VIH VIL VIH VIL VIH VIL tCS tCH tW tDS tS tDH IOUT1, IOUT2 DEFINITION OF CONTROL SIGNALS: CS : Chip Select (Active low). It will enable WR1. WR1 : Write 1 (Active low) The WR1 is used to load the digital data bits (DB) into the input latch. BYTE1/BYTE2 : Byte sequence control. The BYTE1/BYTE2 control pin is used to select MSB and LSB both input latches. WR2 : Write 2 (Active low). It will enable XFER. XFER : Transfer control signal (Active low). This signal, in combination with WR2, causes the 16-bit data which is available in the input latches to transfer to the DAC register. DB0 to DB15: Digital Inputs. DB0 is the least significant digital input (LSB) and DB15 is the most significant digital input (MSB). IOUT1 : DAC Current Output 1 Bus. IOUT1 is a maximum for a digital code of all 1’s in the DAC register, and is zero for all 0’s in the DAC register. IOUT2 : DAC Current Output 2 Bus. IOUT2 is a complement of IOUT1 . The ladder termina- tion has been tied to IOUT2 internally. R FB : Feedback Resistor. This internal feedback resistor should always be used (not an external resistor) since it matches the resistors in the DAC and tracks these resistor over temperature. VREF : Reference Voltage Input. This input connects an external precision voltage source to the internal DAC. The VREF can be selected over the range of +25V to –25V or the analog signal for a 4-quadrant multiplying mode application. V DD : Power Supply Voltage. This is the power supply pin for the part. The VDD can be from +5 V DC to +15 V DC, however optimum volt- age is +15 V DC. AGND: Analog Ground. Back gate of the DAC N-channel current steering switches. DGND: Digital Ground . The timing diagrams for updating the DAC register are shown in Figures 1 and 2.

Rev. 2.00 SYMBOL MIN MAX MIN MAX A 0.097 0.104 2.464 2.642 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° INCHES MILLIMETERS e 20 11

20 LEAD SMALL OUTLINE

(300 MIL JEDEC SOIC) S20 D E H B A L C A 1 Seating Plane α h x 45°

Rev. 2.00 PERFORMANCE CHARACTERISTICS Graph 1. Relative Accuracy vs. Digital Code LSB NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.