MP7628 EXAR | Alldatasheet

Document overview

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Technical content

Rev. 2.00

FEATURES

  • Readback Capability for all DACs
  • On-Chip Latches for All DACs
  • Linearity Grades to +1/8 LSB
  • Single Supply Voltage (5 Volt)
  • DACs Matched to 1%
  • Four Quadrant Multiplication
  • Microprocessor TTL/CMOS Compatible
  • Latch-Up Free
  • Dual Version: MP7529B

5 V CMOS

Digital-to-Analog Converter

APPLICATIONS

  • Microprocessor Controlled Gain and Attenuation Circuits
  • Microprocessor Controlled/Programmable Power Supplies
  • Hardware Redundant Applications Requiring Data Readback GENERAL DESCRIPTION The MP7628 is a quad 8-bit Digital-to-Analog Converter de- signed using a decoded DAC architecture featuring excellent DAC-to-DAC matching and guaranteed monotonicity. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. The readback function allows the user to poll or read the data latches, eliminating the need for storing information in RAM. In the event the microprocessor power supply is interrupted, it can poll the DACs to establish the last known system state. Data is transferred into any of the four DAC data latches via common 8-bit TTL/CMOS compatible input port. Control inputs DS1 , DS2 and A/B determine which DAC is to be loaded. The MP7628’s load cycle is similar to the write cycle of a random ac- cess memory and the device is bus compatible with most 8-bit microprocessors. The device operates at +5 V power supply and dissipates less than 5mW. All DACs offer excellent four quadrant multiplication charac- teristics with a separate reference input and feedback resistor for each DAC. THREE-STATE BUFFER SIMPLIFIED BLOCK DIAGRAM THREE-STATE BUFFER LATCH A DAC A LATCH B DAC B THREE-STATE BUFFER LATCH C DAC C THREE-STATE BUFFER LATCH D DAC D BI- DIRECTIONAL LINE DRIVER CONTROL LOGIC DB0 (LSB) DATA BUS DB7 (MSB) GND VDD VREFB VREFA R FBA IOUT1A IOUT2A / IOUT2B IOUT1B R FBB R FBC IOUT1C IOUT2C / IOUT2D IOUT1D R FBD R FB VREFDVREFC R FB R FB R FB A/B R/W DS1 DS2

Rev. 2.00

ORDERING INFORMATION

Range Part No. Ceramic Dip MP7628AD Ceramic Dip MP7628BD Ceramic Dip MP7628SD* Ceramic Dip MP7628TD* Plastic Dip MP7628JN –40 to +85°C –55 to +125°C –55 to +125°C Plastic Dip MP7628KN +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1.8 +0.9 +1.8 +0.9 +1.8 +0.9 PLCC MP7628JP +1/2 + 1/2 + 1.8 SOIC MP7628JS +1/2 + 1/2 + 1.8 SOIC MP7628KS +1/4 + 1/4 + 0.9 –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C PLCC MP7628KP–40 to +85°C +1/4 + 1/4 + 0.9 INL (LSB) Gain Error (% FSR) DNL (LSB) *Contact factory for non-compliant military processing PIN CONFIGURATIONS See Packaging Section for Package Dimensions (LSB) DB0 DB1 DB2 DB3 DB4 DB5 DB7 (MSB) DB6 28 Pin CDIP, PDIP (0.600”) D28, N28 VDD VREFA R FBA R FBB VREFB GND VREFC R FBC R FBD VREFD IOUT1A IOUT2A /IOUT2B IOUT1B IOUT1C IOUT2C /IOUT2D IOUT1D 3214 12 13 14 15 16 17 18 28 27 26

28 Pin PLCC

(MSB) R FBD VREFD IOUT1C IOUT2C / IOUT2D IOUT1D R FBC VREFC GND 281 1514 (LSB) 28 Pin SOIC (Jedec, 0.300”) S28 See Pin Out at Left A/B R/W DS1 DS2 DS1 DS2 A/B R/W

Rev. 2.00 PIN OUT DEFINITIONS 1V DD Power Supply 2V REFA Reference Voltage for DAC A 3R FBA Feedback Resistor for DAC A 4I OUT1A Current Output 1 DAC A 5I OUT2A / Current Output 2 DAC A/DAC B IOUT2B 6I OUT1B Current Output 1 DAC B 7R FBB Feedback Resistor for DAC B 8V REFB Reference Voltage for DAC B

9 DB0 Data Input Bit 0 (LSB)

10 DB1 Data Input Bit 1

11 DB2 Data Input Bit 2

12 DB3 Data Input Bit 3

13 DB4 Data Input Bit 4

14 DB5 Data Input Bit 5

15 DB6 Data Input Bit 6

16 DB7 Data Input Bit 7 (MSB)

17 A/B

18 R/W Read/Write

19 DS1 Control 1

20 DS2 Control 2

21 V REFD Reference Voltage for DAC D

22 R FBD Feedback Resistor for DAC D

23 I OUT1D Current Output 1 DAC D

24 I OUT2C / Current Output 2 DAC C/DAC D

25 I OUT1C Current Output 1 DAC C

26 R FBC Feedback Resistor for DAC C

27 V REFC Reference Voltage for DAC C

28 GND Ground

PIN NO. NAME DESCRIPTION

Rev. 2.00

ELECTRICAL CHARACTERISTICS

(VDD = + 5 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 FSR = Full Scale Range Resolution (All Grades) N 8 8 Bits Integral Non-Linearity INL LSB End Point Linearity Spec. (Relative Accuracy) Differential Non-Linearity DNL LSB All grades monotonic over full J, A, S + 1/2 + 1/2 temperature range. Gain Error GE % FSR Using Internal R FB J, A, S + 1.5 + 1.8 Digital Inputs = V INH Gain Temperature Coefficient2 TC GE +2 ppm/ °C ΔGain/ΔTemperature Power Supply Rejection Ratio PSRR + 200 + 400 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Digital Inputs = VINH Output Leakage Current (all) I OUT1 +50 + 200 nA Digital Inputs = V INL REFERENCE INPUT Voltage Range2 +20 + 20 V Input Resistance R IN 12 28 12 28 k Ω DIGITAL INPUTS3 Logic Thresholds VINH 2.4 2.4 V VINL 0.8 0.8 V Input Leakage Current I LKG +1+ 10 µA Input Capacitance2 C IN 3p F DATA BUS OUTPUTS Output Capacitance2 C OUT 7p F Input Leakage Current I LKG +1+ 10 µA ANALOG OUTPUTS Propagation Delay2 500 750 ns From digital input to 90% of final analog output current Output Capacitance2 C OUT 120 pF DAC Inputs all 1’s C OUT 80 pF DAC Inputs all 0’s Glitch Energy2 160 440 nVs Typical for code transition from all 0’s to all 1’s

Rev. 2.00 25°C NOTES: Specifications are subject to change without notice ELECTRICAL CHARACTERISTICS (CON’T) Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments POWER SUPPLY 5 Functional Voltage Range2 VDD 4.5 5.5 4.5 5.5 V Supply Current I DD 50 50 µA All digital inputs = 0 V or all = 5 V SWITCHING CHARACTERISTICS 2, 4 Data Write Time t W 320 400 ns Write Strobe Req. t DSW 200 250 ns Data Hold Time t DHLD 40 50 ns Data Read Time t R 480 600 ns 3-state Hold Time t TSHD 240 300 ns Read Strobe Req. t DSR 320 400 ns 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagrams. 5 Specified values guarantee functionality. Refer to other parameters for accuracy. ABSOLUTE MAXIMUM RATINGS (T A = +25°C unless otherwise noted)1, 2 Digital Input Voltage to GND (2) GND –0.5 to VDD +0.5 V. Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies.

Rev. 2.00 TIMING DIAGRAM READ CYCLE 3-state Data (A) 3-state Data (B) A/B R/W DS1 DS2 BUS (D )N Set up time for BUS, A/B, R/W Minimum DS = low pulse Minimum time between DS = low pulses Data delay time t R = tDSR + tNR = 40 ns t S = 320 ns tDSR (min) = 120 ns tNR = 200 ns tD H tDSR tNR tD tD tS TIMING DIAGRAM WRITE CYCLE Data (A) Data (B) A/B R/W DS1 DS2 Set up time for BUS, A/B, R/W Minimum DS = low pulse Minimum time between DS = low pulses Data delay time t W = tDSW + tNW = 40 ns t S = 200 ns tDSW (min) = 120 ns tNW = 110 ns tD tD A Select B Select Last Data Data (A) Last Data Data (B) DATA (DN ) DAC A OUT DAC B OUT H L H tDSWtS tNW tS + tD tDHLD MODE SELECTION TABLE L H H L WRITE A L H L L WRITE B H L H L WRITE C H L L L WRITE D L H H H READ A L H L H READ B H L H H READ C H L L H READ D L L H L WRITE A & C L L L L WRITE B & D H H X X HOLD A/B/C/D L L H H HOLD A/B/C/D L L L H HOLD A/B/C/D DS1 DS2 A/B R/W MODE DAC L = LOW STATE H = HIGH STATE X = DON’T CARE

Rev. 2.00 INTERFACE LOGIC INFORMATION DAC Selection: All DAC latches share a common 8-bit input port. The control inputs DS1, DS2, A/B select which DAC can accept data from the input port. Mode Selection: Inputs DS and R/W control the operating mode of the selected DAC. See Mode Selection Table on the previous page. Write Mode: When DS and R/W are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0-DB7. Hold Mode: The selected DAC latch retains the data which was present on DB0-DB7 just prior to DS and R/W assuming a high state. Both analog outputs remain at the values corre- sponding to the data in their respective latches. Read Mode: When DS is low and R/W is high, the selected DAC is in the read mode and the data held in the appropriate latch is outputed to the data bus. APPLICATION NOTES Refer to Section 8 for Applications Information

Rev. 2.00 b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– E 0.500 0.610 12.70 15.49 4 E 1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– Q 0.015 0.060 0.381 1.52 3 α 0° 15° 0° 15° –– D b e

28 LEAD CERAMIC DUAL-IN-LINE

(600 MIL CDIP) D28 SYMBOL MIN MAX MIN MAX NOTES INCHES MILLIMETERS S NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 11 4 See Note 1 E α c L Q Seating Plane Base Plane A

Rev. 2.00

28 LEAD PLASTIC DUAL-IN-LINE

(600 MIL PDIP) N28 SYMBOL MIN MAX MIN MAX INCHES B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.380 1.490 35.05 37.85 E 0.585 0.625 14.86 15.88 E 1 0.500 0.610 12.70 15.49 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q 1 0.055 0.070 1.40 1.78 S 0.020 0.100 1.508 2.54 MILLIMETERS Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. D eB 1 A 1 α C E A L B Q 1 Seating Plane S

Rev. 2.00 SYMBOL MIN MAX MIN MAX A 0.097 0.104 2.464 2.642 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.701 0.711 17.81 18.06 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° INCHES MILLIMETERS

28 LEAD SMALL OUTLINE

(300 MIL JEDEC SOIC) S28 e D E H B A L C A 1 Seating Plane α h x 45° 28 15

Rev. 2.00 A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.533 C 0.008 0.012 0.203 0.305 D 0.485 0.495 12.32 12.57 D 1 (1) 0.450 0.454 11.43 11.53 D 2 0.390 0.430 9.91 10.92 D 3 0.300 Ref 7.62 Ref. e1 0.050 BSC 1.27 BSC

28 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC) P28 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS D D 1 D 2 B A A 1 C D D 1 D 3 Seating Plane Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. A 2

Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.