MP7626 EXAR | Alldatasheet

Document overview

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Technical content

Rev. 2.00

FEATURES

  • Four Quadrant Multiplication
  • 16-Bit Monotonicity
  • Low Power Consumption
  • TTL/5 V CMOS Compatible
  • Single-Buffered or Transparent Data inputs
  • Decoded DAC Approach
  • Latch-Up Free
  • 8-Bit Bus Version: MP7636A Microprocessor Compatible Buffered Multiplying 16-Bit Digital-to-Analog Converter

APPLICATIONS

  • Digitally Programmable References
  • Programmable Audio Attenuator
  • High Accuracy Process Control Systems
  • Automatic Test Equipment
  • Easy Interface to 8 and 16-Bit Microprocessor Buses GENERAL DESCRIPTION The MP7626 is a CMOS 16-bit Digital-to-Analog Converter (DAC) that is manufactured using advanced thin film resistors on a double metal CMOS process. It incorporates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 16 bit differential non-linearity is achieved with minimal trimming. Two 8-bit latches (MSB latch and LSB latch) hold the 16-bit data which are converted by the DAC. A 16-bit bus can load both latches in one cycle. An 8-bit bus loads one latch at a time. By making the latches transparent (MSB latch = LSB latch = High) the DAC will continuously convert the BIT1 - BIT16 inputs. SIMPLIFIED BLOCK AND TIMING DIAGRAM D E Q D E Q DB15-DB8 GND DATA 16-Bit Multiplying DAC MSB Latch DB7-DB0 LSB Latch Latch Latch LATCH OUTPUT VDDVREF R FB IOUT1 IOUT2

Rev. 2.00 MP7626KD* + 2+ 2Ceramic Dip

ORDERING INFORMATION

Range Part No. Ceramic Dip MP7626JD* + 4+ 4 MP7626JN–40 to +85°CPlastic Dip +0.1 MP7626KNPlastic Dip –40 to +85°C –40 to +85°C –40 to +85°C +4+ 4 +2+ 2+ 0.1 +0.1 +0.1 MP7626JP MP7626KP –40 to +85°C –40 to +85°C PLCC PLCC +0.1 +0.1 INL (LSB) Gain Error (% FSR) DNL (LSB) *Recommend using MP7626KN or JN PIN CONFIGURATION MSB LATCH DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 (MSB) DB15 DB3 DB2 DB1 DB0 (LSB) LSB LATCH GND 24 Pin PDIP, CDIP (0.600”) N24, D24, C24 11 14 12 13 VDD IOUT1 IOUT2 R FB VREF 3214 12 13 14 15 16 17 18 28 27 26

28 Pin PLCC

(MSB) DB15 V REF R FB IOUT2 IOUT1 VDD MSB LATCH DB3 DB2 DB1 DB0 (LSB) LSB LATCH GND DB4 DB5 DB6See Packaging Section for Package Dimensions PIN OUT DEFINITIONS 1 26 DB4 Data Input Bit 4 2 27 DB5 Data Input Bit 5 3 28 DB6 Data Input Bit 6 4 1 DB7 Data Input Bit 7 5 2 DB8 Data Input Bit 8 6 5 DB9 Data Input Bit 9 7 6 DB10 Data Input Bit 10 8 7 DB11 Data Input Bit 11 9 8 DB12 Data Input Bit 12 10 9 DB13 Data Input Bit 13 11 10 DB14 Data Input Bit 14 12 11 DB15 Data Input Bit 15 (MSB) DIP PLCC DESCRIPTION 13 13 V REF Reference Input Voltage 14 14 R FB Internal Feedback Resistor Pin 15 15 I OUT2 Current Output 2 16 16 I OUT1 Current Output 1 17 17 V DD Power Supply 18 19 GND Ground 19 20 LSB LSB Latch Enable 20 21 MSB MSB Latch Enable 21 22 DB0 Data Input Bit 0 (LSB) 22 23 DB1 Data Input Bit 1 23 24 DB2 Data Input Bit 2 24 25 DB3 Data Input Bit 3 DESCRIPTIONNAME DIP PLCC NAME

Rev. 2.00

ELECTRICAL CHARACTERISTICS

(VDD = + 15 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 FSR = Full Scale Range Resolution (All Grades) N 16 16 Bits Relative Accuracy INL LSB Best Fit Straight Line Spec. 4+ 4 (Max INL – Min INL) / 2 K+ 2+ 2 Differential Non-Linearity DNL LSB J+ 4+ 4 K+ 2+ 2 Gain Error GE + 0.1 + 0.1 % FSR Using Internal R FB Gain Temperature Coefficient2 TC GE +2 ppm/ °C ΔGain/ΔTemperature Power Supply Rejection Ratio PSRR + 50 + 50 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Output Leakage Current I OUT +10 + 200 nA I OUT1 DYNAMIC PERFORMANCE 2 R L=100Ω , CL=13pF Current Settling Time t S 2 µs Full Scale Change to 0.1% AC Feedthrough at IOUT1 FT 2 mV p-p V REF = 10kHz, 20 Vp-p, sinewave REFERENCE INPUT Input Resistance R IN 2.5 7.5 2.5 7.5 k Ω DIGITAL INPUTS3 Logical “1” Voltage V IH 3.0 2.4 3.0 V Logical “0” Voltage V IL 0.8 0.8 V Input Leakage Current I LKG +1+ 1 µA Input Capacitance2 Data C IN 5p F Control C IN 5p F ANALOG OUTPUTS 2 Output Capacitance C OUT1 280 pF DAC Inputs all 1’s C OUT1 120 pF DAC Inputs all 0’s C OUT2 100 pF DAC Inputs all 1’s C OUT2 240 pF DAC Inputs all 0’s POWER SUPPLY Functional Voltage Range5 VDD 4.5 16.5 5.0 16.5 V Supply Current I DD 1 1 mA All digital inputs = 0 V or all = 5 V

Rev. 2.00 25°C NOTES: Specifications are subject to change without notice ELECTRICAL CHARACTERISTICS (CON’T) Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments SWITCHING CHARACTERISTICS 2, 4 Data Valid to Write Set-Up Time t DS 250 ns Write Strobe Width t SW 125 ns 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. 5 Specified values guarantee functionality. Refer to other parameters for accuracy. ABSOLUTE MAXIMUM RATINGS (T A = +25°C unless otherwise noted)1, 2 DC Voltage Applied to IOUT1 or IOUT2 GND –0.5 to +17 V. . Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATION NOTES Refer to Applications Section for Additional Information LATCH CONTROL MSB LATCH LSB LATCH FUNCTION 0 0 Data Latched (Held) 1 0 Transfer (DB15-DB8) to DAC 0 1 Transfer (DB7-DB0) to DAC 1 1 Transparent Mode ÉÉÉ ÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉ ÉÉ Data Changing Data Stable DATA LATCH OUTPUT tS tDS tSW TIMING DIAGRAM

Rev. 2.00 PERFORMANCE CHARACTERISTICS Graph 1. Relative Accuracy vs. Digital Code LSB APPLICATION NOTES Refer to Section 8 for Applications Information

Rev. 2.00

24 LEAD PLASTIC DUAL-IN-LINE

(600 MIL PDIP) N24 SYMBOL MIN MAX MIN MAX INCHES A –– 0.225 –– 5.72 B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.160 1.290 29.46 32.77 E 0.585 0.625 14.86 15.88 E 1 0.500 0.610 12.70 15.49 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q 1 0.055 0.070 1.40 1.78 S 0.040 0.098 1.02 2.49 MILLIMETERS Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. D eB 1 A 1 α C E A L B Q 1 Seating Plane S

Rev. 2.00 b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– E 0.500 0.610 12.70 15.49 4 E 1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.120 0.200 3.05 5.08 –– Q 0.015 0.075 0.381 1.91 3 α 0° 15° 0° 15° –– D b e b

24 LEAD CERAMIC DUAL-IN-LINE

(600 MIL CDIP) D24 SYMBOL MIN MAX MIN MAX NOTES INCHES MILLIMETERS S NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 11 2 See Note 1 E α c L Q Seating Plane Base Plane A

Rev. 2.00 b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– E 0.500 0.610 12.70 15.49 4 E 1 0.590 0.620 14.99 15.75 7 e 0.100 BSC 2.54 BSC 5 L 0.120 0.200 3.05 5.08 –– Q 0.015 0.075 0.381 1.91 3 D b e

24 LEAD CERAMIC SIDE-BRAZED DUAL-IN-LINE

(600 MIL S/B DIP) C24 SYMBOL MIN MAX MIN MAX NOTES INCHES MILLIMETERS 121 S E c NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. Applies to all four corners. 7. E 1 shall be measured at the centerline of the leads. L Q Seating Plane Base Plane A

Rev. 2.00 A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.533 C 0.008 0.012 0.203 0.305 D 0.485 0.495 12.32 12.57 D 1 (1) 0.450 0.454 11.43 11.53 D 2 0.390 0.430 9.91 10.92 D 3 0.300 Ref 7.62 Ref. e1 0.050 BSC 1.27 BSC

28 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC) P28 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS D D 1 D 2 B A A 1 C D D 1 D 3 Seating Plane Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. A 2

Rev. 2.00 Notes

Rev. 2.00 Notes

Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.