MP7614 EXAR | Alldatasheet

Document overview

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Technical content

Rev. 2.00

FEATURES

  • Full Four-Quadrant Multiplication
  • Excellent Stability Over Temperature and Time
  • Guaranteed Monotonic
  • TTL/5 V CMOS Compatible

15 V CMOS

Digital-to-Analog Converter

  • Low Sensitivity to Output Amplifier VOS
  • Low Glitch Energy
  • 16-Bit Version: MP7616 GENERAL DESCRIPTION The MP7614 is a high density 14-bit CMOS multiplying Digi- tal-to-Analog Converter. Silicon nitride passivation and un- trimmed silicon chromium resistors have been combined to pro- vide long term stability and reliability. Using the most significant bit (MSB) segmentation technique, the MP7614 features 13-bit (0.012%) differential and 12-bit (0.01%) integral linearity. To achieve 13-bit linearity without laser trim, the MP7614 digi- tally decodes the four MSB’s into 15 equal current sources, rather than the standard binary-weighted sources. Each resis- tor contributes only 1/16 full scale output thus reducing the matching accuracy requirement of the resistor and CMOS switches from 0.0015% to 0.006%. The decoding technique achieves an eightfold improvement in differential linearity stability over temperature, an eightfold im- provement in relative accuracy due to aging effects (long term stability), a fourfold improvement in glitch amplitude, and a ten- fold reduction in sensitivity to output amplifier offset voltage. SIMPLIFIED BLOCK DIAGRAM 4 to 15 Decoder R RRRRRRRRRRRRRR 10-Bit DAC (LSB) To 10-Bit DAC To Switches VDD VREF IOUT2 IOUT1 R FB (MSB) 45 1 4 GND

Rev. 2.00

ORDERING INFORMATION

Range Part No. Ceramic Dip MP7614KD Ceramic Dip MP7614TD* Plastic Dip MP7614JN Plastic Dip MP7614KN –40 to +85°C –55 to +125°C +0.8 +0.8 +0.8 +0.8 –40 to +85°C –40 to +85°C SOIC MP7614KS +0.8–40 to +85°C +2+ 2 INL (LSB) Gain Error (% FSR) DNL (LSB) *Contact factory for non-compliant military processing PIN CONFIGURATIONS GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 14 (LSB) BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 20 Pin CDIP, PDIP (0.300”) D20, N20 IOUT1 IOUT2 R FB VREF VDD 201 1110 20 Pin SOIC (Jedec, 0.300”) S20 BIT 14 (LSB) BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 R FB VREF VDDGND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 I OUT1 IOUT2 See Packaging Section for Package Dimensions 1I OUT1 Current Output 1 2I OUT2 Current Output 2

3 GND Ground

4 BIT 1 Data Input Bit 1 (MSB)

5 BIT 2 Data Input Bit 2

6 BIT 3 Data Input Bit 3

7 BIT 4 Data Input Bit 4

8 BIT 5 Data Input Bit 5

9 BIT 6 Data Input Bit 6

10 BIT 7 Data Input Bit 7

PIN NO. NAME DESCRIPTION

11 BIT 8 Data Input Bit 8

12 BIT 9 Data Input Bit 9

13 BIT 10 Data Input Bit 10

14 BIT 11 Data Input Bit 11

15 BIT 12 Data Input Bit 12

16 BIT 13 Data Input Bit 13

17 BIT 14 Data Input Bit 14 (LSB)

19 V REF Reference Input Voltage

20 R FB Internal Feedback Resistor

PIN NO. NAME DESCRIPTION

Rev. 2.00

ELECTRICAL CHARACTERISTICS

(VDD = + 15 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 FSR = Full Scale Range Resolution (All Grades) N 14 14 Bits Integral Non-Linearity5 INL LSB Best Fit Straight Line Spec. (Relative Accuracy) (Max INL – Min INL) / 2 J, S + 4+ 4 K, T + 2+ 2 Differential Non-Linearity5 DNL LSB J, S + 4+ 4 K, T + 2+ 2 Gain Error GE 0.8 + 0.8 % FSR Using Internal R FB Gain Temperature Coefficient2 TC GE +1.0 + 2.0 ppm/ °C ΔGain/ΔTemperature Non-Linearity Tempco2 +0.2 + 0.5 ppm/ °C Differential Linearity Tempco2 +0.2 + 0.5 ppm/ °C Power Supply Rejection Ratio PSRR + 5+ 50 + 50 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Output Leakage Current6 IOUT +1+ 10 + 200 nA DYNAMIC PERFORMANCE 2 Current Settling Time t S 2 µs To 0.01% of FSR; all digital inputs low to high and high to low Feedthrough at IOUT1 FT 1 2 mV p-p V REF = 20 V p-p @ 10 kHz REFERENCE INPUT Input Resistance R IN 13 1 0 1 1 0 k Ω DIGITAL INPUTS3 Logical “1” Voltage V IH 3.0 2.4 3.0 V Logical “0” Voltage V IL 0.8 0.8 V Input Leakage Current I LKG +1.0 + 1.0 µA ANALOG OUTPUTS 2 Output Capacitance C OUT1 100 pF DAC Inputs all 1’s C OUT1 50 pF DAC Inputs all 0’s C OUT2 50 pF DAC Inputs all 1’s C OUT2 100 pF DAC Inputs all 0’s POWER SUPPLY 4 Functional Voltage Range2 VDD 4.5 15 16 4.5 16 V Supply Current I DD 0.4 4 4 mA All digital inputs = 0 V or all = 5 V

Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) NOTES: Specifications are subject to change without notice 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 Specified values guarantee functionality. Refer to other parameters for accuracy. 5 Linearity error is degraded by 65µV for every mV of voltage offset at output amplifier. 6 Output leakage current refers to IOUT1 . 1 LSB of current constantly flows into IOUT2 (30nA at 5 kΩ input impedance, VREF = +10 V) due to ladder termination into IOUT2 . ABSOLUTE MAXIMUM RATINGS (T A = +25°C unless otherwise noted)1, 2 Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATION NOTES Refer to Section 8 for Applications Information

Rev. 2.00 b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– E 0.220 0.310 5.59 7.87 4 E 1 0.290 0.320 7.37 8.13 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– Q 0.015 0.070 0.381 1.78 3 α 0° 15° 0° 15° –– D be 1b

20 LEAD CERAMIC DUAL-IN-LINE

(300 MIL CDIP) D20 SYMBOL MIN MAX MIN MAX NOTES INCHES MILLIMETERS S 1 S NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 11 0 11See Note 1 E α c L Q Seating Plane Base Plane A

Rev. 2.00

20 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP) N20 D eB 1 A 1 α C E A L B Q 1 Seating Plane SYMBOL MIN MAX MIN MAX INCHES A –– 0.200 –– 5.08 B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.945 1.060 24.0 26.92 E 0.295 0.325 7.49 8.26 E 1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q 1 0.055 0.070 1.40 1.78 S 0.040 0.080 1.02 2.03 MILLIMETERS S Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only.

Rev. 2.00 SYMBOL MIN MAX MIN MAX A 0.097 0.104 2.464 2.642 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° INCHES MILLIMETERS e 20 11

20 LEAD SMALL OUTLINE

(300 MIL JEDEC SOIC) S20 D E H B A L C A 1 Seating Plane α h x 45°

Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.