MP7610 EXAR | Alldatasheet

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Technical content

Rev. 4.01 1EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z(510) 668-7000 z(510) 668-7017E1998

FEATURES

  • Eight Independent 14-Bit DACs with Output Amplifiers
  • Low Power 320 mW (typ.)
  • Serial Digital Data and Address Port (3-Wire Standard)
  • 14-Bit Resolution, 12-Bit Accuracy
  • Extremely Well Matched DACs
  • Extremely Low Analog Ground Current (<60mA/Channel)
  • +10 V Output Swing with +11.4 V Supplies
  • Zero Volt Output Preset (Data = 10 .. 00)
  • Rugged Construction -- Latch-Up Free
  • Parallel Version: MP7611 Octal 14-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address mP Control Logic

APPLICATIONS

  • Data Acquisition Systems
  • ATE
  • Process Control
  • Self-Diagnostic Systems
  • Logic Analyzers
  • Digital Storage Scopes
  • PC Based Controller/DAS June 1998-3 GENERAL DESCRIPTION The MP7610 provides eight independent 14-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a 3-wire standard serial digital address and data port. The output amplifier is capable of sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30ms (typ.). The MP7610 is equipped with a serial data (3-wire standard) m-processor logic interface to reduce pin count, package size, and board space. Built using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR’s patented thin-film resistor process which exhibits excellent long term stability and reliability. SIMPLIFIED BLOCK DIAGRAM VO0 VO7 SDO VRP VRN DAC0 DAC7 VRP VRN D Q XR XE LAT0 LAT7 D Q XR XE RST VRN VRP Tri-State Buffer XE0 - XE7 4 to 16 Decoder Not Used LD 4SDI CLK LD LAT D QEN LATD Q EN A0 to A3D0 to D13 18-Bit Shift Register VEE VEE VCC VCC AGND AGND VREF DGND DVDD VRP XE0 XE7 LD

Rev. 4.01

ORDERING INFORMATION

(LSB)Part No. PLCC --40 to +85°C MP7610AP ¦8 PLCC --40 to +85°C MP7610BP ¦4 Res. (Bits) DNL (LSB) FSE (LSB) ¦32 ¦24 SOIC --40 to +85°C MP7610AS ¦8 SOIC --40 to +85°C MP7610BS ¦2 ¦32 ¦16 PLCC 0 to +70°C MP7610CP ¦214 ¦2 ¦16 SOIC 0 to +70°C MP7610CS ¦414 ¦3 ¦24 PIN CONFIGURATIONS 28 Pin SOIC (Jedec, 0.346”) VO0 VO1 VO2 VO3 VEE VCC VREF VCC VEE VO4 VO5 VO6 DGND DVDD N/C or DVDD N/C SDO SDI CLK AGND 281 1514 VO7 AGND N/C N/C N/C N/C LD RST

44 Pin PLCC

See the following page for pin descriptions

Rev. 4.01 PIN DESCRIPTION SOIC Pin # PLCC Pin # Symbol Description 1 2 AGND Analog Ground 2 3 VO0 DAC 0 Output 3 4 VO1 DAC 1 Output 4 5 VO2 DAC 2 Output 5 6 VO3 DAC 3 Output 6 7 VEE Analog Negative Power Supply (--12 V) 7 9 VCC Analog Positive Power Supply (+12 V) 8 12 VREF Voltage Reference Input (+5 V) 9 13 VCC Analog Positive Power Supply (+12 V) 10 15 VEE Analog Negative Power Supply (--12 V) 11 18 VO4 DAC 4 Output 12 19 VO5 DAC 5 Output 13 20 VO6 DAC 6 Output 14 21 VO7 DAC 7 Output 15 24 AGND Analog Ground

16 N/C No Connection

17 26 RST Reset all DACs to 0 V Output

18 N/C No Connection

19 29 LD Load Signal; Load Data to Selected DAC 20 31 CLK Serial Data Clock 21 32 SDI Serial Data Input 22 34 SDO Shift Register Serial Output

23 N/C No Connection

24 37 N/C No Connection or DVDD 25 40 DVDD Digital Positive Power Supply (+5 V)

26 N/C No Connection

27 1, 8, 10, 11, 14, 16, 17, 22, 23, 25, 27, 28, 30, 33, 35, 36, 38, 39, 41, 42, 43 N/C No Connection 28 44 DGND Digital Ground

Rev. 4.01 25°C Tmin to Tmax

ELECTRICAL CHARACTERISTICS

VCC = +12 V, VEE = --12 V, VREF = 5 V, DVDD = 5.0 V, T = 25°C, Output Load = 5kW (unless otherwise noted) Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) N 14 Bits Integral Non-Linearity INL LSB End Point Linearity Spec (Relative Accuracy) A ¦8 ¦8 B ¦4 ¦4 C ¦2 ¦2.5 Differential Non-Linearity DNL LSB A ¦4 ¦4 B ¦3 ¦3 C ¦2 ¦2.5 Positive Full Scale Error +FSE LSB A 24 ¦32 ¦32 B 16 ¦24 ¦24 C 12 ¦16 ¦16 Positive Full Scale Error D+FSE/ 4 ppm/°C 0°C to 85°C Temperature Coefficient DT Negative Full Scale Error --FSE LSB A 24 ¦32 ¦32 B 16 ¦24 ¦24 C 12 ¦16 ¦16 Negative Full Scale Error D--FSE/ 4 ppm/°C 0°C to 85°C Temperature Coefficient DT Bipolar Zero Offset ZOFS LSB A ¦16 ¦16 B ¦12 ¦12 C ¦12 ¦12 Bipolar Zero Offset DZOFS/ 2 ppm/°C 0°C to 85°C Temperature Coefficient DT INL Matching DINL LSB A ¦8 ¦8 B ¦6 ¦6 C ¦6 ¦6 All Channels Maximum Error ME LSB with DAC 0 adjusted to minimum error A ¦16 ¦16 B ¦8 ¦8 C ¦6 ¦6 Bipolar Zero Matching DZOFS LSB A ¦16 ¦16 B ¦12 ¦12 C ¦12 ¦12 Full Scale Error Matching DFSE LSB A ¦16 ¦16 B ¦12 ¦12 C ¦12 ¦12

Rev. 4.01 25°C Tmin to Tmax ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments DYNAMIC PERFORMANCE Voltage Settling from LD tsd 30 50 50 ms ZS to FS (20 V Step) to VDAC Out1 5k, 50pF load Channel-to-Channel Crosstalk6 CT 0.04 LSB DC Digital Feedthrough1, 6 Q --70 dB CLK and Data to VOUTi Power Supply Rejection Ratio PSRR 5 ppm/% DVEE & DVCC = ±5%, ppm of FS REFERENCE INPUTS Impedance of VREF REF 350 700 1.05k 350 1.05k W See Application Hints for Driving the reference input VREF Voltage1, 2 VREF 3.5 6 V DIGITAL INPUTS3 Logic High VIH 2.4 V Logic Low VIL 0.8 V Input Current IL ±10 mA Input Capacitance1 CL 8 pF ANALOG OUTPUTS Output Swing --VEE +1.4 VCC --1.4 V Output Drive Current --5 5 mA Output Impedance RO 1 W Output Short Circuit Current ISC 25 mA +FS to AGND 30 mA +FS to VEE 40 mA --FS to AGND 55 mA --FS to VCC DIGITAL OUTPUTS Output High Voltage VOH 4.5 V Output Low Voltage VOL 0.5 V POWER SUPPLIES VCC Voltage5 VCC VREF+1.5 12 12.75 VREF+1.5 12.75 V VEE Voltage5 VEE --12.75 --12 --5 --12.75 --5 V DVDD Voltage DVDD 4.5 5 5.5 4.5 5.5 V Positive Supply Current ICC 8 10 10 mA Bipolar zero Negative Supply Current IEE 15 20 20 mA Bipolar zero Digital Supply Current IDD 2 2 mA Bipolar zero Power Dissipation PDISS 320 420 450 mW Bipolar zero ANALOG GROUND CURRENT Per Channel1 IAGND ±60 mA See Application Notes DIGITAL TIMING SPECIFICATIONS1,4 VIL = 0, VIH = 5.0, CL = 20 pF Input Clock Pulse Width tCH, tCL 60 ns Data Setup Time tDS 15 ns Data Hold Time tDH 15 ns CLK to SDO Propagation Delay tPD 40 ns DAC Register Load Pulse Width tLD 45 ns Preset Pulse Width tPR 65 ns Clock Edge to Load Time tCKLD1 140 ns Note: tLD and tCKLD2 cannot both tCKLD2 0 be min. since tCKLD1=tCKLD2+tLD LD Falling Edge to SDO tHZ1 50 ns Tri-state Enable

Rev. 4.01 25°C Tmin to Tmax ELECTRICAL CHARACTERISTICS (CONT’D) Specifications are subject to change without notice Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments DIGITAL TIMING SPECIFICATIONS1, 4 (CONT’D) LD Rising Edge to SDO tHZ2 50 ns Tri-state Disable LD Rising Edge to CLK Enable tLDCK 50 ns LD Set-up Time with Respect tLDSU 45 ns to CLK NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 2 and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < ¦2£VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 (Functionality guaranteed for ¦0.5 V only) Digital Input & Output Voltage VCC, VEE, DVDD, AGND, DGND (provided that power dissipation of the package spec is not exceeded) Operating Temperature Range Maximum Junction Temperature --65°C to 150°C. . . Package Power Dissipation Rating @ 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings”may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. APPLICATION NOTES NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to ¦300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than ¦1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths.

Table 1. Digital Function Truth Table Note: For timing information See Electrical Characteristics. Table 2. MP7610 Ideal DAC Output vs. Input Code

163842 O O O 10 · (--1 + ) = 0

Rev. 4.01 PERFORMANCE CHARACTERISTICS Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF 11 V 0 V --11 V 2.5mV 0 V --2.5mV VOUT VOUT Settling 50ms/Division Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the differ- ence between the output and the ideal output. Graph 2. Linearity with VREF = 5 V, All DACs, All Codes 0 16384 --4 14-BIT LSB CODE

Rev. 4.01 Graph 3. DAC 0 INL vs. VREF Graph 4. DAC 0 DNL vs. VREF Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = ¦10 Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = ¦9 Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = ¦8 Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = ¦7 0 16384 --4 14-BIT LSB CODE 0 16384 --4 14-BIT LSB CODE 0 16384 --4 14-BIT LSB CODE 0 16384 --4 14-BIT LSB CODE

Figure 9. Circuit for Determining Typical Analog Output Pulse Response

Rev. 4.01

44 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC) Rev. 1.00 D A D D1 A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ. 12.70 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS B e Seating Plane 2 44 Note: The control dimension is the inch column 45° x H2 45° x H1 C R

Rev. 4.01 SYMBOL MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.706 0.718 17.93 18.24 E 0.340 0.350 8.64 8.89 e 0.050 BSC 1.27 BSC H 0.460 0.485 11.68 12.32 L 0.016 0.050 0.40 1.27 a 0° 8° 0° 8° INCHES MILLIMETERS

28 LEAD SMALL OUTLINE

(350 MIL JEDEC SOIC) Rev. 1.00 e D E H B A L C Seating Plane a 28 15 Note: The control dimension is the millimeter column

Rev. 4.01 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright 1998 EXAR Corporation Datasheet June 1998 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.