MP7543

MP7543 EXAR | Alldatasheet

Document overview

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Technical content

Rev. 2.00

5 V CMOS

Digital-to-Analog Converter

FEATURES

• 12-Bit DAC with Serial Digital Input Interface
• Nonlinearity +1/2 LSB from Tmin to Tmax
• Lowest Sensitivity to Amplifier VOS
• Low Output Capacitance
• Full 4-Quadrant Multiplication
• Latch-Up Free
• Asynchronous CLEAR Input
• Serial Load On Positive or Negative Strobes
• +5 V Supply Operation
• 3 V Version: MP75L43
• 4-Bit Parallel Version: MP7542 BENEFITS
• Compatible with Serial Addressing Systems GENERAL DESCRIPTION The MP7543 is a precision, 12-bit CMOS 4-quadrant multi- plying Digital-to-Analog Converter designed for serial interface applications. The MP7543 consists of two 12-bit registers, control logic and a 12-bit multiplying D/A converter. The input register (register A) is a 12-bit serial-in parallel-out shift register. Serial data at the SR1 pin is clocked into Register A on the leading or trailing edge (user selected) of the strobe input, with the MSB loaded first. Register B is a 12-bit parallel-in parallel-out register that follows register A. The contents of register A are loaded into register B under control of the Load inputs. A CLEAR input is provided for the asynchronous resetting of register B to all 0’s. The MP7543 is manufactured using an advanced thin film monolithic CMOS fabrication process. A unique decoding tech- nique is utilized yielding excellent accuracy and stability. 12-bit linearity is achieved without laser trimming. The MP7543 reduces the additional linearity errors due to output amplifier offset to only 330 µV per millivolt of offset - half the value of a standard R-2R CMOS DAC design approach. SIMPLIFIED BLOCK DIAGRAM 12-Bit D/A Converter DAC Register B Register A 12-Bit Shift Register Load STB1 STB4 STB2 AGND SRI DGND VREF R FB VDD IOUT1 IOUT2 CLR LD1 LD2 STB3

Rev. 2.00

ORDERING INFORMATION

Range Part No. Ceramic Dip MP7543AD Ceramic Dip MP7543BD Ceramic Dip MP7543TD* Plastic Dip MP7543JN Plastic Dip MP7543KN PLCC MP7543JP PLCC MP7543KP –40 to +85°C –40 to +85°C –55 to +125°C SOIC MP7543JS SOIC MP7543KS +1/2 +1/2 +1/2 +1/2 +1/2 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C Ceramic Dip MP7543SD*–55 to +125°C +1+ 2+ 14.5 INL (LSB) Gain Error (LSB) DNL (LSB) *Contact factory for non-compliant military processing PIN CONFIGURATIONS See Packaging Section for Package Dimensions AGND STB1 N/C SRI STB2 DGND STB4 16 Pin CDIP, PDIP (0.300”) D16, N16 3 2 1 20 19 9 1 01 11 21 3

20 Pin PLCC

16 Pin SOIC (Jedec, 0.300”) S16 AGND STB1 SRI STB2 STB4 DGND VDD VREF R FB N/C N/C N/C N/C N/C IOUT1 IOUT2 IOUT1 IOUT2 CLR LD1 LD2 STB3 LD2 STB3 CLR LD1

Rev. 2.00 1 N/C No Connection. 2I OUT1 DAC current output pin. Normally terminated at op amp virtual ground. 3I OUT2 DAC current output pin. Normally terminated at AGND. 4 AGND Analog Ground. 5 STB1 Register A Strobe 1 input, See Table 1. 6 N/C No Connection.

7 LD1

DAC Register B Load 1 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B. 8 N/C No Connection. 9 SR1 Serial Data Input to Register A.

10 STB2 Register A Strobe 2 input,

See Table 1. 11 N/C No Connection.

12 LD2

DAC Register B Load 2 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B.

13 STB3

Register A Strobe 3 input, See Table 1. 14 STB4 Register A Strobe 4 input, See Table 1. 15 DGND Digital Ground. 16 N/C No Connection.

17 CLR

Register B CLEAR input (active LOW), can be used to asynchronously reset Register B to 0000 0000 0000. 18 V DD +5 V Supply Input. 19 V REF Reference input. Can be positive or negative DC voltage or AC signal. 20 R FB DAC Feedback Resistor. PIN OUT DEFINITIONS 1I OUT1 DAC current output pin. Normally terminated at op amp virtual ground. 2I OUT2 DAC current output pin. Normally terminated at AGND. 3 AGND Analog Ground.

4 STB1 Register A Strobe 1 input,

See Table 1. 5 LD1 DAC Register B Load 1 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B. 6 N/C No Connection. 7 SRI Serial Data Input to Register A.

8 STB2 Register A Strobe 2 input,

See Table 1. 9 LD2 DAC Register B Load 2 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B.

10 STB3

Register A Strobe 3 input, See Table 1. 11 STB4 Register A Strobe 4 input, See Table 1. 12 DGND Digital Ground.

13 CLR

Register B CLEAR input (active LOW), can be used to asynchronously reset Register B to 0000 0000 0000. 14 V DD +5 V Supply Input. 15 V REF Reference input. Can be positive or negative DC voltage or AC signal. 16 R FB DAC Feedback Resistor. PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION PDIP, CDIP and SOIC PLCC

Rev. 2.00

ELECTRICAL CHARACTERISTICS

(VDD = + 5 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 Resolution (All Grades) N 12 12 Bits Integral Non-Linearity INL LSB Best Fit Straight Line Spec. (Relative Accuracy) (Max INL – Min INL) / 2 J, A, S + 1+ 1 Differential Non-Linearity DNL LSB Monotonicity: J, A, S + 2+ 2 11 Bits Guaranteed K, B, T + 1+ 1 12 Bits Guaranteed Gain Error GE LSB Using Internal R FB Gain Temperature Coefficient2 TC GE +2 ppm/ °C ΔGain/ΔTemperature Power Supply Rejection Ratio PSRR + 50 + 100 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Output Leakage Current I OUT nA J, K, A, B + 10 + 10 S, T + 10 + 200 DYNAMIC PERFORMANCE Current Output Settling Time2 tS 22 µsR L=100Ω , CL=13pF Full Scale Output Settles to 1/2 LSB of Final Value AC Feedthrough at I OUT1 2 FT 2.5 2.5 mV p-p V REF = 10kHz, 20 Vp-p, sinewave REFERENCE INPUT Input Resistance R IN 5 10 20 5 20 k Ω DIGITAL INPUTS3 Logical “1” Voltage V IH 3.0 3.0 V Logical “0” Voltage V IL 0.8 0.8 V Input Leakage Current I LKG +1+ 1 µA ANALOG OUTPUTS 2 Output Capacitance C OUT1 260 260 pF DAC Inputs all 1’s C OUT1 100 100 pF DAC Inputs all 0’s C OUT2 50 50 pF DAC Inputs all 1’s C OUT2 210 210 pF DAC Inputs all 0’s POWER SUPPLY Supply Voltage V DD 4.75 5.25 4.75 5.25 V V DD = +5 V +5% for specified performance Supply Current I DD 2.5 2.5 mA All digital inputs = 0 V or all = 5 V

Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) 25°C Tmin to Tmax NOTES: Specifications are subject to change without notice 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments SWITCHING CHARACTERISTICS 2, 4 Serial Input to Strobe Set-up Time tDS1 50 100 ns STB1 used as a strobe Serial Input to Strobe Set-up Time tDS4 0 0 ns STB4 used as a strobe Serial Input to Strobe Set-up Time tDS3 0 0 ns STB3 used as a strobe Serial Input to Strobe Set-up Time tDS2 20 40 ns STB2 used as a strobe Serial Input to Strobe Hold Time tDH1 30 60 ns STB1 used as a strobe Serial Input to Strobe Hold Time tDH4 80 160 ns STB4 used as a strobe Serial Input to Strobe Hold Time tDH3 80 160 ns STB3 used as a strobe Serial Input to Strobe Hold Time tDH2 60 120 ns STB2 used as a strobe SRI Data Pulse Width t SRI 80 160 ns STB1 Pulse Width t STB1 80 160 ns STB4 Pulse Width t STB4 100 200 ns STB3 Pulse Width t STB3 100 200 ns STB2 Pulse Width t STB2 80 160 ns Load Pulse Width t LD1, 2 150 300 ns Minimum time between strobing t ASB 00 n s Reg. A and loading Reg. B CLR pulse width t CLR 200 400 ns ABSOLUTE MAXIMUM RATINGS (T A = +25°C unless otherwise noted)1, 2, 3 Digital Input Voltage to GND (2) GND –0.5 to VDD +0.5 V. (Functionality Guaranteed +0.5 V) Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 GND refers to AGND and DGND.

1. CLR = 0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A.
2. Serial data is loaded into Register A MSB first, on edges shown is positive edge, is negative edge.
3. 0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.

Table 1. Truth Table

Rev. 2.00

16 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP) N16 D e B 1 A 1 α C E A L B Q 1 Seating Plane SYMBOL MIN MAX MIN MAX INCHES A –– 0.200 –– 5.08 B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.745 0.785 18.92 19.94 E 0.295 0.325 7.49 8.26 E 1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q 1 0.055 0.070 1.40 1.78 S 0.020 0.080 0.51 2.03 MILLIMETERS Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. S

Rev. 2.00 b 0.014 0.023 0.356 0.584 –– b 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– E 0.220 0.310 5.59 7.87 4 E 0.290 0.320 7.37 8.13 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– Q 0.015 0.060 0.381 1.52 3 α 0° 15° 0° 15° –– D b e

16 LEAD CERAMIC DUAL-IN-LINE

(300 MIL CDIP) D16 SYMBOL MIN MAX MIN MAX NOTES INCHES MILLIMETERS S 1 S NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 9See Note 1 E α c A L Q Seating Plane Base Plane

Rev. 2.00 SYMBOL MIN MAX MIN MAX A 0.097 0.104 2.46 2.64 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.482 C 0.0091 0.0125 0.231 0.318 D 0.402 0.412 10.21 10.46 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° INCHES MILLIMETERS

16 LEAD SMALL OUTLINE

(300 MIL JEDEC SOIC) S16 e 16 9 D E H B A L C A 1 Seating Plane α h x 45°

Rev. 2.00 A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.533 C 0.008 0.012 0.203 0.305 D 0.385 0.395 9.78 10.03 D 1 (1) 0.350 0.354 8.89 8.99 D 2 0.290 0.330 7.37 8.38 D 3 0.200 Ref 5.08 Ref. e1 0.050 BSC 1.27 BSC

20 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC) P20 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS D D 1 D 2 B A A 1 C D D 1 Seating Plane D 3 Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. A 2

Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.