MP7542 EXAR | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Rev. 2.00
FEATURES
- 12-Bit DAC with a 4-Bit Parallel Address for 4 & 8-Bit Microprocessor or Microcontroller Interface
- Nonlinearity +1/2 LSB Tmin to Tmax
- Latch-Up Free
- Low Sensitivity to Output Amplifier VOS
- Low Output Capacitance
5 V CMOS
4-Bit Input, 12-Bit Digital-to-Analog Converter
- +5 V Supply Operation
- Low Power Consumption: 40mW Max.
- Low Cost
- Serial Version: MP7543 GENERAL DESCRIPTION The MP7542 is a precision, 12-bit CMOS 4-quadrant multi- plying Digital-to-Analog Converter designed for direct interface to 4 and 8-bit microprocessors. The MP7542 consists of three 4-bit registers, a 12-bit DAC register, address decoding logic, and a 12-bit CMOS multiplying DAC. Data is loaded into the data registers in three 4-bit nibbles and subsequently transferred to the 12-bit DAC register. All data loading or data transfer operations are identical to the WRITE cycle of a static RAM. A CLEAR input allows the 12-bit DAC reg- ister to be reset to all zeros. The MP7542 is manufactured using advanced thin-film on monolithic double metal CMOS fabrication process. A unique decoding technique is utilized yielding excellent accuracy and stability. The MP7542 reduces the additional linearity errors due to output amplifier offset to only 330 µV per millivolt of offset versus 670 µV for the standard R-2R ladder CMOS DACs. SIMPLIFIED BLOCK DIAGRAM 12-Bit Multiplying DAC 12-Bit DAC Register H-Byte Data Register M-Byte Data Register L-Byte Data Register Address Decode LogicA0 AGND DB1 DB2 DB3 (MSB) DGND DB0 (LSB) VREF R FB VDD IOUT1 IOUT2 CLR WR CS
Rev. 2.00
ORDERING INFORMATION
Range Part No. Ceramic Dip MP7542AD Ceramic Dip MP7542BD Ceramic Dip MP7542SD* Ceramic Dip MP7542TD* Plastic Dip MP7542JN Plastic Dip MP7542KN SOIC MP7542JS SOIC MP7542KS –40 to +85°C –40 to +85°C –55 to +125°C –55 to +125°C +1/2 +1/2 +1/2 +1/2 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C INL (LSB) DNL (LSB) Gain Error (LSB) *Contact factory for non-compliant military processing PIN CONFIGURATIONS AGND DB3 DB2 DB1 DB0 DGND 16 Pin CDIP, PDIP (0.300”) D16, N16 R FB VREF VDD 161 16 Pin SOIC (Jedec, 0.300”) S16 DGND R FB VREF VDD IOUT1 IOUT2 AGND DB3 DB2 DB1 DB0 I OUT1 IOUT2 See Packaging Section for Package Dimensions CLR WRCS CLR WRCS PIN OUT DEFINITIONS 1I OUT1 DAC current output. Normally terminated at op amp. 2I OUT2 DAC current output. Normally terminated at ground.
3 AGND Analog Ground
4 DB3 Data Input Bit 3 (MSB)
5 DB2 Data Input Bit 2
6 DB1 Data Input Bit 1
7 DB0 Data Input Bit 0 (LSB)
PIN NO. NAME DESCRIPTION 8C S Chip Select Input 9W R Write Input
10 A0 Address Bus Input
11 A1 Address Bus Input
12 DGND Digital Ground
13 CLR
14 V DD +5 V Supply Input
15 V REF Reference Input
16 R FB DAC Feedback Resistor
PIN NO. NAME DESCRIPTION
Rev. 2.00
ELECTRICAL CHARACTERISTICS
(VDD = + 5 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 Resolution (All Grades) N 12 12 Bits Integral Non-Linearity INL LSB Best Fit Straight Line Spec. (Relative Accuracy) (Max INL – Min INL) / 2 J, A, S + 1+ 1 Differential Non-Linearity DNL LSB Monotonicity J, A, S + 2+ 2 11 Bits Guaranteed K, B, T + 1+ 1 12 Bits Guaranteed Gain Error J, A, S, K, B, T GE + 12.3 + 14.5 LSB Using Internal R FB Gain Temperature Coefficient2 TC GE +2 ppm/ °C ΔGain/ΔTemperature Power Supply Rejection Ratio PSRR + 50 + 100 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Output Leakage Current I OUT +10 + 200 nA DYNAMIC PERFORMANCE R L=100Ω , CL=13pF Current Settling Time2 tS 2.0 2.0 µs Full Scale Change to 1/2 LSB AC Feedthrough at IOUT1 2 FT 2.5 2.5 mV p-p V REF = 10kHz, 20 Vp-p, sinewave REFERENCE INPUT Input Resistance R IN 5 10 20 5 20 k Ω DIGITAL INPUTS3 Logical “1” Voltage V IH 3.0 3.0 V Logical “0” Voltage V IL 0.8 0.8 V Input Leakage Current I LKG +1+ 1 µA Input Capacitance2 C IN 88 p F ANALOG OUTPUTS Output Capacitance2 C OUT1 260 260 pF DAC Inputs all 1’s C OUT1 100 100 pF DAC Inputs all 0’s C OUT2 50 50 pF DAC Inputs all 1’s C OUT2 210 210 pF DAC Inputs all 0’s POWER SUPPLY Supply Voltage5 VDD +4.5 +5.5 +4.5 +5.5 V Supply Current I DD 2.5 2.5 mA All digital inputs = 0 V or all = 5 V
Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) 25°C Tmin to Tmax NOTES: Specifications are subject to change without notice 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. 5 Specified values guarantee functionality. Refer to other parameters for accuracy. Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments SWITCHING CHARACTERISTICS 2, 4 WR Pulse Width t WR 120 220 ns Address to WR Hold Time t AWH 50 65 ns CS to WR Hold Time t CWH 50 100 ns CLR Pulse Width t CLR 200 300 ns Byte Loading, CS to WR Setup t CWS1 60 130 ns Byte Loading, Address to WR Setup t AWS1 80 180 ns Byte Loading, WR to Data Setup t DS 50 65 ns Byte Loading, WR to Data Hold t DH 50 65 ns DAC Loading, CS to WR Setup t CWS2 60 150 ns DAC Loading, Address to WR Setup t AWS2 120 240 ns ABSOLUTE MAXIMUM RATINGS (T A = +25°C unless otherwise noted)1, 2, 3 Digital Input Voltage to GND (2) GND –0.5 to VDD +0.5 V. (Functionality Guaranteed +0.5 V) Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. 3 GND refers to AGND and DGND.
Figure 1. Timing Diagram
- indicates LOW to HIGH transition
- Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to
latch data and using CS as a device enable. Table 1. Truth Table
the DAC output to go to –VREF .
- The MP7542 DAC register can be asynchronously
- Each MP7542 requires only 4 bits of memory.
- Any of the four basic loading operations (i.e. load low
ble address location for the required DAC operation. Figure 2. 8085/MP7542 Interface (Memory Mapped Output)
Rev. 2.00
16 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP) N16 D e B 1 A 1 α C E A L B Q 1 Seating Plane SYMBOL MIN MAX MIN MAX INCHES A –– 0.200 –– 5.08 B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.745 0.785 18.92 19.94 E 0.295 0.325 7.49 8.26 E 1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q 1 0.055 0.070 1.40 1.78 S 0.020 0.080 0.51 2.03 MILLIMETERS Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. S
Rev. 2.00 b 0.014 0.023 0.356 0.584 –– b 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– E 0.220 0.310 5.59 7.87 4 E 0.290 0.320 7.37 8.13 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– Q 0.015 0.060 0.381 1.52 3 α 0° 15° 0° 15° –– D b e
16 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP) D16 SYMBOL MIN MAX MIN MAX NOTES INCHES MILLIMETERS S 1 S NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 9See Note 1 E α c A L Q Seating Plane Base Plane
Rev. 2.00 SYMBOL MIN MAX MIN MAX A 0.097 0.104 2.46 2.64 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.482 C 0.0091 0.0125 0.231 0.318 D 0.402 0.412 10.21 10.46 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° INCHES MILLIMETERS
16 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC) S16 e 16 9 D E H B A L C A 1 Seating Plane α h x 45°
Rev. 2.00 Notes
Rev. 2.00 Notes
Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.