MP7528 EXAR | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Rev. 2.00
FEATURES
- On-Chip Latches for Both DACs
- +5 V to +15 V Operation
- DACs Matched to 1%
- Four Quadrant Multiplication
- 15 V CMOS Compatible
- See MP7529A or MP7529B for Improved Performance CMOS Dual Buffered Multiplying 8-Bit Digital-to-Analog Converter
APPLICATIONS
- Microprocessor Controlled Gain Circuits
- Microprocessor Controlled Attenuator Circuits
- Microprocessor Controlled Function Generation
- Precision AGC Circuits
- Bus Structured Instruments GENERAL DESCRIPTION The MP7528 is a dual 8-bit digital/analog converter designed using EXAR’s proven decoded DAC architecture. It features ex- cellent DAC-to-DAC matching and guaranteed monotonicity. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input DACA /DACB determines which DAC is to be loaded. The MP7528’s load cycle is similar to the write cycle of a random ac- cess memory and the device is bus compatible with most 8-bit microprocessors. The device operates from a +5V to +15V power supply with only 2 mA of current (maximum). Both DACs offer excellent four quadrant multiplication char- acteristics with a separate reference input and feedback resistor for each DAC. SIMPLIFIED BLOCK AND TIMING DIAGRAM DGND LATCH A LATCH B DAC A DAC B D E Q D E Q DB7-DB0 OUT DB7-DB0 AGND VDD VREFA R FBA IOUTA R FBB IOUTB VREFB DACA /DACB CS WR DACA /DACB CS WR
Rev. 2.00 Ceramic Dip MP7528AD Ceramic Dip MP7528BD Ceramic Dip MP7528CD Ceramic Dip MP7528SD* Ceramic Dip MP7528TD* –40 to +85°C –40 to +85°C –40 to +85°C –55 to +125°C –55 to +125°C +1/2 +1/4 +1/2
ORDERING INFORMATION
Range Part No. Plastic Dip MP7528JN Plastic Dip MP7528KN Plastic Dip MP7528LN PLCC MP7528JP PLCC MP7528KP PLCC MP7528LP SOIC MP7528JS SOIC MP7528KS SOIC MP7528LS +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C INL (LSB) Gain Error (LSB) DNL (LSB) *Contact factory for non-compliant military processing PIN CONFIGURATIONS AGND DGND (MSB) DB7 DB6 DB5 DB4 DB0 (LSB) DB1 DB2 DB3 20 Pin CDIP, PDIP (0.300”) D20, N20 R FBA VREFA R FBB VREFB VDD 20 Pin SOIC (Jedec, 0.300”) S20 201 1110 See Pin Out at Left IOUTB IOUTA See Packaging Section for Package Dimensions DACA /DACB CS WR
Rev. 2.00 PIN CONFIGURATIONS (CONT’D) 3 2 1 20 19 9 1 01 11 21 3
20 Pin PLCC
(MSB) DB7 DB6 VREFA DB5 DB4 DB3 DB2 DB1 DB0 VREFB VDD R FBB (LSB) IOUTBIOUTA DACA /DACB CS WR PIN OUT DEFINITIONS
1 AGND Analog Ground
3R FBA Feedback Resistor for DAC A 4V REFA Reference Input for DAC A
5 DGND Digital Ground
6 DAC A
/ DAC Select DAC B
7 DB7 (MSB) Data Input Bit 7
8 DB6 Data Input Bit 6
9 DB5 Data Input Bit 5
10 DB4 Data Input Bit 4
11 DB3 Data Input Bit 3
12 DB2 Data Input Bit 2
13 DB1 Data Input Bit 1
14 DB0 (LSB) Data Input Bit 0
16 WR Write
17 V DD Power Supply
18 V REFB Reference Input for DAC B
19 R FBB Feedback Resistor for DAC B
20 I OUTB Current Out DAC B
PIN NO. NAME DESCRIPTION
Rev. 2.00
ELECTRICAL CHARACTERISTICS
(VDD = + 5 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 Resolution (All Grades) N 8 8 Bits Integral Non-Linearity INL LSB End Point Linearity Spec. (Relative Accuracy) J, A, S + 1+ 1 L, C + 1/4 + 1/4 Monotonicity Guaranteed over temp Differential Non-Linearity DNL + 1+ 1 LSB All grades monotonic over full J, A, S temperature range. K, B, T L, C Gain Error GE LSB Using Internal R FB J, A, S + 4+ 6 Digital Inputs = V INH K, B, T + 2+ 4 L, C + 1+ 3 Gain Temperature Coefficient2 TC GE +70 ppm/ °C ΔGain/ΔTemperature Power Supply Rejection Ratio PSRR + 200 + 400 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Digital Inputs = VINH Output Leakage Current (Pin 2) IOUT1 +50nA + 400nA nA Digital Inputs = V INL Output Leakage Current (Pin 20) IOUT2 +50nA + 400nA nA Digital Inputs = V INH Input Resistance V REFA 8 15 8 15 k Ω TC = –300 ppm/°C max. VREFB 8 15 8 15 k Ω 11 kΩ typical Input Resistance Matching + 1+ 1% DYNAMIC PERFORMANCE 2 R L=100Ω , CL=13pF Harmonic Distortion THD –85 dB V IN = 6VRMS @ 1 KHz Digital Crosstalk Q 30 nVs Measured for code transition ZS to FSS Channel-to-Channel Isolation CCI –77 dB AC Feedthrough at I OUT1 FT –70 –65 dB V REF = 10kHz, 20 Vp-p, sinewave Glitch Energy Egl 160 nVs Z S to FS Input Change Propagation Delay t PD 220 270 ns From digital input to 90% of final analog output current
Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments DIGITAL INPUTS3 Logical “1” Voltage V IH 2.4 2.4 V Logical “0” Voltage V IL 0.8 0.8 V Input Leakage Current I LKG +1+ 10 µA Input Capacitance2 Data C IN 10 10 pF Control C IN 15 15 pF ANALOG OUTPUTS 2 Output Capacitance C OUTA 120 120 pF DAC Inputs all 1’s C OUTA 50 50 pF DAC Inputs all 0’s C OUTB 120 120 pF DAC Inputs all 1’s C OUTB 50 50 pF DAC Inputs all 0’s POWER SUPPLY 5 Functional Voltage Range2 VDD 4.5 15.75 4.5 15.75 V Supply Current I DD 2 2 mA All digital inputs = 0 V or all = 5 V 2 2 mA All digital inputs = V IL or all = VIH SWITCHING CHARACTERISTICS Chip Select to Write Set-Up Time tCS 200 230 ns Chip Select to Write Hold Time t CH 20 30 ns DAC Select to Write Set-Up Time t AS 200 230 ns DAC Select to Write Hold Time t AH 20 30 Data Valid to Write Set-Up Time t DS 110 130 ns Data Valid to Write Hold Time t DH 00 n s Write Pulse Width t WR 180 200 ns NOTES: Specifications are subject to change without notice 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. 5 Specified values guarantee functionality. Refer to other parameters for accuracy.
Rev. 2.00 (VDD = + 15 V, VREF = +10 V unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE 1 Resolution (All Grades) N 8 8 Bits Integral Non-Linearity INL LSB End Point Linearity Spec. (Relative Accuracy) J, A, S + 1+ 1 L, C + 1/4 + 1/4 Monotonicity Guaranteed over temp Differential Non-Linearity DNL LSB All grades monotonic over full J, A, S + 1+ 1 temperature range. K, B, T + 1+ 1 L, C + 1+ 1 Gain Error GE LSB Using Internal R FB J, A, S + 4+ 5 Digital Inputs = V INH K, B, T + 2+ 3 L, C + 1+ 1 Gain Temperature Coefficient2 TC GE +35 ppm/ °C ΔGain/ΔTemperature Power Supply Rejection Ratio PSRR + 100 + 200 ppm/% |ΔGain/ΔVDD | ΔVDD = + 5% Digital Inputs = VINH Output Leakage Current (Pin 2) IOUT1 +50nA + 200nA nA Digital Inputs = V INL Output Leakage Current (Pin 20) IOUT2 +50nA + 200nA nA Digital Inputs = V INH Input Resistance V REFA 8 15 8 15 k Ω TC = –300 ppm/°C max. VREFB 8 15 8 15 k Ω 11 kΩ typical Input Resistance Matching + 1+ 1% DYNAMIC PERFORMANCE 2 R L=100Ω , CL=13pF Harmonic Distortion THD –85 dB V IN = 6VRMS @ 1 KHz Digital Crosstalk Q 60 nVs Measured for code transition ZS to FS Channel-to-Channel Isolation CCI –77 dB AC Feedthrough at I OUT1 FT –70 –65 dB V REF = 10kHz, 20 Vp-p, sinewave Glitch Energy Egl 440 nVs ZS to F S Input Change Propagation Delay t PD 80 100 ns From 50% of digital input to 90% of final analog output current DIGITAL INPUTS3 Logical “1” Voltage V IH 13.5 13.5 V Logical “0” Voltage V IL 1.5 1.5 V Input Leakage Current I ILKG +1+ 10 µA Input Capacitance2 Data C IN 10 10 pF Control C IN 15 15 pF
Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) 25°C Tmin to Tmax NOTES: Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments ANALOG OUTPUTS 2 Output Capacitance C OUTA 120 120 pF DAC Inputs all 1’s C OUTA 50 50 pF DAC Inputs all 0’s C OUTB 120 120 pF DAC Inputs all 1’s C OUTB 50 50 pF DAC Inputs all 0’s POWER SUPPLY 5 Functional Voltage Range2 VDD 4.5 15.75 4.5 15.75 V Supply Current I DD 2 2 mA All digital inputs = 0 V or all = 5 V 2 2 mA All digital inputs = V IL or all = VIH SWITCHING CHARACTERISTICS Chip Select to Write Set-Up Time t CS 60 80 ns Chip Select to Write Hold Time t CH 10 15 ns DAC Select to Write Set-Up Time t AS 60 80 ns DAC Select to Write Hold Time t AH 10 15 ns Data Valid to Write Set-Up Time t DS 30 40 ns Data Valid to Write Hold Time t DH 00 n s Write Pulse Width t WR 60 80 ns Specifications are subject to change without notice 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. 5 Specified values guarantee functionality. Refer to other parameters for accuracy. ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 (Functionality Guaranteed +0.5 V) Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. 3 GND refers to AGND and DGND.
accept data from the input port. sponding to the data in their respective latches. Table 1. Mode Selection Table Figure 1. Write Cycle Timing Diagram
- All input signal rise and fall times measured from 10% to 90% of V
- Timing measurement reference level is VIH + VIL / 2
Rev. 2.00 This page left blank
Rev. 2.00 b 0.014 0.023 0.356 0.584 –– b1 0.038 0.065 0.965 1.65 2 c 0.008 0.015 0.203 0.381 –– E 0.220 0.310 5.59 7.87 4 E 1 0.290 0.320 7.37 8.13 7 e 0.100 BSC 2.54 BSC 5 L 0.125 0.200 3.18 5.08 –– Q 0.015 0.070 0.381 1.78 3 α 0° 15° 0° 15° –– D be 1b
20 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP) D20 SYMBOL MIN MAX MIN MAX NOTES INCHES MILLIMETERS S 1 S NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) be- tween centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 11 0 11See Note 1 E α c L Q Seating Plane Base Plane A
Rev. 2.00
20 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP) N20 D eB 1 A 1 α C E A L B Q 1 Seating Plane SYMBOL MIN MAX MIN MAX INCHES A –– 0.200 –– 5.08 B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.945 1.060 24.0 26.92 E 0.295 0.325 7.49 8.26 E 1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q 1 0.055 0.070 1.40 1.78 S 0.040 0.080 1.02 2.03 MILLIMETERS S Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only.
Rev. 2.00 SYMBOL MIN MAX MIN MAX A 0.097 0.104 2.464 2.642 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° INCHES MILLIMETERS e 20 11
20 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC) S20 D E H B A L C A 1 Seating Plane α h x 45°
Rev. 2.00 Notes
Rev. 2.00 Notes
Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.