MP7226 EXAR | Alldatasheet

Document overview

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Technical content

Rev. 2.00

FEATURES

  • MPS Pioneered Segmented DAC Approach
  • Four 8-Bit DACs with Buffer Amplifiers
  • Bipolar Amplifier Inputs for Low Noise and Drift
  • Operates with Single or Dual Supplies
  • µP Compatible (95ns WR)
  • No External Adjustments Required
  • Power-on-Reset Function
  • Specified for 5 to 15 V Operation
  • ESD Protection: 2000 Volts Minimum
  • Latch-Up Proof
  • Octal Available: MP7228 BiCMOS Fixed, Quad, Voltage Output, Single or Dual Supply 8-Bit Digital-to-Analog Converter

APPLICATIONS

  • Function Generators
  • Automatic Test Equipment
  • Process Controls BENEFITS
  • Reduced Board Space; Lower System Cost
  • Reduced System Errors due to Excellent DAC-to-DAC Matching and Tracking
  • Easy to Design with Microprocessors
  • Stable, High Reliability through Advanced Processing
  • Lower 1/f Noise Increases Useful Dynamic Range GENERAL DESCRIPTION The MP7226 contains four 8-bit voltage-output Digital-to- Analog Converters, with BiCMOS output buffer amplifiers and interface logic on a monolithic chip. Separate on-chip latches are provided for each of the four D/A converters. The control logic is speed compatible with most 8-bit microprocessors. All digital inputs are TTL/CMOS(5V) compatible. The MP7226 is manufactured using advanced thin film resis- tors on a double metal BiCMOS process. The MP7226 incorpo- rates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. The MP7226 maintains 8-Bit accuracy over the full operat- ing temperature range without laser trim or external adjust- ments. SIMPLIFIED BLOCK DIAGRAM LATCH 1 DAC 1 + 1 DAC 2 + 2 DAC 3 + 3 DAC 4 + 4 VOUT1 VOUT2 VOUT3 VOUT4 VREF VDD LATCH 2 LATCH 3 LATCH 4 VSS AGND MSB LSB DATA (8 BIT) WR CONTROL LOGIC D A T A B U S DGND

Rev. 2.00

ORDERING INFORMATION

(LSB)Part No. DNL (LSB) Full Scale Error (LSB) Plastic Dip PLCC SOIC –40 to +85°C MP7226KN MP7226KP MP7226KS –40 to +85°C –40 to +85°C 1 1 Plastic Dip –40 to +85°C MP7226LN* 1/2 PLCC MP7226LP*–40 to +85°C SOIC MP7226LS*–40 to +85°C *Contact factory for availability. PIN CONFIGURATIONS 20 Pin PDIP (0.300”) N20 DB0 (LSB) DB1 DB2 DB3 20 Pin SOIC (Jedec, 0.300”) S20 VOUT2 VOUT1 VSS VREF AGND DGND DB7 (MSB) DB6 DB5 DB4 VDD VOUT3 VOUT4 201 1110 See Pin Out at Left 3 2 1 20 19 9 1 01 11 21 3 See Pin Out at Far Left

20 Pin PLCC

See Packaging Section for Package Dimensions PIN OUT DEFINITIONS 1V OUT2 DAC 2 Voltage Output 2V OUT1 DAC 1 Voltage Output 3V SS Negative Power Supply (0 V to –5 V) 4V REF Reference Input Voltage

5 AGND Analog Ground

6 DGND Digital Ground

7 DB7 Data Input Bit 7 (MSB)

8 DB6 Data Input Bit 6

9 DB5 Data Input Bit 5

10 DB4 Data Input Bit 4

PIN NO. NAME DESCRIPTION

11 DB3 Data Input Bit 3

12 DB2 Data Input Bit 2

13 DB1 Data Input Bit 1

14 DB0 Data Input Bit 0 (LSB)

Write (Active Low)

16 A1 DAC Address Bit 1

17 A0 DAC Address Bit 0

DD Positive Power Supply (+5 to +15 V)

19 V OUT4 DAC 4 Voltage Output

20 V OUT3 DAC 3 Voltage Output

PIN NO. NAME DESCRIPTION

Rev. 2.00

ELECTRICAL CHARACTERISTICS

Single or Dual Supply Operation (VDD = +10.8 V to 16.5 V, VSS = 0 V or –5 V 10%, AGND = 0 V, DGND = 0 V, VREF = +2 V to +10 V, RL = 2kΩ , CL = 100pF unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) N 8 8 Bits Integral Non-Linearity INL LSB (Relative Accuracy) K 1 1 End Point Linearity Spec L 1/2 1/2 Differential Non-Linearity DNL LSB All grades monotonic over full K 1/2 3/4 temperature range. L 1/2 3/4 Total Unadjusted Error

2 LSB V DD = 15 V 10%, VREF = +10 V

Full Scale Error3 LSB V REF = +10 V typ. Tempco is K 1 1 5 ppm/ °C L 1/2 1/2 Zero Code Error mV TA = 25 °C typ. Tempco is K 20 30 30 µV/°C L 15 20 Output Load Resistance 2 2 k Ω VOUT = +10 V DYNAMIC PERFORMANCE 4 Voltage Output Slew Rate 2 4 2 V/ µs Voltage Output Settling Time 4 5 µsV REF = +10 V; Settling Time to 1/2 LSB Digital Feedthrough 25 nVs Code transition all 0s to all 1s VREF = 0 V, WR = VDD Digital Crosstalk5 25 nVs Code transition all 0s to all 1s VREF = +10 V, WR = 0 V REFERENCE INPUT Reference Input Range1 1 10 1 10 V Limitation: V REF – VSS < 11 V Reference Input Resistance R IN 22 k Ω Min RIN at Code 14910 Reference Input Capacitance4 500 pF Occurs when all DACs are loaded with all 1s AC Feedthrough –70 dB V REF = 10 kHz, 5 V p-p sinewave DIGITAL INPUTS Input High Voltage V INH 2.4 2.4 V Input Low Voltage V INL 0.8 0.8 V Input Leakage Current I LKG 1 1 µAV IN = 0 V or VDD Input Capacitance4 88 p F Input Coding Binary

Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments POWER SUPPLY VDD Range 10.8 16.5 10.8 16.5 V For specified performance VSS Range (Dual Supplies)8 0 –5.5 0 –5.5 V For specified performance IDD 12 14 mA Outputs unloaded; VIN=VINL or VINH ISS (Dual Supplies) 10 12 Outputs unloaded; VIN=VINL or VINH SWITCHING CHARACTERISTICS 4, 6, 7 Address to WR Setup Time, t1 t AS 00 n s Address to WR Hold Time, t2 t AH 00 n s Data Valid to WR Setup Time, t3 t DS 70 95 ns Data Valid to WR Hold Time, t4 t DH 10 10 WR Pulse Width, t5 t WR 95 120 ns NOTES: Specifications are subject to change without notice 1 VOUT must be less than VDD by 3.5 V to ensure correct operation. 2 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 3 Calculated after zero code error has been adjusted out. 4 Sample tested at 25°C to ensure compliance. 5 The glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 All input rise and fall times are measured from 10% to 90% of +5 V, tR = tF = 5 ns. 7 Timing measurement reference level is (VINH + VINL)/2.

Rev. 2.00 Single & Dual 5 V Supply Operation (VDD = +5 V 5%, VSS = 0 V to –5 V 10%, VREF = +1.25 V, AGND = 0 V, DGND = 0 V, RL = 2kΩ , CL = 100pF unless otherwise noted) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) N 8 8 Bits Integral Non-Linearity INL LSB (Relative Accuracy) K 2 2 End Point Linearity Spec L1 1 Differential Non-Linearity DNL LSB All grades monotonic over full K 1 1 temperature range. L 1 1 Total Unadjusted Error 2 4 LSB V DD = 5 V 5%, VREF = 1.25 V Full Scale Error3 LSB V REF = +1.25 V K 4 4 L 2 2 Zero Code Error 20 mV Output Load Resistance 2 k Ω VOUT = +10 V DYNAMIC PERFORMANCE 4 Voltage Output Slew Rate 2 4 V/ µs Voltage Output Settling Time 4 µsV REF = +1.25 V; Settling Time to 1/2 LSB Digital Feedthrough 25 nVs Code transition all 0s to all 1s VREF = 0 V, WR = VDD Digital Crosstalk5 25 nVs Code transition all 0s to all 1s VREF = +1.25 V, WR = 0 V REFERENCE INPUT Reference Input Range 1 1.6 1 1.6 V V OUT must be < VDD by 3.2V Reference Input Resistance R IN 22 k Ω Reference Input Capacitance4 500 pF Occurs when all DACs are loaded with all 1s AC Feedthrough –70 dB V REF = 10 kHz, 1/2 V p-p sinewave DIGITAL INPUTS Input High Voltage V INH 2.4 2.4 V Input Low Voltage V INL 0.8 0.8 V Input Leakage Current I LKG 1 1 µAV IN = 0 V or VDD Input Capacitance4 88 p F Input Coding Binary

Rev. 2.00 ELECTRICAL CHARACTERISTICS (CONT’D) 25°C Tmin to Tmax Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments POWER SUPPLY VDD Range 4.75 5.25 4.75 5.25 V For specified performance IDD 8 8 mA Outputs unloaded; VIN=VINL or VINH ISS (Dual Supplies) 6 6 Outputs unloaded; VIN=VINL or VINH SWITCHING CHARACTERISTICS 4, 6, 7 Address to WR Setup Time, t1 t AS 00 n s Address to WR Hold Time, t2 t AH 00 n s Data Valid to WR Setup Time, t3 t DS 70 95 ns Data Valid to WR Hold Time, t4 t DH 0 WR Pulse Width, t5 t WR 95 120 ns NOTES: Specifications are subject to change without notice 1 VOUT must be less than VDD by 3.5 V to ensure correct operation. 2 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 3 Calculated after zero code error has been adjusted out. 4 Sample tested at 25°C to ensure compliance. 5 The glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 All input rise and fall times are measured from 10% to 90% of +5 V, tR = tF = 5 ns. 7 Timing measurement reference level is (VINH + VINL)/2. ABSOLUTE MAXIMUM RATINGS (T A = +25°C unless otherwise noted)1, 2 (Functionality Guaranteed +0.5 V) Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs.

the addressed DAC will receive input data. Table 2. shows the code relationship for the part in unipolar Table 2. Unipolar Code Table Table 3. Bipolar Code Table

Rev. 2.00 PERFORMANCE CHARACTERISTICS Graph 1. Power Supply Current vs. Temperature Graph 2. Relative Accuracy vs. Digital Code

Rev. 2.00

20 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP) N20 D eB 1 A 1 α C E A L B Q 1 Seating Plane SYMBOL MIN MAX MIN MAX INCHES A –– 0.200 –– 5.08 B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.945 1.060 24.0 26.92 E 0.295 0.325 7.49 8.26 E 1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q 1 0.055 0.070 1.40 1.78 S 0.040 0.080 1.02 2.03 MILLIMETERS S Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only.

Rev. 2.00 SYMBOL MIN MAX MIN MAX A 0.097 0.104 2.464 2.642 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° INCHES MILLIMETERS e 20 11

20 LEAD SMALL OUTLINE

(300 MIL JEDEC SOIC) S20 D E H B A L C A 1 Seating Plane α h x 45°

Rev. 2.00 A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.533 C 0.008 0.012 0.203 0.305 D 0.385 0.395 9.78 10.03 D 1 (1) 0.350 0.354 8.89 8.99 D 2 0.290 0.330 7.37 8.38 D 3 0.200 Ref 5.08 Ref. e1 0.050 BSC 1.27 BSC

20 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC) P20 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS D D 1 D 2 B A A 1 C D D 1 Seating Plane D 3 Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. A 2

Rev. 2.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.