MP6005

MP6005 MPS | Alldatasheet

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Technical content

High-Efficiency Flyback/Forward Controller with Primary and Secondary-Side Regulation MP6005 Rev. 1.0 www.MonolithicPower.com 1 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

DESCRIPTION

The MP6005 is a high-power, high -efficiency flyback and forward controller. It is specifically designed as a low-cost, small, isolated solution with primary -side regulation (PSR) for flyback application, and high -efficiency secondary-side regulation (SSR) for active-clamped forward application. The MP 6005 can also be used in SSR for flyback topology. In PSR mode, t he MP6005 senses the third winding waveform on the primary side to regulate the output and save the optocoupler and TL431 feedback circuit from SSR application. Continuous conduction mode (CCM) provides high efficiency under heavy load conditions, while the output diode compensation function supports good output regulation even during primary-side regulation. In SSR mode, the SYNC driver provides high efficiency for active-clamped forward topology. The MP6005 includes a 2A gate driver, frequency dithering, overload protection (OLP), and over-voltage protection (OVP). The MP6005 is available in an MSOP10 package.

FEATURES

 Primary-Side Regulated Flyback without Optocoupler Feedback  Synchronous Gate Driver (SYNC) Provides High Efficiency for Active-Clamped Forward Topology  Wide 8V to 80V Input Voltage Range  Internal Circuit Supply Compatible with 16V External Power  2A GATE and 0.8A SYNC Drivers  160mV Switching Current-Sense (CS) Limit  Output Diode Compensation in Primary- Side Regulation (PSR) Mode  250kHz Fixed Switching Frequency  Hiccup Protection, Overload Protection (OLP), Short-Circuit Protection (SCP), Over- Voltage Protection (OVP), and Thermal Shutdown  Frequency Dithering to Reduce Electromagnetic Interference (EMI)  Available in an MSOP10 Package

APPLICATIONS

 Security Cameras  Video Telephones  Wireless Access Points (WAPs)  Point-of-Sale (POS) Systems  Power over Ethernet (PoE) Systems  Industrial Isolated Power Supplies All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION VIN GATE GND VOUT VIN EN VCC SENSE FB COMP C5R5 MODE SYNC MP6005 Efficiency PSR flyback, VOUT = 12V

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 2 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking MSL Rating MP6005GK MSOP10 See Below 1 * For Tape & Reel, add suffix –Z (e.g. MP6005GK–Z). TOP MARKING Y: Year code W: Week code LLL: Lot number M6005: First five digits of the part number PACKAGE REFERENCE TOP VIEW 5 6 4 7 VCC SENSE EN VIN MODE GATE SYNC GND FB COMP MSOP10

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 3 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Pin Function

1 VCC

Internal circuit supply pin. The VCC pin is powered by the internal LDO regulator (LDO) from the VIN pin. To bypass the internal regulator, connect a capacitor from the VCC pin to GND. The VCC capacitor has a 1µF minimum for flyback application, and a 4.7µF minimum for forward application. The VCC pin can also be powered by an external power source to reduce internal low-dropout loss.

2 SENSE

Current-sense PSR, output voltage (VOUT) compensation, and frequency dither ing setting pin. For function details, see the Output Voltage Compensation section and the Frequency Dithering section on page 17. 3 EN On/off control pin. The EN pin is internally connected to GND through a 2.5MΩ resistor. 4 VIN Input power supply pin. Connect a bypass capacitor from the VIN pin to GND. 5 MODE PSR/SSR mode and dead time setting pin. For function details, see the Work Mode Detection section on page 15. 6 COMP Loop compensation pin. In PSR mode, the COMP pin is the error amplifier (EA) output. In SSR mode, the COMP pin is pulled up to 5V through an internal 10kΩ resistor. 7 FB Output voltage feedback and OVP monitor ing pin. To regulate the output voltage in PSR mode, connect the FB pin to a resistor divider from the SENSE pin. The internal EA is disabled in SSR mode. The FB pin detects the OVP signal in both PSR and SSR mode. If OVP is not used in SSR mode, connect the FB pin to GND. 8 GND Ground. Power return for the controller. 9 SYNC Synchronous MOSFET gate driver pin. 10 GATE Main MOSFET gate driver pin. ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25°C) (4) (6) Recommended Operating Conditions (5) Operating junction temp (TJ) ... -40 °C to +125°C Thermal Resistance θJA θJC MSOP10 Notes: 1) Exceeding these ratings may damage the device. 2) When VEN is pulled high, a current limited by the external pull- up resistor flows into the EN pin. See the Enable (EN) Control section on page 15 for the EN pin’s voltage rating description. 3) FB is clamped by the internal circuit . The sink and source currents should be limited. See the Setting the Output Voltage section on page 20 for details. 4) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calc ulated by P D (MAX) = (T J (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can cause excessive die temperature, and the regulator may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 5) The device is not guaranteed to function outside of its operating conditions. 6) Measured on EV6005-K-00A, 2-layer 90mmx35mm PCB. 7) The value of θJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51 -7 and simulated on a specified JEDEC board. They do not represent the performance obtained in actual application.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 4 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 48V, VEN = 5V, TJ = -40°C to +125°C (8), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Power Supply and Under-Voltage Lockout (UVLO) UVLO rising threshold VIN-R VIN rising, start charge VCC 4.5 5.5 6.5 V VIN UVLO falling threshold VIN-F VIN falling 3.8 4.8 5.8 V VCC regulation voltage VCC Load = 0mA to 20mA 8.5 V VCC dropout voltage VCC-DROP VIN = 8V, IVCC = 10mA 1.5 V VCC UVLO rising threshold VCC-R VIN > VIN-R, VCC rising 5.4 5.7 6.0 V VCC UVLO falling threshold VCC-F VIN > VIN-R, VCC falling 5.0 5.3 5.6 V Quiescent supply current IQ MODE pin float, VFB = -0.1V, VSENSE = 100mV, VCOMP = 0V, IQ = IIN - ICOMP, GATE and SYNC floating 800 μA VMODE = 0V, VCOMP = 0V, IQ = IIN - ICOMP, GATE and SYNC floating 450 μA Shutdown supply current ISD VEN = 0V 1 μA Enable (EN) Control EN turn-on threshold VEN-R Start switching 1.93 2 2.07 V EN hysteresis VEN-HYS Stop switching 0.2 V EN high micro-power threshold VEN-H Start internal logic 1.0 V EN low micro-power threshold VEN-L Stop internal logic 0.4 V EN input current IEN VEN = 5V 2 μA EN turn-on delay EN on to GATE output 500 μs Voltage Feedback FB reference voltage VREF TJ = 25°C 1.98 2 2.02 V TJ = -40°C to +125°C 1.97 2 2.03 V FB leakage current IFB VFB = 2V 10 50 nA FB over-voltage protection (OVP) threshold VFBOVP 120% 125% 130% VREF OVP hiccup off time 340 ms Minimum diode conduction time for FB sample tSAMPLE 0.5 0.6 (9) μs Regulation compensation current into FB VSENSE = 50mV, RSENSE-GND = 3.3kΩ (10) 2.7 μA VSENSE = 50mV, RSENSE-GND = 6.8kΩ (10) 5.4 μA VSENSE = 50mV, RSENSE-GND = 12.7kΩ (10) 10.8 μA Error Amplifier (EA) EA transconductance GEA MODE floating, VFB is ±50mV from VREF, VCOMP = 1.5V 0.59 mA/V

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 5 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, TJ = -40°C to +125°C (8), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units EA max source current IEA MODE floating, VCOMP = 1.5V, VFB = 1.9V -110 μA EA max sink current IEA MODE floating, VCOMP = 1.5V, VFB = 2.1V 110 μA COMP high voltage VCOMP MODE floating, VFB = 1.9V 4 V VMODE = 0V, float COMP 5 COMP internal pull-up resistor SSR mode 10 kΩ Soft Start (SS) Internal soft-start time tSS When MODE is floating, test FB from 0V to 2V; when VMODE = 0V, test COMP from 1.5V to 3.5V 4.7 ms Current Sense (CS) Max CS ILIMIT-MAX 140 160 180 mV Low current threshold ILIMIT-MIN In PSR mode 33 36 39 mV Short-circuit protection (SCP) 240 300 360 mV Current leading-edge blanking time tLED 250 ns CS amplifier gain GCS 11 V SENSE input bias current VSENSE = 160mV 10 50 nA Pulse-Width Modulation (PWM) Switching frequency fSW 225 250 275 kHz Minimum foldback frequency in pulse-frequency modulation (PFM) mode In PSR mode, VCOMP = 0V 30 kHz Mode, Dead Time, Dither, VOUT Compensation Setting (MODE and SENSE Pin) MODE detection current IMODE 35 40 45 μA SENSE detection current ISENSE 90 100 110 μA MODE/SENSE detection period tMODE/ tSENSE 200 μs MODE/SENSE detection threshold (11) VMODE/ VSENSE Voltage level 1 range 0.15 V Voltage level 2 range 0.25 0.4 V Voltage level 3 range 0.55 0.85 V Voltage level 4 range 1.1 1.5 V Voltage level 5 range 2.2 V GATE Signal GATE sourcing impedance IGATE IGATE = -20mA 2 Ω GATE sinking impedance IGATE IGATE = 20mA 1.7 Ω GATE source current (12) VCC = 8.5V, GATE = 10nF, test gate rising speed 2 A ELECTRICAL CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, TJ = -40°C to +125°C (8), typical value is tested at TJ = 25°C, unless otherwise noted.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 6 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Parameter Symbol Condition Min Typ Max Units GATE sink current (12) VCC = 8.5V, GATE = 10nF, test gate falling speed 1.7 A GATE high voltage output VGATE VCC - 0.05 V GATE low voltage output VGATE 0.05 V GATE minimum on time tON-MIN 250 ns GATE max duty cycle DMAX 70 % SYNC Signal SYNC sourcing impedance ISYNC IGATE = -20mA 5 Ω SYNC sinking impedance ISYNC IGATE = 20mA 2 Ω SYNC source current (12) VCC = 8.5V, SYNC = 10nF, test SYNC rising speed 0.8 A SYNC sink current (12) VCC = 8.5V, SYNC = 10nF, test SYNC falling speed 1.2 A SYNC high voltage output VSYNC VCC - 0.05 V SYNC low voltage output VSYNC 0.05 V Protections Overload protection (OLP) hiccup on time (12) 4.8 ms OLP hiccup off time (12) 340 ms Thermal shutdown temperature (12) TSD 150 °C Thermal shutdown hysteresis (12) THYS 20 °C Notes: 8) Guaranteed by over-temperature correlation, not tested in production. 9) A minimum output diode conduction time greater than 0.7µs is recommended. 10) RSENSE-GND is the resistance from the SENSE pin to GND, which includes the CS resistor from the MOSFET source to GND and the resistor from the MOSFET source to the SENSE pin. 11) See Table 1 on page 15 and Table 2 on page 17 for voltage-level program options. 12) Guaranteed by sample characterization, not tested in production.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 7 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VIN = 48V, VEN = 5V, TA = 25°C, unless otherwise noted. VCC Load Regulation Quiescent Current vs. VIN 0 5 10 15 20 VCC VOLTAGE (V) VCC LOAD CURRENT (mA) VIN=8V VIN=48V 200 400 600 800 1000 0 20 40 60 80 IQ (uA) INPUT VOLTAGE (V) PSR SSR Shutdown Current vs. VIN VIN UVLO vs. Junction Temp 0 20 40 60 80 ISHUTDOWN (nA) INPUT VOLTAGE (V) 3.5 4.5 5.5 -50 0 50 100 150 VIN UVLO (V) JUNCTION TEMPERATURE (℃) Rising Falling VCC UVLO vs. Junction Temp EN UVLO vs. Junction Temp 4.4 4.8 5.2 5.6 -50 0 50 100 150 VCC UVLO (V) JUNCTION TEMPERATURE (℃) Rising Falling 1.5 1.6 1.7 1.8 1.9 2.1 -50 0 50 100 150 EN UVLO (V) JUNCTION TEMPERATURE (℃) Rising Falling

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 8 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, TA = 25°C, unless otherwise noted. VREF vs. Junction Temp Switching Frequency vs. Junction Temp 1.8 1.85 1.9 1.95 2.05 2.1 -50 0 50 100 150 VREF (V) JUNCTION TEMPERATURE (℃) 200 210 220 230 240 250 260 270 280 -50 0 50 100 150 Fsw (kHz) JUNCTION TEMPERATURE (℃) Minimum Foldback Frequency vs. Junction Temp PSR mode Current Limit Sense Voltage vs. Junction Temp -50 0 50 100 150 MINIMUM FOLD-BACK Fsw (kHz) JUNCTION TEMPERATURE (℃) 120 130 140 150 160 170 180 -50 0 50 100 150 VLIMIT (mV) JUNCTION TEMPERATURE (℃) Low Threshold Current Limit Sense Voltage vs. Junction Temp PSR mode OVP Threshold vs. Junction Temp -50 0 50 100 150 LOW THRESHOLD VLIMIT (mV) JUNCTION TEMPERATURE (℃) 2.3 2.35 2.4 2.45 2.5 2.55 2.6 -50 0 50 100 150 VOVP (V) JUNCTION TEMPERATURE (℃)

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 9 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, VOUT = 12V, IOUT = 2.5A, TA = 25°C, unless otherwise noted. Efficiency PSR flyback, VOUT = 12V Efficiency SSR forward, VOUT = 5V 0 0.5 1 1.5 2 2.5 3 EFFICIENCY (% ) LOAD CURRENT (A) Vin=36V Vin=48V Vin=57V 0 1 2 3 4 5 6 EFFICIENCY (% ) LOAD CURRENT (A) Vin=36V Vin=48V Vin=57V Load Regulation PSR flyback, VOUT = 12V, RFBH = 100kΩ, RSENSE-GND = 6.8kΩ Load Regulation PSR flyback, VIN = 48V, VOUT = 12V, RFBH = 100kΩ 0 1 2 3 LOAD REGULATION (% ) LOAD CURRENT (A) Vin=36V Vin=48V Vin=57V 0 0.5 1 1.5 2 2.5 LOAD REGULATION (% ) LOAD CURRENT (A) RSENSE-GND=0 RSENSE-GND=3.3K RSENSE-GND=6.8K RSENSE-GND=12.7K Load Regulation SSR forward, VOUT = 5V Line Regulation PSR flyback, VOUT = 12V, RFBH = 100kΩ, RSENSE-GND = 6.8kΩ -0.3 -0.2 -0.1 0.1 0.2 0.3 0 2 4 6 LOAD REGULATION (% ) LOAD CURRENT (A) Vin=36V Vin=48V Vin=57V 30 40 50 60 LINE REGULATION (% ) INPUT VOLTAGE (V) Iout=1A Iout=2.1A Iout=2.5A

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 10 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, VOUT = 12V, IOUT = 2.5A, TA = 25°C, unless otherwise noted. Line Regulation SSR forward, VOUT = 5V -0.3 -0.2 -0.1 0.1 0.2 0.3 30 40 50 60 LINE REGULATION (% ) INPUT VOLTAGE (V) Iout=0A Iout=2.5A Iout=5A

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 11 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, VOUT = 12V, IOUT = 2.5A, TA = 25°C, unless otherwise noted. Steady State IOUT = 30mA Steady State IOUT = 2.5A CH1: VOUT/AC 50mV/div. CH2: VIN 20V/div. CH3: SW 50V/div. CH4: IPRI 1A/div. CH1: VOUT/AC 50mV/div.C H2: VIN 20V/div. CH3: SW 50V/div. CH4: IPRI 2A/div. 20µs/div. 4µs/div. Start-Up through VIN IOUT = 30mA Start-Up through VIN IOUT = 2.5A CH1: VOUT 5V/div. CH2: VIN 20V/div. CH3: SW 50V/div. CH4: IPRI 1A/div. CH1: VOUT 5V/div. CH2: VIN 20V/div. CH3: SW 50V/div. CH4: IPRI 5A/div. 4ms/div. 4ms/div. Shutdown through VIN IOUT = 30mA Shutdown through VIN IOUT = 2.5A CH1: VOUT 5V/div. CH2: VIN 20V/div. CH3: SW 50V/div. CH4: IPRI 1A/div. CH1: VOUT 5V/div. CH2: VIN 20V/div. CH3: SW 50V/div. CH4: IPRI 5A/div. 200ms/div. 100ms/div.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 12 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, VOUT = 12V, IOUT = 2.5A, TA = 25°C, unless otherwise noted. Start-Up through EN IOUT = 30mA Start-Up through EN IOUT = 2.5A CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: SW 50V/div. CH4: IPRI 2A/div. CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: SW 50V/div. CH4: IPRI 5A/div. 4ms/div. 4ms/div. Shutdown through EN IOUT = 30mA Shutdown through EN IOUT = 2.5A CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: SW 50V/div. CH4: IPRI 2A/div. CH1: VOUT 5V/div. CH2: VEN 5V/div. CH3: SW 50V/div. CH4: IPRI 5A/div. 100ms/div. 1ms/div. SCP Entry IOUT = 30mA to short SCP Entry IOUT = 2.5A to short CH1: VOUT 5V/div. CH2: VIN 50V/div. CH3: SW 50V/div. CH4: IPRI 2A/div. CH1: VOUT 5V/div. CH2: VIN 50V/div. CH3: SW 50V/div. CH4: IPRI 5A/div. 100ms/div. 100ms/div.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 13 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VEN = 5V, VOUT = 12V, IOUT = 2.5A, TA = 25°C, unless otherwise noted. SCP Recovery IOUT = short to 30mA SCP Recovery IOUT = short to 2.5A CH1: VOUT 5V/div. CH2: VIN 50V/div. CH3: SW 50V/div. CH4: IPRI 5A/div. CH1: VOUT 5V/div. CH2: VIN 50V/div. CH3: SW 50V/div. CH4: IPRI 5A/div. 100ms/div. 100ms/div. OVP Entry IOUT = 30mA to 2mA OVP Recovery IOUT = 2mA to 30mA CH1: VOUT 5V/div. CH2: VIN 50V/div. CH3: SW 50V/div. CH4: IPRI 1A/div. CH1: VOUT 5V/div. CH2: VIN 50V/div. CH3: SW 50V/div. CH4: IPRI 1A/div. 100ms/div. 100ms/div. Load Transient IOUT = 30mA to 1.25A, IRAMP = 50mA/µs, RFBH = 100kΩ, RSENSE-GND = 6.8kΩ Load Transient IOUT = 1.25A to 2.5A, IRAMP = 50mA/µs, RFBH = 100kΩ, RSENSE-GND = 6.8kΩ CH1: VOUT/AC 500mV/div. CH4: IOUT 1A/div. CH1: VOUT/AC 500mV/div. CH4: IOUT 1A/div. 10ms/div. 1ms/div.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 14 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM VIN UVLO Regulator Oscillator and Slope Compensation EN VIN VCC PWM Logic Driver PWM Comparator GATE GND SENSE COMP Enable (EN) Control OCP Cycle by Cycle OCP 0.16V VCC UVLO SCP 0.3V OLP, SCP, OVP Lead to Hiccup Protection FB Protection Hiccup Mode 50µs Timer -2.5V OVP 36mV PSR Low Threshold PFM 4.8ms OLP FB Sample and Hold +SS OLP PSR Mode VOUT Compensation Current Dither and Compensation Driver SYNC MODE MODE Dead Time MODE MODE 10k SS in SSR Dither GND VCC Current-Sense (CS) Amplifier Figure 1: Functional Block Diagram

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 15 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. OPERATION Start-Up and Power Supply The MP6005 features an 80V internal start-up circuit. When the input vol tage ( VIN) exceeds 5.5V, the VCC pin’s capacitor is charged by the internal LDO regulator (LDO) . Typically, if V IN exceeds 10V, the VCC’s pin voltage ( VCC) is regulated at 8.5V and VCC under-voltage lockout (UVLO) is 5.7V. Aside from VCC UVLO, the MP6005 also has EN UVLO (typically 2V ). When VCC exceeds the 5.7V UVLO threshold and the EN pin is pulled high, the part begins operating. After the MP6005 turns on, the VCC pin can be powered by the auxiliary winding transformer to reduce IC power loss. The auxiliary power must be greater than V CC regulation (8.5V) to override the internal LDO. The internal reverse- blocking circuit allows VCC to exceed VIN if VCC has bias power . VCC should be below 16V due to the pin’s voltage rating. If VIN is below 8.5V and V CC is not regulated at 8.5V, the internal high -voltage VCC LDO has a voltage drop of about 1.5V. This allows the MP6005 to work when VIN is as low as 8V. Enable (EN) Control The EN pin is the on/off control for the MP6005. When the EN pin’s voltage ( VEN) exceeds 1V, the MP6005’s micro-power mode allows the device to turn on some of the internal circuits . If VEN exceeds the turn -on threshol d (2V), all functions are turned on and the GATE/SYNC driver signal starts up. The GATE/SYNC signal can be disabled if V EN drops to about 1.8V. Micro-power mode is only disabled after VEN drops below 0.4V. After shutdown, the MP6005 sinks a current below 1µA from the input power supply. EN can program the VIN pin’s start-up voltage through a resistor divider. The maximum recommended voltage for EN is 6.5V . If EN’s divider voltage exceeds 6.5V , it is recommended to use a divider resistor to limit the current going into EN . One inter nal Zener diode on EN clamps VEN when the divider voltage exceeds 6.5V. Ensure the clamped Zener diode current into EN is below 0.4mA with an external pull-up resistor. Work Mode Detection After turning on, the MP6005 produces a 40µA output current to the MODE pin to detect the resistor setting. If the MODE pin ’s voltage (VMODE) exceeds 2.2V, the MP6005 works in primary-side regulat ion (PSR) mode, and the internal error amplifier ( EA) turns on . If MODE is connected to GND through a resistor. the MP6005 works in secondary-side regulation (SSR) mode and the internal EA turns off while COMP is pulled up to the internal 5V power source through a 10kΩ resistor. Table 1 shows MODE program options. Table 1: MODE Program Options MODE to GND Resistance (kΩ) Work Mode Dead Time (ns) Min Typ (1%) Max 0 0 3.3 SSR 100 7.32 7.5 8.2 SSR 150 16 16.9 18.7 SSR 200 32.4 32.4 33 SSR 300

64.9 Float Float PSR 150

In PSR mode, the output voltage (V OUT) feedback signal is detected by auxiliary winding from the FB pin. Under light-load conditions, the MP6005 reduces the frequen cy accordingly. Under no -load conditions, the frequency remains above 30kHz. In SSR mode, the VOUT feedback signal is detected by the COMP pin , and the MP6005 maintains a fixed frequency. The peak current is regulated by the COMP pin’s voltage (VCOMP) until the MP6005’s power - save mode (PSM) is triggered. Once the MP6005 turns on, there is a 500 µs period b efore the device starts switching. The MODE pin, dead time, dither, and V OUT compensation are detected during this period. The MODE p in determines the PSR and SSR modes. It also programs the dead time between the GATE and SYNC pins . Table 1 shows the programming options. The MODE detection current lasts about 200µs. Typically, a resistor from MODE to GND is sufficient. A capacitor from MODE to GND may be required for filtering in a noisy environment. This capacitor must be below 100pF to allow

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 18 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. If V SENSE exceeds the current-limit threshold (typically 160mV), the MP6005 turns off the GATE output. Then the internal oscillator begins the next cycle and sense s the current again. The MP6005 limits the MOSFET current cycle by cycle. Error Amplifier (EA) In PSR mode, the MP6005 senses the feedback voltage (VFB) during the flyback period with the feedback pulse signal. The feedback signal is then held and fed to the error amplifier (EA). The EA regulates VCOMP based on the feedback signal, and VCOMP controls the transformer peak current to regulate VOUT. In SSR mode, the internal EA is disabled and the COMP pin is pulled up by an internal resistor. The external opto coupler can b e connected to COMP for VOUT signal feedback. Light-Load Control Under light-load conditions in PSR mode, VCOMP decreases to regulate the low transformer peak current. If the peak current signal is below 36mV, the MP6005 stops decreasing the transformer current, and instead decreases the frequency. As a result, the transferred energy decreases, and VOUT is regulated. In light -load PSR mode, the MP6005 sets the minimum frequency above 30kHz. This helps the device detect the output voltage a nd avoid audible noise. The minimum frequency requires some load to maintain V OUT, so that V OUT does not rise and trigger over -voltage protection (OVP). Under light-load condition s in SSR mode, the MP6005 maintains a fixed frequency and VCOMP continues to drop toward the PSM threshold. Over-Voltage Protection (OVP) The MP6005 includes over -voltage protection (OVP). If VFB exceeds 125% of VREF, the MP6005 turns off the GATE signal and enters h iccup mode . Once the fault has been removed, t he MP6005 turns on again after a 340ms delay, and then resumes normal operation. Connect the FB pin to GND if the OVP function is not used .OVP sampling has a blanking time to avoid mistriggering due to the oscillation of the leakage inductance and parasitic capacitance. Overload Protection (OLP) The MP6005 limits the peak current cycle by cycle under OCP condition s. If the load continues to increase after triggering OCP, VOUT decreases and the peak current triggers OCP for each cycle. The MP6005 sets overload detection by monitoring VSENSE. Once the internal soft start is complete, overload protection (OLP) turns on. If an OCP signal longer than 4.8ms is detected , the MP6005 turns off the gate driver. After a 340ms delay, the MP6005 turns on again with the next cycle. During OLP, a 50µs one -shot timer is activated after one OCP pulse. This means if there is one OCP pulse in a 50µs period, the MP6005 registers this event as OCP. If the OCP condition is removed before 4.75ms, the MP6005 resumes normal operation. Short-Circuit Protection (SCP) When the output is shorted to GND, the MP6005 works in OCP mode and the current is limited cycle by cycle. If the peak current is not limited by the 160mV VSENSE in each cycle because of the gate driver’s minimum on time, the current may run out of control and the transformer may saturate. If VSENSE reaches 300mV, the MP6005 turns off the gate driver and enters hiccup protection with a 340ms off time. Once the short circuit is removed, VOUT recovers after a 340ms delay and then enters the next cycle. Soft Start (SS) The MP6005 employs soft start (SS) by charging an internal capacitor from a current source. During the soft -start period, the SS signal ramps up slowly. In the event of a command shutdown, thermal shutdown, or protection condition, t he soft -start capacitor is completely discharged. In PSR mode, the soft -start signal clamps the feedback VREF. From 0V to 2V, the feedback reference soft-start time is typically 4.7ms. In SSR mode, the soft-start signal clamps VCOMP until it reaches the switching current level. The soft-start signal continues to ramp up at the same rate. VCOMP’s ramp time from 1.5V to 3.5V is typically 4.7ms.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 19 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Minimum On Time The parasitic transformer capacitance and GATE signal create a current spike on the SENSE resistor when the power MOSFET turns on. The MP6005 includes a 250ns leading-edge blanking period to avoid false termination of the switching pulse. During this blanking period, the CS comparator turns off and the gate driver remains on. Gate Driver The MP6005 has a high-current gate driver for the primary-side N-channel MOS FET. This driver has strong driving capability and benefits for MOSFET selection by allowing the MOSFET’s V GS to be charged quickly . If QG is low, th en the switching speed should remain low as well. It is recommended to use a series resistor above 5Ω to reduce EMI. The MP6005 has a SYNC driver pin that controls the second switch. If SYNC is high, the second switch turns off. If SYNC is low, the second switch turns on. Figure 4 shows the phase and dead time relationships between the GATE and SYNC pins. tD tD 50% 50% GATE SYNC Figure 5: GATE and SYNC Driver Both GATE and SYNC maintain a low voltage if UVLO or a nother protection mode has turned off the IC. Transformer Inductance In PSR mode, the MP6005 samples VOUT during the flyback time, and the secondary diode conduct time with minimum peak current (controlled by 33mV minimum sense limit) should be longer than 0.7 µs. The transformer inductance can be calculated with Equation (2): 33mV R x0.7μ. x N N x )V+(V L SENSE S P DOFOUTPRI ≥ (2) Where LPRI is the transformer’s primary inductance, and VDOF is the output r ectifier diode’s forward drop. There is no inductance limit in SSR mode . However, if the IC is designed to work in continuous conduction mode ( CCM), set the peak current high to avoid triggering PSM , which may lead to a larger VOUT ripple, (particularly in SYNC mode forward topology). Thermal Shutdown Thermal shutdown prevents thermal runaway. If the silicon die temperature exceeds its upper threshold, the MP6005 turns off . Once the temperature returns to below its lower threshold, thermal shutdown ends and the device turns on again with the next new cycle.

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 22 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. leads to high switching los s, while a low Q G may cause fast turn -on/off speed, which determines the spike and kick. The turn -on threshold voltage (V TH) i s also important. The GATE pin is powered by V CC, so VTH must be lower than VCC. Selecting a Transformer for Flyback Application A transformer is an important component of a flyback converter because it determines the duty cycle, peak current, efficiency, MOSFET value, output diode rating, and more. A good transformer should account for the winding ratio, primary-side inductance, saturation current, leakage inductance, current rating, and core selection. The transformer winding ratio determines the duty cycle , which can be c alculated with Equation (10): OUT OUT IN N VD= N V V  (10) Where N is the primary winding transformer to output winding ratio, and D is the duty cycle. For most applications, it is recommended to have a duty cycle of about 45%. The primary -side inductance affects the inpu t current ripple ratio factor. A high inductance value results in a large transformer size and high cost . A low inductance value results in a high switching peak current and RMS current, which can decrease efficiency. Choose a primary-side induct or to set the current ripple ratio factor between 30% and 50%. The primary-side inductance can be estimated with Equation (11): SWIN IN P f x I x n x 2 D x V=L (11) Where n is the current ripple ratio, I IN is the input current, and LP is the primary inductance. Calculate L P based on the minimum input voltage condition. The transformer sho uld have a high saturation current to support the switching peak current; otherwise, the transformer inductance decreases sharply. The SENSE resistor can be used to limit the switching peak current. The energy stored in the leakage inductance cannot coupl e to the secondary side, which causes a high spike when the MOSFET turns off. This decreases efficiency and increases MOSFET stress. Normally, the transformer leakage inductance is less than 3% of the transformer inductance. The current rating counts the max imum RMS current, which allows current to flow through each winding. Uncontrolled current density can cause high resistive power loss. Setting the Diode Conduct Time (Only for PSR Flyback Mode) In PSR mode, the MP6005 starts sampling the auxiliary-winding voltage after the primary power MOSFET turns off. A 300ns blank ing time helps avoid spike ringing from the leakage inductance. To guarantee a sufficient sample FB period, the output diode ’s current- conduction time (tCON) should not exceed 600ns under light-load conditions. Design the transformer to ensure tCON exceeds 700ns when VSENSE_PK = 33mV, which can be estimated with Equation (12): 700ns) V+ (V x N x R N x L33mV x DOFOUTPSENSE SP ≥ (12) Where VDOF is the output diode’s forward-drop voltage. Resistance Capacitor Diode ( RCD) Snubber for Flyback Application The transformer leakage inductance causes spikes and excessive ringing on the drain voltage waveform . The RCD snubber circuit limits the voltage spike (see Figure 10). CSN DSN NP RSN AGND NS GATE MP6005 MOSFET PGND Figure 10: RCD Snubber The power dissipation of the snubber circuit can be estimated with Equation (13): SN K PEAK SW

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 24 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. D) - (1 x N x VD =V NI R (19) The QF maximum VDS voltage (VF) can be calculated with Equation (20): N V=V IN F (20) Where N is the transformer primary winding to output winding ratio , and D is the primary duty cycle. Some margin is typically necessary. The MOSFET current rating should exceed its maximum RMS current and peak current . The QR RMS current (IR) can be calculated with Equation (21): OUT PP OUTR )I I( x 3 1 + 1 x D x I=I (21) The QF RMS current (IF) can be calculated with Equation (22): OUT PP OUTF )I I( x 3 1 + 1 x D - 1 x I=I (22) Where IPP is the peak-to-peak current. Since one MOSFET’s drain is the other MOSFET’s gate, the Q R gate driver voltage is equal to V F, and the Q F gate driver voltage is equal to V R. If the driver voltage exceeds the maximum GATE voltage, a clamp circuit is required. The turn-on resistance determines the conduction loss, and QG determines the circuit driver loss. Both the turn -on resistance and QG should remain low to achieve high efficiency and low temperature rise. Selecting an Output Inductor for Forward The forward output inductor supplies constant current to the output load w hile the main power MOSFET turns on . A large r-value inductor results in less ripple current and a lower output voltage ripple. However, larger-value inductor s are larger in size, and have a higher series resistance and lower current saturation. To determine the inductance, allow the peak -to- peak ripple current in the inductor to b e approximately 30 % to 50% of the maximum output current. The inductance value can be calculated with Equation (23): OUT OUT SW L IN V V x NL = x (1 - )f x ΔIV (23) Where V OUT is the output voltage, V IN is the input voltage, fSW is the switching frequency, and ΔI L is the peak -to-peak inductor ripple current. Choose an inductor that does not saturate under the maximum inductor peak current. Selecting an Input Capacitor An input capacitor is required to supply the AC ripple current to the inductor while limiting noise at the input source. A low -ESR capacitor is required to minimize noise. It is recommended to use ceramic capacitors, but tantalum or low - ESR electrolytic capacitors can also be used . For ceramic capacitors, the capacitance dominates the input ripple at the switching frequency. In flyback mode, the input ripple can be estimated with Equation (24): ) V+ x V(N x C x f V x I=ΔV INOUTINSW IN ININ (24) Where ΔVIN is the in put voltage ripple, IIN is the input current, and CIN is the input capacitor. In forward mode, the input ripple can be estimated with Equation (25): OUTIN IN SW IN IN V x NIΔV = x (1- )f x C V (25) Equation (25) omits the primary-side inductance current that makes the current ripple smaller. Selecting an Output Capacitor The output capacitor maintains the DC output voltage. For the best results, it is recommended to use ceramic capacitors or low-ESR capacitors to minimize the output voltage ripple. For ceramic capacitors, the capacitance dominates the output ripple at the switching frequency. In flyback mode, the output ripple can be estimated with Equation (26): OUT OUT SWOUTIN OUT OUT C I x f x ) x VN + (V x VN=ΔV (26) If the voltage ripple is too high, place two capacitors on either side of the inductor to

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 28 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

PACKAGE INFORMATION

0.030(0.75) 0.002(0.05) 0.006(0.15) FRONT VIEW SIDE VIEW GAUGE PLANE 0.010(0.25) 0.016(0.40) 0.026(0.65) SEATING PLANE PIN 1 ID (NOTE 5) 0.114(2.90) 0.122(3.10) 0.187(4.75) 0.199(5.05) 1 5 610 0.007(0.18) 0.114(2.90) 0.122(3.10) TOP VIEW NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION, OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) PIN 1 IDENTIFICATION HAS THE HALF OR FULL CIRCLE OPTION. 6) DRAWING MEETS JEDEC MO-817, VARIATION BA. 7) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN 0.181(4.60) 0.040(1.00)

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER MP6005 Rev. 1.0 www.MonolithicPower.com 29 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package MP6005GK– Z MSOP10 2500 50 13in 12mm 8mm

MP6005 – WIDE-INPUT, HIGH-EFFICIENCY FLYBACK AND FORWARD CONTROLLER Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP6005 Rev. 1.0 www.MonolithicPower.com 30 2/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 2/5/2021 Initial Release -

Summary

High-Efficiency Flyback/Forward Controller with Primary and Secondary-Side Regulation 2/5/2021 Rev. 1.0

Description