MP3924GU

MP3924 MPS | Alldatasheet

Document overview

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Technical content

Quad-Port, IEEE 802.3af/at PSE Controller for Power over Ethernet MP3924 Rev. 1.0 MonolithicPower.com 1 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

DESCRIPTION

The MP3924 is a quad -port power source equipment (PSE) power controller for IEEE 802.3af/at compliant power over Ethernet (PoE) applications. The device has all the functions of IEEE 802.3af/at, including detection, single-event and two-event classification, current limit ing, and disconnected load detection. All of the functions can be configured to work in automatic operation mode or software program mode via the I2C. The MP3924 features a 9-bit analog-to-digital converter ( ADC) to monitor the current and voltage, a special I 2C interface for isolated controller communication, adjustable current limits, and configurable system funct ions. These features provide flexibility for P oE applications. The MP3924 is available in a QFN-32 (5mmx5mm) package.

FEATURES

 IEEE802.3af/at Compliant  Quad-Port and 4-Bit Configurable I2C Address  0.25Ω Current-Sense Resistor  Automatic Mode and I2C Command Control Mode  Automatic Input Over-Power Shutdown  Internal VCC Power Supply  Three-Wire I2C Interface for Isolated

Applications

 Two INT Pins for Interrupt Priority Selection  Disconnected DC Load Detection  Instantaneous Current/Voltage Readout  Thermal Protection  Available in a QFN-32 (5mmx5mm) Package  PSE Switches/Routers  PSE Midspan Power Injectors  Surveillance NVR and DVRs All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green s tatus, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION MP3924 VIN VIN = 54V C1 VCC EN AUTO MID OUTn Output Port x4 GATEn SENSEn SGNDx PGNDDGND SCL SDAO SDAI INT1 PMAX INT2 Note: Only One Port is Shown Here CLS5 CH1: VOUTx - VVIN 20V/div. Start-Up for Class 4 PD 100ms/div.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 2 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number Package Top Marking MSL Rating MP3924GU* QFN-32 (5mmx5mm) See Below 2 EVKT-MP3924 Evaluation kit - * For Tape & Reel, add suffix -Z (e.g. MP3924GU-Z). TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP3924: Part number LLLLLLL: Lot number EVALUATION KIT EVKT-MP3924 EVKT-MP3924 kit contents ( items listed below can be ordered separately, and the GUI installation file and supplemental documents can be downloaded from the MPS website): # Part Number Item Quantity

1 EV3924-U-00A MP3924 evaluation board 1

2 EVKT-USBI2C-02 Includes one USB to I2C communication interface device, one USB

cable, and one ribbon cable 1

3 MP3924GU MP3924 controller IC 2

Order directly from MonolithicPower.com or our distributors. USB to PMBus Communication Interface (EVKT-USBI2C-02) USB Cable Ribbon Cable Input Power Supply Load Input Output Evaluation Board Figure 1: EVKT-MP3924 Evaluation Kit Set-Up

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 3 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PACKAGE REFERENCE TOP VIEW 9 10 11 12 13 14 2930 25262728 15 16 3132 GATE2 SENSE2 OUT3 GATE3 SENSE3 OUT4SENSE1 OUT2 OUT1 INT2 SGND1 CLS5 AUTO GATE1 MID INT1 SENSE4 VIN PMAX VCC PGND GATE4 SGND2 DGND SDAI EN A0 A1 A2 A3SCL SDAO QFN-32 (5mmx5mm)

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 4 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 GATE1 MOSFET gate driver for port 1. Float the GATE1 pin if not used.

2 OUT1

Output voltage sense pin for port 1. Connect OUT1 to the output interface return for detecting, classif ying, voltage sensing, and current limit fold back control. Float the OUT1 pin if not used.

3 INT2

High-priority interrupt request pin. INT2 pulls low when the selected high -priority interrupt source register is set and the interrupt is enabled. INT2 is an o pen-drain output. Connect INT2 to DGND if the interrupt function is not used.

4 SGND1

Current sense negative input for port 1 and port 2. Connect SGND1 to the low-side terminal of the sense resistor. For an accurate current sense, use a Kelvin connection when connecting SGND1 to the PCB. Connect SGND1 to DGND if not used.

5 CLS5

Class 5 enable input . CLS5 is internally pulled down to DGND through a 50kΩ resistor. Leave CLS5 disconnected to disable the classification for Class 5 devices (IEEE 802.3at - compliant mode). Connect CLS5 to V CC to enable the classification of Class 5 devices. CLS5’s status is latched when the device starts up, or after a reset condition. If CLS5 ’s status changes after start-up, there is no effect.

6 AUTO

Automatic mode setting pin. AUTO is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ resistor can be added). Float the AUTO pin to make automatic mode the default. Connect the AUTO pin to DGND to make shutdown mode the default. AUTO’s status is latched when the device starts up, or after a reset condition . If AUTO ’s status changes after start-up, there is no effect.

7 MID

Midspan mode setting . MID is i nternally pulled up to VCC through a 50kΩ resistor ( an external 10kΩ resistor can be added ). Float the MID pin for midspan mode, then wait 2.8s to reinitiate detection . Connect the M ID pin to DGND to disable midspan mode. MID’s status is latched when the device starts up, or after a reset condition . If MID ’s status changes after start-up, there is no effect.

8 INT1

Interrupt request pin for all interrupt source event s. INT1 pulls low when the interrupt register is set and the interrupt function is enabled. INT1 is an o pen-drain output. Connect INT1 to DGND if the interrupt function is not used. 9 SCL I2C clock input pin. Connect SCL to VCC using an external pull -up resistor (typically 4.7kΩ). Connect SCL to VCC if the I2C interface is not used.

10 SDAO

I2C serial data output pin. SDAO is an o pen-drain output. Connect SDAO to VCC using an external pull -up resistor (typically 4.7k Ω). Connect SDAO to S DAI for non-isolated applications. Connect SDAO to DGND if the I2C interface is not used.

11 SDAI

I2C serial data input pin. Connect SDAI to VCC using an external pull -up resistor (typically 4.7k Ω). Connect SDAI to SDAO for non-isolated application s. Connect SDAI to DGND if the I2C interface is not used. 12 EN Enable input . EN turns all internal circuit s and four ports (except the VCC regulator ) on and off. To turn on the device automatically, externally connect EN to VCC. 13 A0 MP3924 address setting pin. Connect A0 to VCC or DGND to set the lower 4-bit address bits (address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up or is reset . A0 is i nternally pulled up to V CC through a 50kΩ resistor (an external 10kΩ resistor can also be added). 14 A1 MP3924 address setting pin. Connect A1 to VCC or DGND to set the lower 4-bit address bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up or is reset A1 is i nternally pulled up to V CC through a 50kΩ resistor (an external 10kΩ resistor can also be added).

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 5 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PIN FUNCTIONS (continued) Pin # Name Description 15 A2 MP3924 address setting pin. Connect A2 to VCC or DGND to set the lower 4-bit address bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up or is reset . A2 is i nternally pulled up to VCC through a 50kΩ resistor (an external 10kΩ resistor can be added). 16 A3 MP3924 address setting pin. Connect A3 to VCC or DGND to set the lower 4-bit address bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up or is reset . A3 is i nternally pulled up to V CC through a 50kΩ resistor (an external 10kΩ resistor can also be added). 17 DGND Ground of the internal digital and analog circuit.

18 SGND2

Current sense negative input for port 3 and port 4. Connect SGND2 to the low-side terminal of the sense resistor. For an accurate current sense, use a Kelvin connection when connecting SGND2 to the PCB. Connect SGND2 to DGND if not used. 19 PGND Ground of input power supply. 20 VCC 3.3V internal regulator output for analog and digital circuit supply. A minimum 1µF ceramic capacitor must be placed between VCC and DGND.

21 PMAX

Maximum loading power setting pin. Connect one resistor from th e PMAX pin to DGND to set the total power capability on all four output ports. The MP3924 limits the total power on all four ports below this set limit. The PMAX setting signal is latched when the device starts up or is reset. 22 VIN Power supply input for both V CC and output port s. Bypass VIN with at least one 0.1µF/100V ceramic capacitor, placed between VIN and PGND.

23 SENSE4

Current-sense pin from the high-side sense resistor terminal for port 4. It is recommended to use a 0.25Ω sense resistor for all application s. For an accurate current sense, use a Kelvin connection when connecting SENSE4 during PCB layout . Connect SENSE4 to DGND if not used. 24 GATE4 MOSFET gate driver for port 4. Float the GATE4 pin if not used.

25 OUT4

Output voltage sense pin for port 4. Connect OUT4 to the return of the output interface for detec ting, classif ying, voltage sens ing, and current limit foldback control. Float the OUT4 pin if not used.

26 SENSE3

Current-sense pin from the high-side sense resistor terminal for port 3. It is recommended to use a 0.25Ω sense resistor for all application s. For an accurate current sense, use a Kelvin connection when connecting S ENSE3 during PCB layout . Connect SENSE3 to DGND if not used. 27 GATE3 MOSFET gate driver for port 3. Float the GATE3 pin if not used.

28 OUT3

Output voltage sense pin for port 3. Connect OUT3 to the return of the output interface for detect ing, classif ying, voltage s ensing, and current limit foldback control. Float the OUT3 pin if it is not used.

29 SENSE2

Current-sense p in from the high-side sense resistor terminal for port 2. It is recommended to use a 0.25Ω sense resistor for all application s. For an accurate current sense, use a Kelvin connection when connecting SENSE1 during PCB layo ut. Connect SENSE1 to DGND if not used. 30 GATE2 MOSFET gate driver for port 2. Float the GATE2 pin if not used.

31 OUT2

Output voltage sense pin for port 2. Connect OUT2 to the return of the output interface for detect ing, classif ying, voltage sens ing, and current limit f oldback control. Float the OUT2 pin if it is not used.

32 SENSE1

Current-sense pin from the high-side sense resistor terminal for port 1. It is recommended to use a 0.25Ω sense resistor for all application s. For an accurate current sense, use a Kelvin connection when connecting SENSE1 during PCB layout . Connect SENSE1 to DGND if not used.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 6 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) INT1, INT2, SDAO maximum sink current……... Continuous power dissipation (TA = 25°C) Recommended Operating Conditions (3) INT1, INT2, SDAO maximum sink current……... Operating junction temp (TJ). ... -40°C to +125°C Thermal Resistance θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature , TJ (MAX), the junction -to- ambient thermal r esistance, θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can cause excessive die temperature, and the regulator may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on EV3924-U-00A, 2-layer, 88mmx106mm PCB. 5) The value of θJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51 -7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 7 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN = 54V, PGND, DGND, SGND1 , and SGND2 are connected together, R SENSE = 0.25Ω, TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Power Supply Input under-voltage lockout (UVLO) VIN_UVLO VIN rising 28 29.5 31 V Input UVLO hysteresis VIN_UVLO_HYS 2.7 V Input over-voltage lockout (OVLO) VIN_OVP VIN rising 62 65 68 V Input OVLO hysteresis VIN_OVP_HYS 2.8 V Input OVP lockout delay (7) 100 µs Input power okay threshold VIN_OK VIN rising 38 40 42 V Input power okay hysteresis VIN_OK_HYS 0.7 V EN logic high voltage VHI 2.5 V EN logic low voltage VLI 0.4 V EN input current Pull EN to 0V, 3.3V 0 µA EN turn on/off delay tEN_ON EN pin high pulse duration for start-up or low-pulse duration for shutdown 150 µs tEN_OFF 120 Supply current IIN Logic pin is floating, no connection for all output ports, AUTO = low 2 4 mA Shutdown current ISD EN = 0V 150 µA VCC regulation VCC Load = 0mA 3.3 V Load = 15mA 3.2 VCC UVLO VCC_UVLO VCC rising 2.3 2.5 2.7 V VCC UVLO hysteresis VCC_UV_HYS 170 mV VCC current limit VCC = DGND 17 mA Power-on reset (POR) delay tPOR From VCC on to detection 0.5 ms Detection First detection voltage VDET1 Test the VIN to OUTx pins 3.6 4 V Second detection voltage VDET2 Test the VIN to OUTx pins 7.2 8 V Detection voltage slew rate VSLEW CDET = 0.1µF 0.02 V/µs Detection current limit IDET_LIMIT Short VIN to OUTx 1 1.2 1.5 mA Short-circuit detection threshold VSC First detection voltage 1 1.5 1.8 V Open-circuit current threshold IOPEN 10 15 25 µA

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 8 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 54V, PGND, DGND, SGND1 , and SGND2 are connected together, R SENSE = 0.25Ω, TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Minimum valid detection resistance RGOODL 15 17 19 kΩ Maximum valid detection resistance RGOODH 26.5 30 33 kΩ Maximum valid capacitance CGOOD_MAX 1 9 µF Detection time tDET Second detection phase 280 310 ms Detection reset time tRESET Port reset by internal discharge between VIN and OUTx before detection starts 80 100 ms Midspan mode detection delay tMIDDLY Re-detection interval, MID = 1 2.8 sec Power removal detection delay tREMDLY Re-detection after one power removal event due to error condition (ICUT, ILIM, INRUSH), fault timer = 60ms MID = 0, automatic and semi- automatic mode 0.8 0.96 1.12 sec Classification Classification output voltage VCLS Test VIN to OUTx pins during classification, load < 60mA 16 18 20 V Classification current limit ICLS_ILIM Short VIN to OUTx 70 mA Class event time tCLE 8 15 22 ms Mark event voltage VMARK Test VIN to OUTx pins 7.6 8.8 9.8 V Mark event current limit IMARK_ILIM Short VIN to OUTx 6 10 14 mA Mark event time tME 6.5 9 11 ms Classification current threshold ICLS Class 0 to 1 5.5 6.5 7.5 mA Class 1 to 2 13.5 14.5 15.5 mA Class 2 to 3 21.5 23 24.5 mA Class 3 to 4 31.5 33 34.5 mA Class 4 to over-current (OC) condition (or Class 5 (8)) 45.5 48 50.5 mA Port start-up delay tPON Automatic mode from detection ending to power port above 21V 100 ms Manual mode, from command to output port above 21V 3 ms Port shutdown delay From command off to gate < 1V 0.5 ms Start-up sequence delay (9) From one channel detection to the next channel detection if the first channel powers up in automatic mode 0.5 sec

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 9 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 54V, PGND, DGND, SGND1 , and SGND2 are connected together, R SENSE = 0.25Ω, TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Gate Driver GATE source capability ISOURCE Port start-up, VGATE = GND -43 µA GATE sink capability ISINK Port shutdown, VGATE = 10V 60 µA Port shutdown, VGATE < 1V 9 mA Trigger SCP, VSENSE = 450mV, VGATE = 5V (7) 100 mA GATE clamp voltage VGS_MAX Float GATE pin 10 V OUT Pin OUT pin resistance ROUT Between VIN and OUTx, pull OUTx high in idle state (detection/classification off, port shutdown) 0.2 MΩ OUT pin bias current IOUT OUTx = 0V, port start-up -270 µA OUTx = 54V, port shutdown 1 µA Protection Output power good (PG) rising threshold VPG OUTx pin voltage decrease 1.5 2 2.5 V Output PG hysteresis VPG_HYS 400 mV PG delay Low to high deglitch 3 ms High to low deglitch 10 µs Current limit threshold VILIM Class 0~3, ILIMx bit = 0 101 106.25 111.5 mV Class 4, ILIMx bit = 1 201 212.5 224 mV Class 5, ILIMx bit = 1 251.75 265 278.25 mV Over-current (OC) detection threshold VCUT Class 0~3 (ICUTx = 000) 89.06 93.75 98.44 mV Class 4 (ICUTx = 100) 154.38 162.5 170.63 mV Class 5 (ICUTx = 101) 218.5 230 241.5 mV Current limit timer tILIM TILIM = 11 50 60 70 ms OC timer tICUT TCUT = 10 50 60 70 ms Start inrush current limit timer tINRUSH TINRUSH = 10 50 60 70 ms Foldback initial voltage VFOLD_ST OUTx pin voltage when ILIM decreases, ILIMx bit = 0 32 V OUTx pin voltage when ILIM decreases, ILIMx bit = 1 18 V Foldback end voltage VFOLD_END OUTx pin voltage when ILIM decreases to minimum value 46 V Foldback minimum current limit VLIM_MIN Short VIN to OUTx, FBLIMT bit = 1, Class 4 40 mV Short VIN to OUTx, FBLIMT bit = 0, Class 4 22 mV

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 10 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 54V, PGND, DGND, SGND1 , and SGND2 are connected together, R SENSE = 0.25Ω, TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Short circuit fast-off threshold VSCP ILIMx bit = 0 212 mV ILIMx bit = 1 425 mV Sense pin bias current -1 +1 µA Thermal shutdown (7) 150 °C Thermal shutdown hysteresis (7) 25 °C Total Load Power Limit Load power limit on all four ports PMAX RMAX = 49.9kΩ 49.9 W RMAX = 120kΩ 120 W Maximum load capability on all four ports PMAX_LIMT Float the PMAX pin 204.8 W Maximum load power protection delay tMAX_DLY TPMAX bit = 10 100% x PMAX < load < 150% x PMAX 60 ms Load > 150% x PMAX 2 ms DC Load Disconnection DC disconnect hold threshold VDCHOLD Decrease output load until output port power off 1.25 1.875 2.5 mV DC connect power time tDCON Load time to reset tDCOFF timer 37.5 43.75 50 ms DC disconnect power remove time tDCOFF Time from load < VDCHOLD to gate off 300 350 400 ms Analog-to-Digital Converter (ADC) ADC resolution 9 bits Max ADC current range ADC results = 1 1111 1111 (2.4mA/count) 1.216 A Max ADC voltage range ADC results = 1 1111 1111 (0.15V/count) 76.65 V ADC junction temperature range ADC results = 0 0000 0000 to 1 1111 1111 (0.4°C/count) -40 +164.4 °C Max ADC PMAX setting range ADC results = 1 1111 1111 (0.4W/count) 204.8 W Current conversion I = 600mA 254 count Voltage conversion V = 44V 293 count V = 57V 380 count Temperature conversion (7) TJ = 25°C 163 count TJ = 125°C 413 count PMAX setting conversion RMAX = 49.9kΩ 125 count RMAX = 120kΩ 300 count

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 11 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 54V, PGND, DGND, SGND1 , and SGND2 are connected together, R SENSE = 0.25Ω, TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Logic Interface (SCL, SDAI, SDAO, INT1, INT2, MID, A0, A1, A2, A3, AUTO, CLS5) Input logic low voltage VLI 0.4 V Input logic high voltage VHI 2 V Logic input current For SCL, SDAI -1 +1 µA Open-drain output logic low voltage VLO Sink current = 3mA, SDAO, INT1, INT2 0.4 V Open-drain output logic high leakage Open drain to 3.3V 1 µA Internal pull-up/down Resistance RUP A0, A1, A2, A3, AUTO, MID to VCC, CLS5 to DGND 50 kΩ Notes: 6) Guaranteed by over-temperature correlation. 7) Guaranteed by engineering sample characterization. 8) If CLS5 is enabled, the MP3924 treats the classification current range from the upper of class 4 to the classification current limit as class 5. 9) Guaranteed by detection time, classification time, and start-up delay time.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 12 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS VIN = 54V, TA = 25°C, unless otherwise noted. 100 120 140 160 180 200 25 30 35 40 45 50 55 60 SHUTDOWN CURRENT (μA) INPUT VOLTAGE (V) VIN Shutdown Current vs. Input Voltage 1.2 1.4 1.6 1.8 2.2 2.4 25 30 35 40 45 50 55 60 SUPPLY CURRENT (mA) INPUT VOLTAGE (V) VIN Supply Current vs. Input Voltage 100 150 200 250 -50 0 50 100 150 SHUTDOWN CURRENT (μA) JUNCTION TEMPERATURE (℃) VIN Shutdown Current vs. Junction Temperature 1.2 1.4 1.6 1.8 2.2 2.4 -50 0 50 100 150 VIN SUPPLY CURRENT (mA) JUNCTION TEMPERATURE (℃) VIN Supply Current vs. Junction Temperature -50 0 50 100 150 VIN UVLO (V) JUNCTION TEMPERATURE (℃) VIN UVLO vs. Junction Temperature Rising Falling -50 0 50 100 150 VIN OVP THRESHOLD (V) JUNCTION TEMPERATURE (℃) VIN OVP vs. Junction Temperature Rising Falling

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 13 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN = 54V, TA = 25°C, unless otherwise noted. 0.5 1.5 2.5 -50 0 50 100 150 EN UVLO (V) JUNCTION TEMPERATURE (℃) EN UVLO vs. Junction Temperature Rising Falling 2.1 2.2 2.3 2.4 2.5 2.6 -50 0 50 100 150 VCC UVLO (V) JUNCTION TEMPERATURE (℃) VCC UVLO vs. Junction Temperature Rising Falling 2.7 2.8 2.9 3.1 3.2 3.3 3.4 -50 0 50 100 150 VCC VOLTAGE (V) JUNCTION TEMPERATURE ( C) VCC Voltage vs. Junction Temperature VCC load = 15mA -50 0 50 100 150 DETECTION VOLTAGE (V) JUNCTION TEMPERATURE (℃) Detection Voltage vs. Junction Temperature Second Detection First Detection -50 0 50 100 150 VALID DETECTION RESISTANCE (kΩ) JUNCTION TEMPERATURE (℃) Valid Detection Resistance vs. Junction Temperature Maximum Resistance Minmum Resistance -50 0 50 100 150 CLASS VOLTAGE (V) JUNCTION TEMPERATURE (℃) Class Voltage vs. Junction Temperature

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 14 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL CHARACTERISTICS (continued) VIN = 54V, TA = 25°C, unless otherwise noted. -50 0 50 100 150 MARK VOLTAGE (V) JUNCTION TEMPERATURE (℃) Mark Voltage vs. Junction Temperature -50 0 50 100 150 CLASS CURRENT (mA) JUNCTION TEMPERATURE (℃) Class Current vs. Junction Temperature Class 4 to OCP Class 3 to 4 Class 2 to 3 Class 1 to 2 Class 0 to 1 100 150 200 250 -50 0 50 100 150 ICUT LIMIT (mV) JUNCTION TEMPERATURE (℃) ICUT Limit vs. Junction Temperature Class 4 Class 0 100 150 200 250 -50 0 50 100 150 ILIM LIMIT (mV) JUNCTION TEMPERATURE (℃) ILIM Limit vs. Junction Temperature Class 4 Class 0 1.5 1.6 1.7 1.8 1.9 2.1 -50 0 50 100 150 DC HOLD THRESHOLD (mV) JUNCTION TEMPERATURE (℃) DC Hold Threshold vs. Junction Temperature 100 105 110 115 -50 0 50 100 150 INRUSH CURRENT LIMIT (mV) JUNCTION TEMPERATURE (℃) Inrush Current Limit vs. Junction Temperature

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 15 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted. No PD Connection Class 0~3 PD Connection CH1: VOUTx - VVIN 2V/div. CH1: VOUTx - VVIN 20V/div. 100ms/div. 100ms/div. Class 4 PD Connection Start-Up through VIN No PD connection CH1: VOUTx - VVIN 20V/div. R1: VIN 50V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. 100ms/div. 400ms/div. Start-Up through VIN Class 4 PD connection Shutdown through VIN No PD connection R1: VIN 50V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. R1: VIN 50V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. 400ms/div. 400ms/div.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 16 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted. Shutdown through VIN Class 4 PD connection Start-Up through EN No PD connection R1: VIN 50V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. R1: VEN 2V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. 400ms/div. 400ms/div. Start-Up through EN Class 4 PD connection Shutdown through EN No PD connection R1: VEN 2V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. R1: VEN 2V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. 400ms/div. 400ms/div. Shutdown through EN Class 4 PD connection PMAX Limit Triggered (10) R1: VEN 2V/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. R1: IIN 500mA/div. CH4: OUT4 50V/div. CH3: OUT3 50V/div. CH2: OUT2 50V/div. CH1: OUT1 50V/div. 400ms/div. 400ms/div. Note: 10) The maximum power (PMAX) is set to 50W. If the load’s power exceeds 50W, port 4 shuts down with default priority.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 17 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted. ICUT Triggered ILIM Triggered CH2: VIN 20V/div. CH1: OUT1 20V/div. CH4: IOUT1 500mA/div. CH2: VIN 20V/div. CH1: OUT1 20V/div. CH4: IOUT1 500mA/div. 20ms/div. 20ms/div. Output SCP Triggered Inrush Current Limit Triggered CH2: VIN 20V/div. CH1: OUT1 20V/div. CH4: IOUT1 1A/div. CH2: VIN 20V/div. CH1: OUT1 20V/div. CH4: IOUT1 1A/div. 100ms/div. 100ms/div. Output Disconnection Triggered CH2: VIN 20V/div. CH1: OUT1 20V/div. CH4: IOUT1 100mA/div. 200ms/div.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 18 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM GATE Driver Control GATE 1~4 SENSE 1~4 SGND 1~2 ICUT, ILIM, Inrush, Disconnect . Control Detection Classification OUT 1~4 ADC VCC LDO UVLO OVP VIN VCC EN Enable PSE Interface Logic Control AUTO MID Register Memory I2C SCL SDAI SDAO PGND DGND A3~A0 CLS5 VIN 4V, 8V 8.8V, 18V Current Sense INT1 INT2 Watchdog VIN, Temp, PMAX PMAX Output Port x4 VIN Figure 2: Functional Block Diagram

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 22 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. controlled by the ICUTx bits), then a timer (tICUT) is enabled to record the OC condition. 8The port turns once this timer finishes counting. If the load current exceeds VCUT and triggers V ILIM / RSENSE, then the GATE pin regulates the load at the current limit level . An additional timer (tILIM) is enabled to record the current limit event . tILIM is counted even if the MP3924 is in current foldback mode. VCUT detects the OC threshold, which is be low the VILIM threshold. tICUT starts counting when the OC condition begins. If the load current drops below VCUT, tICUT does not reset immediately. I nstead, tICUT counts down at a rate that is 1/16 of how quickly is counts up. The tICUT timer records for a total of 60ms for every 0.96s + 0.06s detection window. If the port shuts down due to an OC condition, the port can be re -enabled only after tICUT counts down to 0. This logic can detect a short or repeated OC condition. The logic also protects the external MOSFET from overheating. tILIM and tNRUSH operate with the same logic. The over -current protection ( OCP) timer does not reset even if the device shuts down or the EN bit turns off. This means that the port cannot be re-enabled until the timer counts to 0 again. In manual mode, the host should read the Read and Clear register address continuously until the register is reset to 0 . Then the port is re- enabled. I n auto matic mode, the MP3924 automatically restarts after the timer counts down to 0. When tICUT is completed, the related OUT port shuts down (see Figure 10). At the same time, the POWER_STATUS and OVER_LOAD_STATUS registers are set to indicate the power condition. The default VCUT is different for Classes 0~3 than Class 4 and Class 5. V CUT can also be configured. VILIM has three fixed values for Classes 0~3, Class 4, and Class 5. t OUTx Pin VIN ILIM Current tCUT ICUT <60ms 60ms SR1SR2 SR1 = 16 x SR2 OCP >0.96s Detect. t t Figure 10: ICUT Over-Current Detection The GATE pin typically has a 43µA source current capability for current limit regulation , which means that the output voltage maximum start-up slew rate can be controlled by I GATE / CGD (CGD is the capacitance betwee n the external MOSFET’s gate and drain) . When the GATE pin’s voltage is pulled down to 1V by a weak discharge current , the voltage is latched to 0V with a strong pull-down current until the next start-up event. If the load current ramps up quickly and trigger s the VSCP fast-off voltage threshold, the MP3924 shuts down port power quickly to protect the MOSFET. The load at the current limit level is regulated until the timer (tILIM) counts down. The MP3924 shuts down the corresponding output port if an ICUT or ILIM event occurs, and the related fault bits are set . The following registers are also affected:  The PGx and PENx bits in the POWER_STATUS register are cleared.  The DET/CLS_RESULTx register and PORTx_VOLTAGE/CURRENT register are cleared.  The PGCx and PECx bits in the POWER_STATUS_CHANGE register are set.  The ICUTx and ILIMx bits are cleared. Current Foldback During an overload or short-circuit condition, the MP3924 limits the current through the sense resistor by control ling the external MOSFET. The MOSFET loses power due to the rising drain voltage. To reduce power loss and protect the MOSFET, reduce the current limit when the drain voltage rises.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 25 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. the PD input voltage is high, a 250ms discharge timer works with a 100kΩ load between the OUTx pin and VIN . If the PD input exceeds 2.4V, a secondary 500ms discharge timer begins. If the PD input voltage does not fall below 2.4V after the two discharge times , then the MP3924 is set to 0010 in the LEGACY_DETECT_RESULTx registers. After legacy detection starts, a fixed current is charged to the PD input . The voltage difference between two points is used t o calculate the effective capacitance. If the capacitance is too great and the measured voltage difference is below 0.5V, then th e MP3924 reports 0 110. If the capacitance is too low and the measured voltage reaches 18.5V, then the MP3924 reports 0100 or 0101. All of these results are invalid in legacy detection. Table 1: Legacy Detection Measurements Parameter Value Units Minimum measurable capacitance 5 µF Maximum measurable capacitance 100 µF Capacitance test charge current 500 µA Nominal measurement time 150 ms Maximum voltage before start measurement 2.4 V Duration of first port discharge period 250 ms Duration of second port discharge period 500 ms Maximum voltage during measurement 18.5 V If legacy detect ion is enabled and a legacy device is detected in automatic mode , then the detection status is r eported in the LEGACY_DETECT_RESULTx registers. However, the device does not start up immediately, as it require s a host command through the I2C. If LEGENx is set to 01 or 10 in automatic or semi-automatic mode , there is initially one standard detecting cycle . If the standard resistance detection result is valid, then the MP3924 does not continue legacy detect ion and the classification process begins instead. If the standard resistance detect ion result is not valid and legacy detection is valid, the MP3924 does not start the classification process, even if the CLSENx bit is set . In this scenario, a software command is required to trigger the classification process. If the following conditions are met, then PON automatically powers the port (even if the classification result does not match, or there is an OC condition):  PON is enabled by the software after the legacy detection is determined to be valid.  The MP3924 is in automatic or semi - automatic mode. If the LEGENx bit is enabl ed in automatic or semi-automatic mode , the legacy detection result repeats and re freshes the LEGACY_DETECT_RESULTx registers. This process repeats until the LEGENx bit is disabled. In manual mode, legacy detection occurs once, then the LEGENx bits resets automatically. It is recommended to use manual mode. Operation Modes The MP3924 provides four operation modes to flexibly control PoE communication and start-up: automatic mode, semi-automatic mode, manual mode, and shutdown mode. The AUTO pin and the MODEx bits set the different modes, which are described below in greater detail. Automatic Mode In automatic mode, the MP3924 automatically controls and responds to all detection, classification, and start-up function s. The MP3924 handles these processes for each port independently and without external I2C control. Float the AUTO pin to force the MP3924 to work in automatic mode. In automatic mode, the MODEx bits are set to 11 when device turns on. The AUTO pin status is only read once when the device turns on o r the MP3924 is reset. If a master is connected to the MP3924 via the I2C, then th e master can change the MODEx bits to change the operation mode. If there is no valid PD on the port in automatic mode, th en th e MP3924

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 26 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. repeats the detection cycle until a valid PD is connected. If the MP3924 runs in automatic mode after start-up or reset, the DETENx and CLSENx bits are set high based on the AUTO pin. If a port is set to automatic mode via the I2C, the DETENx and CLSENx bits do not change. Semi-Automatic Mode In semi-automatic mode, the MP3924 automatically detects and classifies the connected PD. However, the port does not start up until an I 2C command is issued. Set the MODEx bits to 10 to force the MP3924 to operate in semi-automatic mode. When the port is set to semi-automatic mode, the DETENx and CLSENx bits to not change. If the DETENx and CLSENx bits are high in semi- automatic mode, the port repeats the detection (and classification if the PD detection result is valid) continuously. However, the port does not start up until an I 2C command is issued. If the detection and classification are valid , the port power can be turned on by a PONx bit. If the port is powered off in semiautomatic mode, the DETENx and CLSENx bits are reset to 0. If the detection is valid and the port does not turn on within 400ms in automatic or semi - automatic mode , th en the port initiates a new detection sequence. If the final detection and classification sequences are determined to be invalid before the start-up command is received, the device fails to turn on. At the same time, the STFx bit is set and the MP3924 resets the command. If the detection and classification sequences are valid but a start-up command is not issued after 400ms, then the STFx bit is set. Manual Mode In manual mode, all functions are controlled via the I2C interface. Manual mode is recommended for system diagnostics. S et the MODEx bits to 01 to force the ports to operate in manual mode. In manual mode, the DETENx and CLSENx bits are set to 0 . Set these bits to 1 to enable one- time detection or classification. These bits reset to 0 automatically. The PONx bits power the port in manual mode. The port turns on any time the PONx bit is set. If the DETENx, CLSENx, and PONx bits are set simultaneously, then the MP3924 executes a detection cycle first. If the DETENx and CLSENx bits are set after the port starts up, the MPM3924 ignores the DETENx and CLSENx commands. The RDETx and RCLSx bits follow the same logic. If a PONx command is received while the device recovers from a protection, the n the MP3924 does not turn on and t he failur e is reported to the STFx bit. Shutdown Mode In shutdown mode, a ll detection, classification , and port power output functions are off. To force the MP3924 to operate in shutdown mode, pull the AUTO pin to DGND before the device starts up or resets. Set the MODEx bits to 00 to set a port to shutdown mode. Once a port is in shutdown mode, the power is turned off and the corresponding port event/status registers are cleared, except for the PECx and PGCx bits. The I2C interface still operates in shutdown mode , but the port s do not respond to any detect ion, classification, or port start-up commands. In certain AUTO pin configurations, the MODE bits are set to 00 or 11 after start-up (or after a reset). After start-up, all ports can switch between the four modes. The registers and port states are not chan ged by these bits unless shutdown mode is selected. 9-Bit ADC The MP3924 integrates a 9 -bit analog-to-digital converter (ADC) to continuously measure the input voltage, output voltage, l oad current, and junction temperature. The ADC also measures PMAX once following start-up, or if the device is reset. When any ADC information is required, the host controller can read the corresponding data register s. ADC conversion only works when the port is enabled and if there is no data update for the corresponding port when the port is shut down. The register cannot be update d while it is read, even if ADC conversion is complete for that segment of data. I2C Interface The MP3924 features an I2C interface. The 7-bit device address is defined as 010 xxxx, where

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 28 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. the acknowledgement clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that i t remains low during the high period of this clock pulse. Figure 17 shows the data transfer sequence. After the start condition (S), a slave address is sent. This address is 7 bits long followed by an 8th data direction bit (R/W). A 0 indicates a transmission ( write), while a 1 indicates a request for data ( read). A data transfer is always terminated by a stop condition (P) generated by the master. However, if a master must communicate on the bus, it can generate a repeated start condition (Sr) and address another slave without first generating a stop condition. Start Condition Stop Condition Address Data Data Figure 17: Complete Data Transfer The MP3924 includes a full I2C slave controller. The I 2C slave fully complies with I2C specification requirements. It requires a start condition, a valid I 2C address, a register address byte, and a data byte for a single data update. The MP3924 acknowledges that it has received each byte by pulling the SDA line low during the high period of a single clock pulse. A valid I 2C address selects the MP3924. The MP3924 performs an update on the falling edge of the LSB byte. Figure 18 shows a n I 2C write example. S Slave Address Wr A Register Address K Write DataA A P

8 Bits 8 Bits 8 Bits

A = Acknowledge (SDA = Low) S = Start Condition P = Stop ConditionNA = Not Acknowledge (SDA = High) Write (Wr) = 0 Read (Rd) = 1 Figure 18: I2C Write Example Figure 19 shows an I2C write example. S Slave Address Wr A Register Address K Read Data KA A P Master to Slave Slave to Master A = Acknowledge (SDA = Low) S = Start Condition P = Stop ConditionNA = Not Acknowledge (SDA = High)

8 Bits

Write (Wr) = 0 Read (Rd) = 1 Register address to read specified Read register data from current register location Sr = Repeat Start Condition Figure 19: I2C Read Example Figure 20 shows that the 0x00C address has a different read command from the standard I2C. S 0x0C Rd A Interrupted Device Address P Master to Slave Slave to Master A = Acknowledge (SDA = Low) S = Start Condition P = Stop ConditionNA = Not Acknowledge (SDA = High)

8 Bits 8 Bits

Write (Wr) = 0 Read (Rd) = 1 Read device address data by alert response address Sr = Repeat Start Condition Figure 20: 0x0C Read Example

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 29 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Watchdog The MP3924 implements a watchdog to monitor the SCL line for I 2C activity. If there is no transition on the SCL line for about 2.5s during I2C communication, then the I2C port and all power output ports shut down. The WDS bit is set to 1 to indicate the error condition. WDS must be reset before any port can be re - enabled. After watchdog protection is triggered, the port shuts down until the host re -enables the ENx bits. By default, the watchdog is off after start-up. To enable the watchdog function, set the WDEN bit to 1. Over-Temperature Protection (OTP) Over-temperature protection ( OTP) is implemented to prevent the chip from thermal runaway. When the junction temperature exceeds its upper threshold, the MP3924 shuts down all ports (the I2C and register s still work). Once the temperature drops below its recovery threshold, the ports are enabled again with a new detection cycle. The OTP bit is set to 1 after OTP recovery.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 30 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. REGISTER DESCRIPTION Register Map Addr Register Type D7 D6 D5 D4 D3 D2 D1 D0 Reset State Interrupt Register 00h INTERRUPT R VINF STF OCP CLSC DETC DCDIS PGC PEC 1000 0000 01h INTERRUPT_ MASK R/W VINF_ M STF_ M OCP_ M CLSC_ M DETC_ M DCDIS_ M PGC_ M PEC_ M 1A A0 0A00 (11) 02h INTERRUPT_ PRIORITY R/W VINF_ P STF_ P OCP_ P CLSC_ P DETC_ P DCDIS_ P PGC_ P PEC_ P 1010 0000 Configuration Register 03h MODE_SETTING R/W MODE4 MODE3 MODE2 MODE1 AAAA AAAA (11) 04h MIDSPAN_ SETTING R/W - - - - MID4 MID3 MID2 MID1 0000 MMMM (11) 05h PORT_ENABLE R/W - - - ENAL EN4 EN3 EN2 EN1 0001 1111 06h DET/CLS_ENABLE R/W CLSEN LCSEN CLSEN CLSEN DETEN

4 DETEN3 DETEN

1 AAAA AAAA (11)

07h DISCONNECT_ ENABLE R/W - - - - DISEN

4 DISEN3 DISEN

2 DISEN1 0000 AAAA (11)

08h FAULT_TIMER R/W TPMAX TINRUSH TILIM TCUT 1010 1110 09h RESERVED - - - - - - - - - 0000 0000 0Ah RESERVED - - - - - - - 0000 0000 0Bh FOLDBACK_ILIM R/W - - - - - - - FBLIMT 0000 0001 0Ch 2-EVENT_CLASS_ 5_ENABLE R/W CLS5_ EN4 CLS5_ EN3 CLS5_ EN2 CLS5_ EN1 2EVNT EN4 2EVNTEN3 2EVNT EN2 2EVNT EN1 CCCC AAAA (11) 0Dh PMAX_ SHUTDOWN_ PRIORITY R/W PRTY4 PRTY3 PRTY3 PRTY1 1110 0100 0Eh INTERRUPT_ ENABLE R/W - - - - - CLRPIN CLRAI NT INTEN 0000 0001 0Fh GENERAL_ CONTROL R/W - - - - - PMAXEN ADCEN WDEN 0000 0A 10 (11) Manual Control Register 10h DET/CLS_ TRIGGER R/W RCLS4 RCLS3 RCLS2 RCLS1 RDET4 RDET3 RDET2 RDET1 0000 0000 11h POWER_ON/OFF_ TRIGGER R/W POFF4 POFF3 POFF2 POFF1 PON4 PON3 PON2 PON1 0000 0000 12h LEGACY_ENABLE R/W LEGEN4 LEGEN3 LEGEN2 LEGEN1 0000 0000 Current Limit Configuration Register 13h ICUT1_ THRESHOLD R/W - - - - - ICUT1 0000 0000 14h ICUT2_ THRESHOLD R/W - - - - - ICUT2 0000 0000 15h ICUT3_ THRESHOLD R/W - - - - - ICUT3 0000 0000 16h ICUT4_ THRESHOLD R/W - - - - - ICUT4 0000 0000 17h ILIM1_ THRESHOLD R/W - - - - - - - ILIM1 0000 0000 18h ILIM2_ THRESHOLD R/W - - - - - - - ILIM2 0000 0000 19h ILIM3_ THRESHOLD R/W - - - - - - - ILIM3 0000 0000 1Ah ILIM4_ THRESHOLD R/W - - - - - - - ILIM4 0000 0000 Status Register 20h POWER_ SOURCE_ STATUS1 R FETF4 FETF3 FETF2 FETF1 VCCUV OTP VINOV VINUV 0000 1001 21h R/C (12) 22h POWER_ SOURCE_ STATUS2 R - - - - - - VINOK OVP MAX 0000 0000 23h R/C (12) 24h DET/CLS_ COMPLETE_ STATUS R R/C (12) CLSC4 CLSC3 CLSC2 CLSC1 DETC4 DETC3 DETC2 DETC1 0000 0000 25h 26h DET/CLS_ RESULT_1 R CLSR1 2EVNT C1 DETR1 0000 0000 27h DET/CLS_ RESULT_2 R CLSR2 2EVNT C2 DETR2 0000 0000 28h DET/CLS_ RESULT_3 R CLSR3 2EVNT C3 DETR3 0000 0000 29h DET/CLS_ RESULT_4 R CLSR4 2EVNT C4 DETR4 0000 0000 2Ah POWER_STATUS R PG4 PG3 PG2 PG1 PEN4 PEN3 PEN2 PEN1 0000 0000 2Bh POWER_ STATUS_ CHANGE R PGC4 PGC3 PGC2 PGC1 PEC4 PEC3 PEC2 PEC1 0000 0000 2Ch R/C (12)

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 31 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Addr Register Type D7 D6 D5 D4 D3 D2 D1 D0 Reset State 2Dh OVER_LOAD_ STATUS R OCUT4 OCUT3 OCUT2 OCUT1 STF4 STF3 STF2 STF1 0000 0000 2Eh R/C (12) 2Fh CURRENT_LIMIT_ STATUS R - - - - OLIM4 OLIM3 OLIM2 OLIM1 0000 0000 30h R/C (12) 31h DISCONNECT_ STATUS R - - - - DCDIS

4 DCDIS3 DCDIS2 DCDIS1 0000 0000 32h R/C (12)

33h WATCHDOG_ STATUS R - - - - - - - WDS 0000 0000 34h PIN_STATUS R - - - AUTO A3 A2 A1 A0 000A DDDD (11) 35h LEGACY_ DETECT_ RESULT1 R LEGDET2 LEGDET1 0000 0000 36h LEGACY_ DETECT_ RESULT2 R LEGDET4 LEGDET3 0000 0000 ADC Results Register 40h PORT_1_ CURRENT 41h R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 42h OUT1_PIN_ VOLTAGE 43h R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 44h PORT_2_ CURRENT 45h R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 46h OUT2_PIN_ VOLTAGE 47h R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 48h PORT_3_ CURRENT 49h R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 4Ah OUT3_PIN_ VOLTAGE 4Bh R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 4Ch PORT_4_ CURRENT 4Dh R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 4Eh OUT4_PIN_ VOLTAGE 4Fh R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 50h INPUT_VOLTAGE R - - - - - - - Bit [0] 0000 0000 51h R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 52h JUNCTION_ TEMPERATURE 53h R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000 54h PMAX_POWER_ SETTING 55h R/W Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] PPPP PPPP (11) 60h DIE_ID R FAB MAJOR _REV MINOR _REV VENDO R_ID 0000 0000 - - - - Notes: 11) “A” represents the AUTO pin’s status during start-up. “M” represents the MID pin’s status during start-up. “C” represents CLS5 pin’s status during start-up. “D” represents the A3~A0 address pin status es during start-up. “P” represents the PMAX pin setting ADC results during start-up. 12) R/C is read and clear address. Reading R/C clears the bit status after reading is complete.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 32 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. INTERRUPT REGISTERS INTERRUPT (00h) Read-only Bits Bit Name Default Value Description D[7] VINF 1 Interrupt signal for VIN power failure. If this bit is set to 1, one of the following scenarios has occurred:  The power on VIN is below 29.5V  VIN over-voltage protection (OVP)  VCC is under the under-voltage lockout (UVLO) threshold  Thermal shutdown  A power MOSFET failure  A PMAX event D[6] STF 0 Interrupt signal for a start-up failure. If this bit is set to 1, at least one of the ports has experienced a start -up failure, or if a port shuts down due to the start -up inrush current. D[5] OCP 0 Interrupt signal for over-current (OC) conditions. If this bit is set to 1, at least one of the ports has met the ILIMT current limit timer or the ICUT OC timeout condition. D[4] CLSC 0 Interrupt signal for classification completion. This bit is set to 1 if at le ast one port has completed its classification process. D[3] DETC 0 Interrupt signal for detection completion. This bit is set to 1 if at least one port has completed its detection process. D[2] DCDIS 0 Interrupt signal for a disconnected DC load. This bit is set to 1 if at least one port has had its DC load disconnected (load < 7.5mA). D[1] PGC 0 Interrupt signal for power good (PG) status change. This bit is set to 1 if at least one port has a new PG status. D[0] PEC 0 Interrupt signal for power enable status change. This bit is set to 1 if at least one port has changed its enable or disable status. Read the register addre ss with an R/C byte, or write 1 to CLRAIN to reset the corresponding bit. The IN1 and INT2 pins go low to report if an interrupt bit is set to 1. These pins do not go low if the interrupt signal is masked. INTERRUPT_MASK (01h) Read/write Bits Bit Name Default Value Description D[7] VINF_M 1 Masks the interrupt signal for V IN power failure s. Set this bit to 0 to disable the interrupt function. D[6] STF_M A Masks the interrupt signal for start -up failures. Set this bit to 0 to disable the interrupt function. D[5] OCP_M A Masks the interrupt signal for over-current (OC) conditions. Set this bit to 0 to disable the interrupt function. D[4] CLSC_M 0 Masks the interrupt signal for classification completion. Set this bit to 0 to disable the interrupt function. D[3] DETC_M 0 Masks the interrupt signal for detection completion . Set this bit to 0 to disable the interrupt function. D[2] DCDIS_M A Masks the interrupt sign al for DC load disconnect ion. Set this bit to 0 to disable the interrupt function. D[1] PGC_M 0 Masks the interrupt signal for power good (PG) status change interrupt. Set this bit to 0 to disable the interrupt function.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 33 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. D[0] PEC_M 0 Masks the interrupt signal for power enable status change interrupt. Set this bit to 0 to disable the interrupt function. Write 1 to enable the interrupt function; write 0 to disable the interrupt function. “A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low. These bits only disable the response from the INT1 and INT2 pins . T he corresponding interrupt bit always changes. The device cannot mask certain interruptions during start -up or a reset event, including VIN under-voltage lockout (UVLO) and VCC UVLO. INTERRUPT PRIORITY (02h) Read/write Bits Bit Name Default Value Description D[7] VINF_P 1 Selects if the INT2 pin responds to a VIN power failure interrupt signal. D[6] STF_P 0 Selects if the INT2 pin responds to a start-up failure interrupt signal. D[5] OCP_P 1 Selects if the INT2 pin responds to an over-current (OC) interrupt signal. D[4] CLSC_P 0 Selects if the INT2 pin responds to a classification completion interrupt signal. D[3] DETC_P 0 Selects if the INT2 pin responds to a detection completion interrupt signal. D[2] DCDIS_P 0 Selects if the INT2 pin responds to a DC load disconnect interrupt signal. D[1] PGC_P 0 Selects if the INT2 pin responds to a power good (PG) status cha nge interrupt signal. D[0] PEC_P 0 Selects if the INT2 pin responds to a power enable status change interrupt signal. If a bit is set to 1, the INT2 pin pulls low in response to the corresponding interrupt signal. The INT1 pin responds to all interrupt sources, as long as they are not masked. INT2 only respond s to the interrupt sources that are not masked.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 34 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CONFIGURATION AND CONTROL REGISTERS OPERATION_MODE_SETTING (03h) Read/write Bits Bit Name Default Value Description D[7:6] MODE4 AA Sets the operation mode for ports 1 through 4. “ A” is 1 if the AUTO pin is set hig h during start-up or a reset. “A” is 0 if the AUTO pin is set low. The status is latched only during start-up or a reset. This can be changed via the I2C. 00: Shutdown mode. The port is off, and there is no detection or classification process 01: Manual mode. There is no automatic state change 10: Semi -automatic mode. The detection and classification processes are automated, but the port does not turn on automatically 11: Automatic mode. Start-up, as well as detection and classification processes, are automated D[5:4] MODE3 AA D[3:2] MODE2 AA D[1:0] MODE1 AA MIDSPAN_SETTING (04h) Read/write Bits Bit Name Default Value Description D[7:4] RESERVED - Reserved. D[3] MID4 M Sets the midspan mode for ports 1 through 4. “M” is “1” if the MID pin is high during start-up or a reset. “M” is “0” if MID pin is low. These changes can be configured by writing to the I2C. Set this bit to 1 to enable midspan mode for the corresponding port. D[2] MID3 M D[1] MID2 M D[0] MID1 M PORT_ENABLE (05h) Read/write Bits Bit Name Default Value Description D[7:5] RESERVED - Reserved. D[4] ENAL 1 Enables the MP3924. If this bit is set to 1, a ll internal IC circuits are enabled. Each port is enabled if the ENAL and EN x bits are set to 1. If ENAL is disabled, the I2C continues to operate, but the ports are shut down. D[3] EN4 1 Enables ports 1 through 4. These bits can disable the corresponding port, which includes detection and classification processes, reset s the port and status registers, and shut s down the port . If a port is already turned off and these bits are set to 0, then there is no change. 1: Enabled 0: Disabled D[2] EN3 1 D[1] EN2 1 D[0] EN1 1 DET/CLS_ENABLE (06h) Read/write Bits Bit Name Default Value Description D[7] CLSEN4 A Enables the classification process for the corresponding port. Set these bits to 1 to enable classification. D[6] CLSEN3 A D[5] CLSEN2 A D[4] CLSEN1 A D[3] DETEN4 A Enables the detection process for the corresponding port. Set these bits to 1 to enable detection. D[2] DETEN3 A D[1] DETEN2 A D[0] DETEN1 A

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 35 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. “A” is “1” if the AUTO pin is set high during start -up or a reset. “A” is “0 ” if the AUTO pin is set low. In automatic and semi-automatic mode, the detection and classification processes are enabled when the bit is set to 1. In manual made, set the bit to 1 for one -time detection or classification. Then the bit is reset to 0. DISCONNECT_ENABLE (07h) Read/write Bits Bit Name Default Value Description D[7:4] RESERVED - Reserved. D[3] DISEN4 A Enables DC load disconnection for ports 1 through 4. “A” is 1 if the AUTO pin is set high during start-up or a reset. “A” is 0 if the AUTO pin is set low. If these bits are set to 1, the DC load disconnection function is enabled on the corresponding port. D[2] DISEN3 A D[1] DISEN2 A D[0] DISEN1 A FAULT_TIMER (08h) Read/write Bits Bit Name Default Value Description D[7:6] TPMAX 10 Sets the total power overload timer after start-up. 00: 15ms 01: 30ms 10: 60ms 11: 120ms D[5:4] TINRUSH 10 Sets the start-up inrush current timer for all ports. 00: 15ms 01: 30ms 10: 60ms 11: 120ms D[3:2] TILIM 11 Sets the current limit trigger timer after start-up for all ports. 00: 7.5ms 01: 15ms 10: 30ms 11: 60ms D[1:0] TCUT 10 Set the over-current (OC) timer after start-up for all ports. 00: 15ms 01: 30ms 10: 60ms 11: 120ms The timer begins counting up after a load triggers the threshold. If the current drops below the threshold, the timer begins counting down at 1/16 of the rising rate. If it times out, the port shuts down. The port cannot be redetected once the timer counts down to 0. FOLDBACK_ILIM (0Bh) Read/write Bits Bit Name Default Value Description D[7:1] RESERVED - Reserved. D[0] FBLIMT 1 Sets the foldback over-current (OC) threshold when the OUTx pin exceeds 46V. 0: The foldback current limit is 22mV (88mA if RSENSE = 0.25Ω). 1: The foldback current limit is 40mV (160mA RSENSE = 0.25Ω).

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 36 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 2-EVENT_AND_CLASS_5_ENABLE (0Ch) Read/write Bits Bit Name Default Value Description D[7] CLS5_EN4 C Enables Class 5 classification for all ports. If these bits are set to 1, Class 5 classification is enabled on the corresponding port, and the default current limit can support up to 40W of power. D[6] CLS5_EN3 C D[5] CLS5_EN2 C D[4] CLS5_EN1 C D[3] 2EVNTEN4 A Enables two-event classification for all ports. If these bits are set to 1, two -event classification is enabled when the first classification result on the port is Class 4 or Class 5. D[2] 2EVNTEN3 A D[1] 2EVNTEN2 A D[0] 2EVNTEN1 A “A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low. “C” is “1” if the CLS5 pin is set high during start-up or a reset. “ C” is “0” if the CLS5 pin is set low. The CLS5 pin has a high power level under the IEEE802.3 at classification, but it is not a standard class level that is compatible with IEEE802.3. PMAX_SHUTDOWN_PORT_PRIORITY (0Dh) Read/write Bits Bit Name Default Value Description D[7:6] PRTY4 11 Sets the shutdown priority for all ports after the PMAX limit is triggered. If the value is the same on several ports, priority is arranged based on the default priority. For example, if both port 1 and port 2 are 00, then port 2 shuts down first. 11: The lowest priority port, which shuts down first if the PMAX limit is triggered 10: The third level priority port if the PMAX limit is triggered 01: The second level priority port if the PMAX limit is triggered 00: The highest priority port, which shuts down last if the PMAX limit is triggered D[5:4] PRTY3 10 D[3:2] PRTY2 01 D[1:0] PRTY1 00 INTERRUPT_ENABLE_CONTROL (0Eh) Read/write Bits Bit Name Default Value Description D[7:3] RESERVED - Reserved. D[2] CLRPIN 0 Controls the reset function for the INT1 and INT2 pin s. If this bit is set to 1, resetting the INT1 and INT2 pins does not affect the registers. This bit is automatically set to 0 after the INT1 and INT2 pins are reset. D[1] CLRAINT 0 Controls the reset function for the i nterrupt source . If this bit is set to 1, all registers and the INT1 and INT2 bit are reset . This bit is automatically set to 0 after the INT1 and INT2 pins are reset. D[0] INTEN 1 Enables the interrupt function. This bit does not affect the event register. If this bit is set to 1, the interrupt function is enabled. GENERAL_ENABLE_CONTROL (0Fh) Read/write Bits Bit Name Default Value Description D[7:3] RESERVED - Reserved. D[2] PMAXEN A Enables the maximum total load power limit. If this bit = 1, automatic shutdown is triggered when the PMAX pin reaches its maximum input power setting. D[1] ADCEN 1 Enables the ADC. If this bit = 1, the ADC is enabled. D[0] WDEN 0 Enables the I2C watchdog. If this bit is set to 0, the watchdog is disabled. “A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 37 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. MANUAL MODE AND LEGACY DETECTION CONTROL REGISTERS DET/CLS_TRIGGER (10h) Read/write Bits Bit Name Default Value Description D[7] RCLS4 0 Re-enables the classification function on all ports. If these bits are set to 1, a one - time classification event is enabled on the corresponding port. These bits are reset after classification is complete. D[6] RCLS3 0 D[5] RCLS2 0 D[4] RCLS1 0 D[3] RDET4 0 Re-enables the detection function on all ports. If these bits are set to 1, a one -time detection even t is enabled on the corresponding port. These bits are reset after detection is complete. D[2] RDET3 0 D[1] RDET2 0 D[0] RDET1 0 In manual mode, one-time detection or classification occurs after the corresponding bit is set. In semi - automatic or automatic mode, detection and classification are controlled by the DETENx and CLSENx bits. These processes are repeated once they are enabled. POWER_ON/OFF_TRIGGER (11h) Read/write Bits Bit Name Default Value Description D[7] POFF4 0 Triggers a shutdown on the corresponding port. If these bits are set to 1, the port powers off. The bit automatically resets afterward. D[6] POFF3 0 D[5] POFF2 0 D[4] POFF1 0 D[3] PON4 0 Triggers start -up on the corresponding port. If these bits are set t o 1, the corresponding port powers on. These bits are reset after start -up is complete. The device performs a detection cycle first if the DETENx and PONx bits are set simultaneously. The PONx bits are operational in manual mode. If the port is powered on or in shutdown mode, the port does not respond to these bits. The PONx bits are operational in semi -automatic mode. The port responds to these bits if the detection and classification results are valid. The PONx bits are only functional during legacy detection if the device is set to automatic mode. For all modes, the PONx bits may be cleared by DET/CLS/LEGACY_DET failures, start-up failures, or if the PON signal lasts for 400ms when the port is operational. D[2] PON3 0 D[1] PON2 0 D[0] PON1 0 LEGACY_ENABLE (12h) Read/write Bits Bit Name Default Value Description D[7:6] LEGEN4 00 Enables legacy detection mode for all ports. 00: Legacy detection is disabled 01: Legacy detection is enabled while standard detection is disabled 10: Legacy detection is enabled after standard detection is complete 11: Reserved D[5:4] LEGEN3 00 D[3:2] LEGEN2 00 D[1:0] LEGEN1 00

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 38 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CURRENT LIMIT CONFIGURATION REGISTER ICUT1_THRESHOLD (13h) Read/write Bits Bit Name Default Value Description D[7:3] RESERVED - Reserved. D[2:0] ICUT1 000 Sets port 1’s over-current (OC) threshold. The default value is 000. In auto matic mode, the bits are set to 000 fo r Class 0~3 results, 100 for Class 4 results, and 101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not change unless changes are made via the I2C. 000 = 93.75mV (375mA with RSENSE = 0.25Ω) 001 = 27.5mV (110mA with RSENSE = 0.25Ω) 010 = 47mV (188mA with RSENSE = 0.25Ω) 011 = 93.75mV (375mA with RSENSE = 0.25Ω) 100 = 162.5mV (650mA with RSENSE = 0.25Ω) 101 = 230mV (920mA with RSENSE = 0.25Ω) 110 = 125mV (500mA with RSENSE = 0.25Ω) 111 = 156.25mV (625mA with RSENSE = 0.25Ω) ICUT2_THRESHOLD (14h) Read/write Bits Bit Name Default Value Description D[7:3] RESERVED - Reserved. D[2:0] ICUT2 000 Sets port 2’s over-current (OC) threshold. The default value is 000. In auto matic mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and 101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not change unless changes are made via the I2C. 000 = 93.75mV (375mA with RSENSE = 0.25Ω) 001 = 27.5mV (110mA with RSENSE = 0.25Ω) 010 = 47mV (188mA with RSENSE = 0.25Ω) 011 = 93.75mV (375mA with RSENSE = 0.25Ω) 100 = 162.5mV (650mA with RSENSE = 0.25Ω) 101 = 230mV (920mA with RSENSE = 0.25Ω) 110 = 125mV (500mA with RSENSE = 0.25Ω) 111 = 156.25mV (625mA with RSENSE = 0.25Ω) ICUT3_THRESHOLD (15h) Read/write Bits Bit Name Default Value Description D[7:3] RESERVED - Reserved. D[2:0] ICUT3 000 Sets port 3’s over-current (OC) threshold. The default value is 000. In auto matic mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and 101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not change unless changes are made via the I2C. 000 = 93.75mV (375mA with RSENSE = 0.25Ω) 001 = 27.5mV (110mA with RSENSE = 0.25Ω) 010 = 47mV (188mA with RSENSE = 0.25Ω) 011 = 93.75mV (375mA with RSENSE = 0.25Ω) 100 = 162.5mV (650mA with RSENSE = 0.25Ω) 101 = 230mV (920mA with RSENSE = 0.25Ω) 110 = 125mV (500mA with RSENSE = 0.25Ω) 111 = 156.25mV (625mA with RSENSE = 0.25Ω)

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 39 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ICUT4_THRESHOLD (16h) Read/write Bits Bit Name Default Value Description D[7:3] RESERVED - Reserved. D[2:0] ICUT4 000 Sets port 4’s over-current (OC) threshold. The default value is 000. In auto matic mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and 101 for Class 5 results. In semi -automatic mode or manual mode, t he bits do not change unless changes are made via the I2C. 000 = 93.75mV (375mA with RSENSE = 0.25Ω) 001 = 27.5mV (110mA with RSENSE = 0.25Ω) 010 = 47mV (188mA with RSENSE = 0.25Ω) 011 = 93.75mV (375mA with RSENSE = 0.25Ω) 100 = 162.5mV (650mA with RSENSE = 0.25Ω) 101 = 230mV (920mA with RSENSE = 0.25Ω) 110 = 125mV (500mA with RSENSE = 0.25Ω) 111 = 156.25mV (625mA with RSENSE = 0.25Ω) ILIM1_THRESHOLD (17h) Read/write Bits Bit Name Default Value Description D[7:1] RESERVED - Reserved. D[0] ILIM1 0 Sets port 1’s over-current (OC) limit. The default value is 0. In automatic mode, the bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi- automatic mode and manual mode, the bits do not change unless changes are made via the I2C. 0: 106.25mV (425mA if RSENSE = 0.25Ω) 1: 212.5mV. The current limit is 265mV under Class 5 conditions ILIM2_THRESHOLD (18h) Read/write Bits Bit Name Default Value Description D[7:1] RESERVED - Reserved. D[0] ILIM2 0 Sets port 2’s over-current (OC) limit. The default value is 0. In automatic mode, the bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi- automatic mode and manual mode, the bits do not change unless changes are made via the I2C. 0: 106.25mV (425mA if RSENSE = 0.25Ω) 1: 212.5mV. The current limit is 265mV under Class 5 conditions ILIM3_THRESHOLD (19h) Read/write Bits Bit Name Default Value Description D[7:1] RESERVED - Reserved. D[0] ILIM3 0 Sets port 3’s over-current (OC) limit. The default value is 0. In automatic mode, the bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi- automatic mode and manual mode, the bits do not change unless changes are made via the I2C. 0: 106.25mV (425mA if RSENSE = 0.25Ω) 1: 212.5mV. The current limit is 265mV under Class 5 conditions

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 40 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ILIM4_THRESHOLD (1Ah) Read/write Bits Bit Name Default Value Description D[7:1] RESERVED - Reserved. D[0] ILIM4 0 Sets port 4’s over-current (OC) limit. The default value is 0. In automatic mode, the bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi- automatic mode and man ual mode, the bits do not change unless changes are made via the I2C. 0: 106.25mV (425mA if RSENSE = 0.25Ω) 1: 212.5mV. The current limit is 265mV under Class 5 conditions

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 41 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. STATUS REGISTERS POWER_SOURCE_STATUS1 (20h and 21h) (20h) Read-only (21h) Read and clear Bits Bit Name Default Value Description D[7] FETF4 0 Indicates whether an external power MOSFET failure has occurred. This bit is set to 1 if the external MOSFET on the corresponding port has failed. If this occurs, the current limit cannot be reached, or the OUTx pin is high after start-up. D[6] FETF3 0 D[5] FETF2 0 D[4] FETF1 0 D[3] VCCUV 1 Indicates whether a VCC under-voltage condition has occurred. This bit is set to 1 if VCC has recovered from a shutdown or reset condition. D[2] OTP 0 Indicates whether an over-temperature (OT) condition has occurred. This bit is set to 1 if the junction temperature exceeds 150 °C. For more details, see the Over- Temperature Protection (OTP) section on page 28. D[1] VINOV 0 Indicates whether a VIN over-voltage (OV) condition has occurred. This bit is set to 1 if VIN exceeds 65V. D[0] VINUV 1 Indicates whether a VIN under-voltage (UV) condition has occurred . This bit is set to 1 if VIN drops below 29.5V. Read and Clear (0x21h) means that the bit is reset after a read operation. If read on 0x20h, the bits are not cleared. POWER_SOURCE_STATUS2 (22h and 23h) (22h) Read-only (23h) Read and clear Bits Bit Name Default Value Description D[7:2] RESERVED - Reserved. D[1] VINOK 0 Indicates whether the VIN source power is working normally. This bit is set to 1 if VIN exceeds 40V. D[0] OVPMAX 0 Indicates whether a power overload condition has occurred . This bit is set to 1 i f the total power load on all ports exceeds the PMAX threshold set by the PMAX pin. DET/CLS_COMPLETE_STATUS (24h and 25h) (24h) Read-only (25h) Read and clear Bits Bit Name Default Value Description D[7] CLSC4 0 Indicates whether a port has completed its classification process. These bits are set to 1 if classification has completed on the corresponding bit. D[6] CLSC3 0 D[5] CLSC2 0 D[4] CLSC1 0 D[3] DETC4 0 Indicates whether a port has completed its detection process. These bits are set to 1 if detection has completed on the corresponding bit. D[2] DETC3 0 D[1] DETC2 0 D[0] DETC1 0

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 42 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. DET/CLS_RESULT1 (26h) Read-only Bits Bit Name Default Value Description D[7:4] CLSR1 0000 Returns the classification result for port 1. 0000: Classification is not done 0001: Class 1 0010: Class 2 0011: Class 3 0100: Class 4 0101: Class 5 0110: Class 0 0111: Over-current (OC) condition 1000: The first and secondary class results do not match If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any current exceeding Class 4’s upper limit is considered an OC condition. D[3] 2EVNTC1 0 Indicates whether two-event classification has been completed on port 1. This bit is set to 1 if two -event classification has been completed. This bit is only set once Class 4 and Class 5 are successfully detected. D[2:0] DETR1 000 Indicates port 1’s detection result. 000: Detection has not completed (default after a power-on reset) 001: The port is shorted (VIN - OUT < 1.5V) 010: CDET too high (exceeds 5µF) 011: RDET is too low (below 19kΩ) 100: Detection is valid (19kΩ < RDET < 26.5kΩ) 101: RDET is too high (exceeds 26.5kΩ) 110: The port is open (<15µA load current) 111: Low impedance to PGND (OUT - PGND < 2V) DET/CLS_RESULT2 (27h) Read-only Bits Bit Name Default Value Description D[7:4] CLSR2 0000 Returns the classification result for port 2. 0000: Classification is not done 0001: Class 1 0010: Class 2 0011: Class 3 0100: Class 4 0101: Class 5 0110: Class 0 0111: Over-current (OC) condition 1000: The first and secondary class results do not match If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a Class 5 result. An OC condition triggers a current limit. If Class 5 is dis abled, any current exceeding Class 4’s upper limit is considered an OC condition. D[3] 2EVNTC2 0 Indicates whether two-event classification has been completed on port 2. This bit is set to 1 if two -event classification has been completed. This bit is only set once Class 4 and Class 5 are successfully detected.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 43 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. D[2:0] DETR2 000 Indicates port 2’s detection result. 000: Detection has not completed (default after a power-on reset) 001: The port is shorted (VIN - OUT < 1.5V) 010: CDET too high (exceeds 5µF) 011: RDET is too low (below 19kΩ) 100: Detection is valid (19kΩ < RDET < 26.5kΩ) 101: RDET is too high (exceeds 26.5kΩ) 110: The port is open (<15µA load current) 111: Low impedance to PGND (OUT - PGND < 2V) DET/CLS_RESULT3 (28h) Read-only Bits Bit Name Default Value Description D[7:4] CLSR3 0000 Returns the classification result for port 3. 0000: Classification is not done 0001: Class 1 0010: Class 2 0011: Class 3 0100: Class 4 0101: Class 5 0110: Class 0 0111: Over-current (OC) condition 1000: The first and secondary class results do not match If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any current exceeding Class 4’s upper limit is considered an OC condition. D[3] 2EVNTC3 0 Indicates whether two-event classification has been completed on port 3. This bit is set to 1 if two -event classification has been completed. This bit is only set once Class 4 and Class 5 are successfully detected. D[2:0] DETR3 000 Indicates port 3’s detection result. 000: Detection has not completed (default after a power-on reset) 001: The port is shorted (VIN - OUT < 1.5V) 010: CDET too high (exceeds 5µF) 011: RDET is too low (below 19kΩ) 100: Detection is valid (19kΩ < RDET < 26.5kΩ) 101: RDET is too high (exceeds 26.5kΩ) 110: The port is open (<15µA load current) 111: Low impedance to PGND (OUT - PGND < 2V) DET/CLS_RESULT4 (29h) Read-only Bits Bit Name Default Value Description D[7:4] CLSR4 0000 Returns the classification result for port 4. 0000: Classification is not done 0001: Class 1 0010: Class 2 0011: Class 3 0100: Class 4 0101: Class 5 0110: Class 0 0111: Over-current (OC) condition 1000: The first and secondary class results do not match If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any current exceeding Class 4’s upper limit is considered an OC condition.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 44 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. D[3] 2EVNTC4 0 Indicates whether two-event classification has been completed on port 4. This bit is set to 1 if two -event classification has been completed. This bit is only set once Class 4 and Class 5 are successfully detected. D[2:0] DETR4 000 Indicates port 4’s detection result. 000: Detection has not completed (default after a power-on reset) 001: The port is shorted (VIN - OUT < 1.5V) 010: CDET too high (exceeds 5µF) 011: RDET is too low (below 19kΩ) 100: Detection is valid (19kΩ < RDET < 26.5kΩ) 101: RDET is too high (exceeds 26.5kΩ) 110: The port is open (<15µA load current) 111: Low impedance to PGND (OUT - PGND < 2V) POWER_STATUS (2Ah) Read-only Bits Bit Name Default Value Description D[7] PG4 0 Indicates the power good (PG) status for all ports. This bit is set to 1 if the corresponding port’s power is on, and if the OUTx pin’s voltage is below VPG. The PG bit resets once the OUTx pin’s voltage exceeds the VPG threshold with a short deglitch time. D[6] PG3 0 D[5] PG2 0 D[4] PG1 0 D[3] PEN4 0 Indicates whether power has been enabled on a port. These bits are set to 1 if the corresponding port is powered on. D[2] PEN3 0 D[1] PEN2 0 D[0] PEN1 0 POWER_STATUS_CHANGE (2Bh and 2Ch) (2Bh) Read-only (2Ch) Read and clear Bits Bit Name Default Value Description D[7] PGC4 0 Indicates whether the power good (PG) status has changed on the ports. This bit is set to 1 if the PG status changes on the corresponding port. D[6] PGC3 0 D[5] PGC2 0 D[4] PGC1 0 D[3] PEC4 0 Indicates whether the power status has been enabled or disabled on the ports. This bit is set 1 if the power status changes (disabled or enabled) on the corresponding port. D[2] PEC3 0 D[1] PEC2 0 D[0] PEC1 0 OVER_LOAD_STATUS (2Dh and 2Eh) (2Dh) Read-only (2Eh) Read and clear Bits Bit Name Default Value Description D[7] OCUT4 0 Indicates whether the ICUT1~4 timer (t ICUT) has finished counting af ter ICUTx exceeds the over-current (OC) threshold. This bit is set to 1 if tICUT times out. D[6] OCUT3 0 D[5] OCUT2 0 D[4] OCUT1 0 D[3] STF4 0 Indicates a start -up failure for all ports. This bit is set to 1 if start-up inrush timer times out, or if there is a power-on command failure. D[2] STF3 0 D[1] STF2 0 D[0] STF1 0

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 45 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CURRENT_LIMIT_STATUS (2Fh and 30h) (2Fh) Read-only (30h) Read and clear Bits Bit Name Default Value Description D[7:4] RESERVED - Reserved. D[3] OLIM4 0 Indicates whether a hardware current limit has been triggered on the ports. These bits are set to 1 if a current limit is triggered on a corresponding port. D[2] OLIM3 0 D[1] OLIM2 0 D[0] OLIM1 0 DISCONNECT_STATUS (31h and 32h) (31h) Read-only (32h) Read and clear Bits Bit Name Default Value Description D[7:5] RESERVED - Reserved. D[3] DCDIS4 0 Indicates whether a disconnected DC load event has occurred on the ports. These bits are set to 1 if a disconnected DC load event occurs on the corresponding port. D[2] DCDIS3 0 D[1] DCDIS2 0 D[0] DCDIS1 0 WATCHDOG_STATUS (33h) Read-only Bits Bit Name Default Value Description D[7:1] RESERVED - Reserved. D[0] WDS 0 Indicates the watchdog status. This bit is set to 0 if the watchdog times out without an active CLK signal. PIN_STATUS (34h) Read-only Bits Bit Name Default Value Description D[7:5] RESERVED - Reserved. D[4] AUTO A Returns the AUTO pin’s status during start-up. “A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0 ” if the AUTO pin is set low. This bit is set to 1 if the AUTO pin is pulled high. D[3] A4A3 D Returns the A3~A0 pins’ statuses during start-up. “D” is “1” if the corresponding pin is set high during start -up or a reset. “ D” is “0” if the corresponding pin is set low. These bits are set to 1 if the corresponding pin’s voltage is high. D[2] A3A2 D D[1] A2A1 D D[0] A1A0 D LEGACY_DETECT_RESULT1 (35h) Read-only Bits Bit Name Default Value Description D[7:4] LEGDET2 0000 Returns the legacy detection results for port 2. 0000: No legacy detection 0001: Valid (5µF < PD input capacitor < 100µF) 0010: Unable to discharge the PD input capacitance to 2.4V 0100: The first measurement exceeds the 18.5V maximum voltage 0101: The second measurement exceeds the 18.5V maximum voltage 0110: The difference between the measured voltages is below 0.5V

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 46 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. D[3:0] LEGDET1 0000 Returns the legacy detection results for port 1. 0000: No legacy detection 0001: Valid (5µF < PD input capacitor < 100µF) 0010: Unable to discharge the PD input capacitance to 2.4V 0100: The first measurement exceeds the 18.5V maximum voltage 0101: The second measurement exceeds the 18.5V maximum voltage 0110: The difference between the measured voltages is below 0.5V LEGACY_DETECT_RESULT2 (36h) Read-only Bits Bit Name Default Value Description D[7:4] LEGDET4 0000 Returns the legacy detection results for port 4. 0000: No legacy detection 0001: Valid (5µF < PD input capacitor < 100µF) 0010: Unable to discharge the PD input capacitance to 2.4V 0100: The first measurement exceeds the 18.5V maximum voltage 0101: The second measurement exceeds the 18.5V maximum voltage 0110: The difference between the measured voltages is below 0.5V D[3:0] LEGDET3 0000 Returns the legacy detection results for port 3. 0000: No legacy detection 0001: Valid (5µF < PD input capacitor < 100µF) 0010: Unable to discharge the PD input capacitance to 2.4V 0100: The first measurement exceeds the 18.5V maximum voltage 0101: The second measurement exceeds the 18.5V maximum voltage 0110: The difference between the measured voltages is below 0.5V

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 47 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. ADC RESULT REGISTERS PORT_1_CURRENT (40h and 41h) Read-only Bits Bit Name Default Value Description (40h) D[0] PORT_1_ CURRENT_DATA 0 Returns the lower bit of port 1’s ADC current result. 41h D[7:0] 0000 0000 Returns the higher bits of port 1’s ADC current result. The output current can be calculated with the following equation: Output current = 2.4mA x COUNT - 10mA Where COUNT is the unsigned binary integer of the ADC result. PORT_1_VOLTAGE (42h and 43h) Read-only Bits Bit Name Default Value Description 42h D[0] OUT1_ PIN_ VOLTAGE _DATA 0 Returns the lower bit of port 1’s ADC voltage result. 43h D[7:0] 0000 0000 Returns the higher bits of port 1’s ADC voltage result. The sum of these two registers is the OUT1 pin voltage. The port output voltage can be calculated with the following equation: Output voltage = 0.15V x (VIN COUNT - OUT1 COUNT) Where COUNT is the unsigned binary integer of the ADC result. PORT_2_CURRENT (44h and 45h) Read-only Bits Bit Name Default Value Description 44h D[0] PORT_2_ CURRENT_ DATA 0 Returns the lower bit of port 2’s ADC current result. 45h D[7:0] 0000 0000 Returns the higher bits of port 2’s ADC current result. The output current can be calculated with the following equation: Output current = 2.4mA x COUNT - 10mA Where COUNT is the unsigned binary integer of the ADC result. PORT_2_VOLTAGE (46h and 47h) Read-only Bits Bit Name Default Value Description 46h D[0] OUT2_PIN_ VOLTAGE_ DATA 0 Returns the lower bit of port 2’s ADC voltage result. 47h D[7:0] 0000 0000 Returns the higher bits of port 2’s ADC voltage result. The sum of these two registers is the OUT2 pin voltage. The port output voltage can be calculated with the following equation: Output voltage = 0.15V x (VIN COUNT - OUT2 COUNT) Where COUNT is the unsigned binary integer of the ADC result.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 48 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. PORT_3_CURRENT (48h and 49h) Read-only Bits Bit Name Default Value Description 48h D[0] PORT_3_ CURRENT_ DATA 0 Returns the lower bit of port 3’s ADC current result. 49h D[7:0] 0000 0000 Returns the higher bits of port 3’s ADC current result. The output current can be calculated with the following equation: Output current = 2.4mA x COUNT - 10mA Where COUNT is the unsigned binary integer of the ADC result. PORT_3_VOLTAGE (4Ah and 4Bh) Read-only Bits Bit Name Default Value Description 4Ah D[0] OUT3_PIN_ VOLTAGE_ DATA 0 Returns the lower bit of port 3’s ADC voltage result. 4Bh D[7:0] 0000 0000 Returns the higher bits of port 3’s ADC voltage result. The sum of these two registers is the OUT3 pin voltage. The port output voltage can be calculated with the following equation: Output voltage = 0.15V x (VIN COUNT - OUT3 COUNT) Where COUNT is the unsigned binary integer of the ADC result. PORT_4_CURRENT (4Ch and 4Dh) Read-only Bits Bit Name Default Value Description 4Ch D[0] PORT_4_ CURRENT_ DATA 0 Returns the lower bit of port 4’s ADC current result. 4Dh D[7:0] 0000 0000 Returns the higher bits of port 4’s ADC current result. The output current can be calculated with the following equation: Output current = 2.4mA x COUNT - 10mA Where COUNT is the unsigned binary integer of the ADC result. PORT_4_VOLTAGE (4Eh and 4Fh) Read-only Bits Bit Name Default Value Description 4Eh D[0] OUT4_PIN_ VOLTAGE_ DATA 0 Returns the lower bit of port 4’s ADC voltage result. 4Fh D[7:0] 0000 0000 Returns the higher bits of port 4’s ADC voltage result. The sum of these two registers is the OUT4 pin voltage. The port output voltage can be calculated with the following equation: Output voltage = 0.15V x (VIN COUNT - OUT4 COUNT) Where COUNT is the unsigned binary integer of the ADC result.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 49 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. INPUT_VOLTAGE (50h and 51h) Read-only Bits Bit Name Default Value Description 50h D[0] INPUT_ VOLTAGE_ DATA 0 Returns the lower bit of the ADC VIN result. 51h D[7:0] 0000 0000 Returns the higher bits of the ADC VIN result. VIN can be calculated with the following equation: VIN = 0.15V x COUNT Where COUNT is the unsigned binary integer of the ADC result. JUNCTION_TEMPERATURE (52h and 53h) Read-only Bits Bit Name Default Value Description 52h D[0] JUNCTION_ TEMP ERATURE_ DATA 0 Returns the lower bit of the ADC die temperature result. 53h D[7:0] 0000 0000 Returns the higher bits of the ADC die temperature result. The junction temperature can be calculated with the following equation: Junction temperature = 0.4°C x COUNT - 40°C Where COUNT is the unsigned binary integer of the ADC result. PMAX_POWER_SETTING (54h and 55h) Read/write Bits Bit Name Default Value Description 54h D[0] PMAX_ SETTING_ DATA 0 Returns the lower bit of the ADC PMAX setting data result. 55h D[7:0] 0000 0000 Returns the higher bits of the ADC PMAX setting data result. The maximum power load can be calculated with the following equation: Max power load = 0.4W x COUNT Where COUNT is the unsigned binary integer of the ADC result . The PMAX power result is latched when the MP3924 starts up or is reset . The PMAX power rating is in a decimal value as a multiple 0.4W. DIE_ID (60h) Read-only Bits Bit Name Default Value Description D[7:6] FAB 00 Returns the fab location. D[5:4] MAJOR_REV 00 Returns the major revision. D[3:2] MINOR_REV 00 Returns the minor revision. D[1:0] VENDOR_ID 00 Returns the vendor ID.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 50 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

APPLICATION INFORMATION

Selecting the Input Capacitor The supply voltage (VIN) must be between 44V and 57V. The input capacitor (C IN) maintains the DC input voltage. The system input capacitor(s) must be rated for 100 V, and they can be aluminum electrolytic capacitors. Place a 0.1μF decoupling ceramic capacitor close to VIN and PGND to bypass VIN. Selecting the VCC Capacitor The MP 3924 integrates the V CC (about 3. 3V) to power the internal control circuit. The internal regulator requires a minimum 1μF ceramic bypass capacitor to be connected from VCC to DGND. The VCC current limit is typically 17mA. Do not connect a heavy external load to VCC, as the VCC voltage may drop. This can result in a high VIN to VCC LDO power loss. Selecting the Output Capacitor for Each Port An output capacitor must be placed from VIN to OUTx for the MP3924’s output. It is recommended to us e a 0.1µF, 100V ceramic capacitor. Output Transient Voltage Suppression (TVS) The port transient voltage suppression ( TVS) should be rated for the expected port surge environment. D TVS should have a minimum reverse standoff voltage of 58 V, as well as a maximum clamping voltage of 95 V at the expected peak surge current. Selecting the Output MOSFET for Each Port The por t’s MOSFET can be a small, inexpensive device with average performance characteristics as long as it meets the following conditions:  The voltage rating should be 100V minimum for high-voltage surge environments.  RDS(ON) should be below 150mΩ for power dissipation.  The power dissipation for the power MOSFET (Q1) when RDS(ON) = 100mΩ at the maximum ICUT is about 85mW.  The gate charge (QG) when VGATE = 10V should be below 50nC to satisfy faster response times under overload conditions.  The gate voltage should be 20V to establish a sufficient margin while GATEx is about 10V. The FDMC3612 is recommended for most applications. Selecting the SENSE Resistor for Each Port The load current in each PSE port is sensed as the voltage across a current -sense resistor (RSENSE, which is about 250mΩ). For more accurate current sensing, a Kelvin sense at the low end of the current -sense resistor is provided through pins SGND1 for ports 1 and 2, and SGND2 for ports 3 and 4 (see Figure 21). MP3924 VIN VIN = 54V CIN OUTn Port 1~4 Output GATEn SENSEn SGNDx PGND COUT RSENSE QMAIN DTVS Figure 21: Typical Output Components Maximum Power Supply Setting Connect one resistor from the PMAX pin to DGND to set the total power capability for all four output ports. The maximum output power is equal to the PMAX resist or value (in kΩ). For example, if 120W power is required for all for output, connect a 120kΩ resistor from PMAX to DGND. Selecting the Digital I/O Pull-Up Resistors EN EN is the e nable input pin that can turn all internal circuits and ports on and off (except for the VCC regulator ). Connect EN to VCC through a 100kΩ resistor to automatically turn on the MP3924. AUTO The AUTO pin sets a utomatic mode. AUTO is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ resistor can also be added). Float th e AUTO pin for auto matic mode. Connect the AUTO pin to DGND for shutdown mode.

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 51 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. MID The MID pin sets th e midspan mode. MID is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ resistor can also be added). Float the MID pin for midspan mode, and wait 2.8s befo re reinitiating detection . Connect MID to DGND to disable midspan mode. A0~A3 The A0~A3 pins set the MP3924’s address. These pins are internally pulled up to VCC through a 50kΩ resistor ( an external 10k Ω resistor can also be added). Connect these pins to VCC or DGND to set the low er 4 bits of the address (Address = 010 A3 A2 A1 A0). CLS5 The CLS5 enables Class 5. CLS5 is i nternally pulled down to DGND through a 50kΩ resistor. Leave CLS5 disconnected to disable the classification for Class 5 devices. (This is a high power level with the same classification as IEEE802.3 at . This is not standard class leve l that is compatible with IEEE802.3 ). Connect CLS5 to VCC to enable the classification of Class 5 devices. SCL and SDAI SCL and SDAI are the I2C input pins . The y must be connected to VCC through an external pull-up resistor (typically 4.7k Ω). If the I 2C interface is not used, c onnect SCL to VCC and connect SDAI to DGND. SDAO SDAO is open -drain output pin a s well as the I2C serial data output pin . Connect SDAO to VCC through an ext ernal pull -up resistor (typically 4.7k Ω). Connect SDAO to SDAI for non-isolated applications. If the I 2C interface is not used, connect SDAO to DGND. INT1 and INT2 INT1 and INT2 are open -drain outputs that act as the interrupt request pin s for all interrupt source events. These pins are set low when the interrupt register is set and the interrupt function is enabled. Connect these pins to VCC through an external pull -up resistor (typically 4.7k Ω). If the interrupt function is not used, connect these pins to DGND. Over-Current Protection (OCP) and Overload Protection (OLP) Inrush Current Limit The MP3924 provides a 425mA inrush current limit for inrush protection. When the external MOSFET begins to operate, inrush current protection is enabled. This protection allows the input capacitance of the PD to charge to the full VIN on the power interface . It also ensures the pass FET remains within its safe operating range. If IINRUSCH exceeds ICUT during the inrush , the ICUT timer (tICUT) begins working. If tICUT times out, the output turns off. ICUT Following the end of start-up, a two current-limit protection scheme is applied to the ports. The first level is the ICUT current limit , which includes an ICUT timer (tICUT). If tICUT times out because the ICUT current threshold is exceeded, the port shuts down . The ICUT current limit threshold is configured by the ICUTx bits (see Table 2). Table 2: ICUT Threshold ICUT Register Value ICUT (mA) 000 375 001 110 010 188 011 375 100 650 101 920 110 500 111 625 In auto matic mode, the bits are set to 000 for Class 0~3 results, set to 100 for Class 4 result, and set to 101 for Class 5 result automatically based on classification result. ILIM The second level of current-limit protection is the ILIM current limit. The ILIM current limit is a hard limit. The GATE pin regulates the load at the current limit level, and one additional timer (tILIM) is enabled to record the current limit event. When tILIM completes, the port shuts down. The ILIM cur rent limit threshold can be configured via the ILIMx threshold register (see Table 3 on page 52).

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 53 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUIT FDMC3612 Q1A FDMC3612 Q1B FDMC3612 Q1C FDMC3612 Q1D 0.25Ω R1A 0.25Ω R1B 0.25Ω R1C 0.25Ω R1D SMBJ58A D1B 0.1µF C2A 0.1µF C2B 0.1µF C2C 0.1µF C2D VIN PGND PGND SCL9 GATE2 30 A114 OUT3 28 AUTO6 INT23 VIN 22 INT18 CLS55 OUT1 2 SGND1 4 SDAO10 A013 EN12 OUT2 31 SENSE2 29 GATE3 27 A316 DGND17 VCC20 PMAX21 SENSE4 23 OUT4 25 MID7 GATE1 1 SGND2 18 GATE4 24 PGND19 SENSE1 32 A215 SENSE3 26SDAI11 MP3924 1µF PGND PGND PGND 100kΩ 120kΩ DGND DGND GND SMBJ58A D1A SMBJ58A D1C SMBJ58A D1D 0.1µF C1B 220µF C1A Port 1 Output Port 2 Output Port 3 Output Port 4 Output Figure 23: Typical Application Circuit without I2C Control

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 54 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN-32 (5mmx5mm) PACKAGE OUTLINE DRAWING FOR 32L QFN (5X5mm) MF-PO-D-0052 revision 1.0 SIDE VIEW BOTTOM VIEW PIN 1 ID MARKING TOP VIEW PIN 1 ID INDEX AREA RECOMMENDED LAND PATTERN PIN 1 ID 0.30x45°TYP. NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) DRAWING CONFIRMS TO JEDEC MO-220, VARIATION WHHE-1. 5) DRAWING IS NOT TO SCALE. 0.10x45°

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER MP3924 Rev. 1.0 MonolithicPower.com 55 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. CARRIER INFORMATION Part Number Package (5mmx5mm) 5000 N/A 13in 12mm 8mm

MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER Notice: The information in this document is subject to change without notice. Users should warrant and guarantee that third - party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP3924 Rev. 1.0 MonolithicPower.com 56 7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved.

REVISION HISTORY

Revision # Revision Date Description Pages Updated 1.0 07/16/2021 Initial Release -