MP3274 EXAR | Alldatasheet
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Technical content
Rev. 4.00 Fault Protected 32 Channel, 12-Bit Data Acquisition Subsystem
FEATURES
- Complete 32-Channel 12-Bit A/D Converter with Sample & Hold, Reference, Clock and 3-State Outputs
- Fast Conversion, less than 15µS
- Microprocessor Bus Interface
- Parallel or Serial Data Output Modes
- 65 ns Bus Access Time
- Remote Analog Ground Sensing
- Overvoltage Protected Input (50 V over the Supply Voltages)
- Precision Reference for Long Term Stability and Low Gain T.C.
- Guaranteed Linearity Over Temperature
- Guaranteed Performance at +12/–5 V, ±12 & ±15 V
- Low Power (3 mW per Channel Typical)
- 16 Channel Version: MP3276 & MP3275 GENERAL DESCRIPTION The MP3274 is a complete 32-channel, 12-bit Data Acquisi- tion Subsystem with 3-state output buffers for direct interfacing to 16-bit microprocessor buses. Implemented using an ad- vanced BiCMOS process, the converter combines a 32-channel passive overvoltage protected multiplexer instrumentation amp, a sample & hold, a SAR, a 12-bit decoded D/A, a comparator, a precision reference and the control logic to achieve an accurate, repeated conversion in less than 15µs, and a mux/instrumenta- tion amp settling period of less than 10µs. A unique input design provides input overvoltage protection to 50 V over the supply voltages. Therefore, an overvoltage condition can exist on unselected channels without disrupting the measured channel or operation of the MP3274! The internal
4 V reference has sufficient output current to provide other sys-
tem reference needs. Precision thin film scaling and offset resis- tors are laser trimmed to provide for less than 2 LSB INL for + V inputs on all channels. In addition, the MP3274 will output either full scale (0111 ....) for overrange and – full scale (1000....) for underrange condi- tions. This greatly simplifies microprocessor software develop- ment. SIMPLIFIED BLOCK DIAGRAM Comp SAR 4 V REF 5 32 Ch. MUX AB0-4 (5 pins) AIN0-31 (32 pins) REF OUT Control Logic GND REF. DGND V EE VDAC Latch/ Shift Register 3-State Drivers DB0-DB11 REF IN /2 VDD VCC CLK WR RD CS PXS ADEN STL STS AGND VREF AGND 2 AGND 3 AGND REF IN
Rev. 4.00
ORDERING INFORMATION
Range Part No. DNL (LSB) PGA –40 to +85°C 2MP3274AG INL (LSB) PGA –55 to +125°C MP3274SG* 2 2 PLCC –40 to +85°C 2MP3274AP 2 *Contact factory for non-compliant military processing PIN CONFIGURATIONS
68 Pin PGA
68 Pin PLCC
Rev. 4.00 PIN OUT DEFINITIONS 61 1 V EE Negative Analog Supply 62 2 A IN24 Analog Input 24 63 3 A IN25 Analog Input 25 64 4 A IN26 Analog Input 26 65 5 A IN27 Analog Input 27 66 6 A IN28 Analog Input 28 67 7 A IN29 Analog Input 29 68 8 A IN30 Analog Input 30
19 A IN31 Analog Input 31
2 10 GND Ref. Input Ground Reference 3 11 AGND ADC Analog Ground 4 12 Ref In Reference Input 5 13 Ref Out Reference Output 6 14 AGND3 Reference Analog Ground 7 15 DGND Digital Ground 8 16 DB0/SDC Data Output Bit 0/Serial Data Clock 9 17 N/C No Connection 10 18 DB1 Data Output Bit 1 11 19 DB2 Data Output Bit 2 12 20 DB3 Data Output Bit 3 13 21 DB4 Data Output Bit 4 14 22 DB5 Data Output Bit 5 15 23 DB6 Data Output Bit 6 16 24 DB7 Data Output Bit 7 17 25 DB8 Data Output Bit 8 18 26 DB9 Data Output Bit 9 19 27 DB10 Data Output Bit 10 20 28 DB11/SDO Data Output Bit 11/Serial Data Out 21 29 STS Conversion Status 22 30 STL Mux Settling Status 23 31 PXS Parallel/XSerial 24 32 RD Read Enable 25 33 CS Chip Select 26 34 WR Write Enable NAME DESCRIPTION 27 35 ADEN Address Enable 28 36 AB4 Channel Address 4 29 37 AB3 Channel Address 3 30 38 AB2 Channel Address 2 31 39 AB1 Channel Address 1 32 40 AB0 Channel Address 0 33 41 V DD Positive Digital Supply 34 42 V CC Positive Analog Supply 35 43 A IN0 Analog Input 0 36 44 A IN1 Analog Input 1 37 45 A IN2 Analog Input 2 38 46 A IN3 Analog Input 3 39 47 A IN4 Analog Input 4 40 48 A IN5 Analog Input 5 41 49 A IN6 Analog Input 6 42 50 A IN7 Analog Input 7 43 51 N/C No Connection 44 52 A IN8 Analog Input 8 45 53 A IN9 Analog Input 9 46 54 A IN10 Analog Input 10 47 55 A IN11 Analog Input 11 48 56 A IN12 Analog Input 12 49 57 A IN13 Analog Input 13 50 58 A IN14 Analog Input 14 51 59 A IN15 Analog Input 15 52 60 AGND2 Analog Ground Mux Return 53 61 A IN16 Analog Input 16 54 62 A IN17 Analog Input 17 55 63 A IN18 Analog Input 18 56 64 A IN19 Analog Input 19 57 65 A IN20 Analog Input 20 58 66 A IN21 Analog Input 21 59 67 A IN22 Analog Input 22 60 68 A IN23 Analog Input 23
DESCRIPTION
PIN NO. PGA PADS NAME PLCC PIN NO. PGA PADS
Rev. 4.00 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: VDD = 5 V, VCC = 15 V, VEE = –15 V, GNDRef = 0 V, TA = 25°C, VREF IN = Ref Out 25°C Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments Resolution (All Grades) N 12 12 Bits KEY FEATURES Resolution 12 12 Bits Conversion Time, Per Channel t CONVR 15 15 µs ACCURACY (A, S Grade)1 Differential Non-Linearity DNL 3/4 2 2 LSB Integral Non-Linearity INL 1 2 2 LSB Best Fit Line (Max INL – Min INL)/2 Zero Code Error EZS 2 5 10 LSB fff to 000 [hex] transition Full Scale Error EFS 0.1 0.35 0.5 % V REF IN = 4.000 V POWER SUPPLY REJECTION Max change in Full Scale Calibration VCC = 15 V 1.5 V or 12 V
0.6 V 1 1 LSB
VDD = 5 V 0.25 V 2 2.5 LSB VEE = –15 V 1.5 V or –12 V 0.6 V or 1 1 LSB –5 V 0.25 V REFERENCE VOLTAGES Ref. Voltage Input Ref In 3.6 4.4 V R IN 5KΩ ; VDD = 5 V Ref. Voltage Output Ref Out 3.975 4.025 Ref. Source Current 3.0 4.0 3.0 mA Ref. Sink Current 20 µA ANALOG INPUT Input Voltage Range5 VIN –10 10 –10 10 V Ground Reference GND Ref. CM Range –3 3 –3 3 V CM RR TBD LSB/V Input Resistance R IN 100 130 100 k Ω Input Capacitance C IN 5p F Aperture Delay t AP 180 ns From WR low to high after STL high to low Channel-to-Channel Isolation2 –80 –70 dB DC DIGITAL INPUTS CS , WR, RD AB0-AB4, ADEN Logical “1” Voltage V IH 2.4 5.5 2.4 5.5 V Logical “0” Voltage V IL –0.5 0.8 –0.5 0.8 V Leakage Currents6 IIN –5 5 –10 10 µAV IN=GND to VDD Input Capacitance2 5p F Tmin to Tmax
Rev. 4.00 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Description Symbol Min Typ Max Min Max Units Conditions DIGITAL OUTPUTS C OUT =15 pF (Data Format 2’s Complement) DB0/SDC–DB11/SDO, STS, STL Logical “1” Voltage V OH 4.0 2.4 V I SOURCE = 0.5 mA Logical “0” Voltage V OL 0.4 0.4 V I SINK = 1.6 mA Tristate Leakage I OZ –5 5 –5 5 µAV OUT =GND to VDD POWER SUPPLIES Operating Range Operating Current IDD 27 7 m A ICC 58 8 m A IEE 1.5 3 3 mA Power Dissipation 110 200 200 mW 25°C Tmin to Tmax NOTES 1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage 2 Guaranteed. Not tested. 3 Specified values guarantee functionality. Refer to other parameters for accuracy. 4 Input bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 All channel input pins and ground reference pin have protection which becomes active above 60 V. 6 All digital inputs have diodes to VDD and AGND. Input DC currents will not exceed specified limits for any input voltage between GND and VDD . Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Digital Inputs/Outputs Analog Inputs (AIN0 – AIN31, GND REF) Momentary short to VCC Package Power Dissipation Rating to 75°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All logic inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs.
is available in either parallel or serial format. croprocessor control, where changes can be made dynamically. functions described in Table 1. Table 1. Logic Truth Table for PXS = 1 (Parallel Mode)
1 X X X –– 0 0 No operation
0 X 0 X ADC 0 0 Data from previous conversion on data bus
0 X 0 X Last ADC 1 0 Data from last conversion on data bus
tem designer with useful insight into the operation of the device. Figure 1. shows a complete timing diagram for the MP3274 version the specified set-up times will be longer. possible conditions that will affect conversion timing.
- ADEN = 1. At the falling edge of WR, the input channel is
user better control of the sampling time.
- ADEN = 0. At the falling edge of WR the data present at the
- If RD is held high during a conversion the outputs would re-
or CS should not change during a conversion. should be avoided when possible. Table 2. ADC Write Timing
Table 4. Serial Data Output Mode Timing (See Figure 6.) STS low to SDO (DB11) Valid, t 20 50 50 ns max Load Ckt 4 of Figure 3. Table 5. Logic Truth Table – Serial Data Output Mode
1 X X X X –– 0 0 X No Operation
00 X X X MSB (DB11) 0 0 1 MSB data available at DB11/SDO
00 X ↑ X Hi-Z 0 0 X Data outputs/SDC input disabled
0 X 1 X X Hi-Z 0 1 X Data outputs/RD
0 X 0 0 Hi-Z 0 ↑ 1 STL, MUX select disabled when
Table 6. Key Output Codes vs. Input Voltage (2’s Complement Code)
0 V +1/2 LSB
0 V –1/2 LSB
Rev. 4.00
APPLICATION INFORMATION
The MP3274 is a complete A/D converter system, with its own built-in reference and clock. It may be used by itself (“stand- alone” operation), or it may be interfaced with a microprocessor which can control both conversion and formatting of output. Successful application of the MP3274 requires careful atten- tion to four main areas: 1) Physical layout. 2) Connection/Trimming according to mode of operation. 3) Conditioning of input signals. 4) Control and Timing considerations. Physical Layout The 12-bit accuracy of the MP3274 represents a dynamic range of 72dB. In order that this be preserved, thorough precau- tions must be taken to avoid any interfering signals, whether conducted or radiated.
- Avoid placing the chip and its analog signals near logic traces. In general, using a double sided printed circuit card with a good ground plane on the component side is recommended. Routing analog signals between ground traces will help isolate digital control logic. If these lines cross, do so at right angles. The GND Ref. is the positive terminal of the MUX/Instrumentation amplifier and will provide common mode noise rejection. It should be close to and shielded together with the channel inputs in order to take advantage of this feature.
- Power supplies should be quiet and well regulated. Grounds should be tied together at the package and back to the system ground with a single path. Bypass the supplies at the device with a 0.01 to 0.1µF ceramic cap and a 10-47 µF tantalum type, in parallel. “Stand-Alone” Operation The MP3274 can be used in “stand-alone” operation, which is useful in systems not requiring full computer bus interface capa- bility. This operation is available for either parallel or serial mode. For this operation, CS = 0, ADEN = 1, and conversion is con- trolled by WR. The 3-state buffers are enabled when RD goes low. There are two possible conditions that the 3-state buffers could be in during a conversion. If RD goes low prior to WR, the output buffers are enabled and the data from the previous con- version is available at the outputs during STL = 1. At the end of the present conversion which is initiated at the rising edge of WR , STS returns low and the new conversion result is placed on the output data buffers. If WR goes low prior to RD the data buffers remain in a high impedance state and conversion is initiated at the rising edge of WR . Upon the end of the conversion the STS returns low and the conversion result is placed on the output data buffers. Ground Reference The ground reference pin can be used for remote ground sensing of a common mode input signal with a maximum 6 V p-p around AGND. This common input can also be used to dither each input’s “zero”. By averaging multiple conversions digitally, higher reso- lution for each input conversion can be obtained. Patterns for this dither can be a ramp, a stair step, or white noise. COMP S A R VDAC 130k 26k 130k 26k 1 of 32 GND Ref.
Figure 7. Equivalent Input Circuit from the same date code will further minimize this difference.
Rev. 4.00 A .165 .180 4.19 4.57 A1 .095 .118 2.51 3.00 A2 0.146 0.154 3.71 3.91 B 0.013 0.021 0.330 0.553 C 0.097 0.0103 0.246 0.261 D .985 .995 25.02 25.27 D 1 (1) .950 .954 24.13 24.23 D 2 .890 .930 22.60 23.62 D 3 0.800 Ref 20.32 Ref. e1 0.050 BSC 1.27 BSC
68 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC) P68 SYMBOL MIN MAX MIN MAX INCHES D D 1 D D 1 D 3 Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. D 2B A A 1 C Seating PlaneA 2 MILLIMETERS
Rev. 4.00 A 0.079 0.095 2.00 2.41 b 0.016 0.020 0.406 0.508 D 1.086 1.110 27.6 28.2 D 1 0.788 0.812 20.0 20.6 e 0.100 typ. 2.54 typ. L1 0.170 0.190 4.32 4.83 Q 0.050 typ. 1.27 typ.
68 LEAD PIN GRID ARRAY
(PGA) G68 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS D D É É É É É É É É É É D 1 e D 1 L K J H G F E D 87654321 e b Q Seating Plane Pin 1 1B 2 2B 1 3C 2 4C 1 5D 2 6D 1 7E 2 8E 1 9F 2 10 F1 11 G2 12 G1 13 H2 14 H1 15 J2 16 J1 17 K1 CONNECTION TABLE 18 K2 19 L2 20 K3 21 L3 22 K4 23 L4 24 K5 25 L5 26 K6 27 L6 28 K7 29 L7 30 K8 31 L8 32 K9 33 L9
34 L10
35 K10
36 K11
37 J10
38 J11
39 H10
40 H11
41 G10
42 G11
43 F10
44 F11
45 E10
46 E11
47 D10
48 D11
49 C10
50 C11
51 B11
Note: The letters A-H and numbers 1-8 are the coordinates of a grid. For example, pin 1 is at the intersections of the “B” vertical line and the “2” horizontal line. A
52 B10
53 A10
C B A 91 0 1 1 Index Mark IP IP = Index Pin, not connected
Rev. 4.00 Notes
Rev. 4.00 Notes
Rev. 4.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.