MP2331H MPS | Alldatasheet
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MP2331H 24V, 2A, 1.2MHz, Synchronous Buck Converter MP2331H Rev. 1.0 www.MonolithicPower.com 1 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
DESCRIPTION
The MP2331H is a fully integrated, high- frequency, synchronous , rectified, step -down, switch-mode converter with internal power MOSFETs. The MP2331H offers a very compact solution that achieves 2A of continuous output current with excellent load and line regulation over a wide input range. The MP2331H uses synchronous mode operation for higher efficiency over the output current load range. Constant-on-time (COT) control operation provides very fast transient response, easy loop design, and very tight output regulation. Full protection features include short-circuit protection (SCP), over-current protection (OCP), under-voltage protection (UVP), and thermal shutdown. The MP2331H requires a minimal number of readily available, standard, external components and is available in a space -saving SOT583 package.
FEATURES
Wide 4.2V to 24V Operating Input Range 110mΩ/45mΩ Low RDS(ON) Internal Power MOSFETs 200µA Low IQ High-Efficiency Synchronous Mode Operation Fast Load Transient Response 1.2MHz Switching Frequency TON Extension Forced PWM Operation Programmable Soft-Start Time Power Good (PG) Indication Over-Current Protection (OCP) and Hiccup Pre-Bias Start-Up Thermal Shutdown Available in a SOT583 (1.6mmx2.1mm) Package
APPLICATIONS
Game Consoles Digital Set-Top Boxes Flat-Panel Television and Monitors General Purposes All MPS parts are lead -free, halogen -free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION PG 3.3V/2A 22µF 44 µF MP2331H 2.2µH PG SSC4 6.8nF 40.2 kΩ 13kΩ R2R3 20kΩ 1µF 20Ω19V Efficiency VOUT = 3.3V, L = 2.2μH, DCR = 11.4mΩ
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 2 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking MP2331HGTL SOT583 See Below * For Tape & Reel, add suffix –Z (e.g.: MP2331HGTL–Z). TOP MARKING BCL: Product code of MP2331HGTL Y: Year code LLL: Lot number PACKAGE REFERENCE TOP VIEW 4 5 6IN SW GND BST EN SS 2 7 8PG FB SOT583 (1.6mmx2.1mm)
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 3 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. PIN FUNCTIONS Package Pin # Name Description 1 PG Power good output. The output of PG is an open drain. Decouple PG with a 1nF capacitor. 2 IN Supply voltage. The MP2331H operates from a 4.2V to 24V input rail. A capacitor (C1) is required to decouple the input rail. Connect IN using a wide PCB trace. 3 SW Switch output. Connect SW using a wide PCB trace. 4 GND System ground. GND is the reference ground of the regulated output voltage and requires extra care during the PCB layout. Connect GND with copper traces and vias. 5 BST Bootstrap. Connect a 1µF BST capacitor and a resistor between SW and BS T to form a floating supply across the high-side switch driver. 6 EN Enable. Drive EN high to enable the MP2331H. For automatic start -up, connect EN to V IN through a 604kΩ pull-up resistor. 7 SS Soft start. Connect an external capacitor to SS to program the soft -start time for the switch-mode regulator. 8 FB Feedback. Connect FB to the tap of an external resistor divider from the output to GND to set the output voltage. ABSOLUTE MAXIMUM RATINGS (1) to 26V (28V for <10ns) Continuous power dissipation (TA = +25°C) (3)(5) Recommended Operating Conditions (4) or 13V max Operating junction temp. (TJ) ... -40°C to +125°C Thermal Resistance SOT583 (1.6mmx2.1mm) θJA θJC NOTES: 1) Exceeding these ratings may damage the device. 2) For details on EN’s ABS max rating, please refer to the Enable Control section on page 12. 3) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation on EV2331H Board at any ambient temperature is calculated by PD (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown cir cuitry protects the device from permanent damage. 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on EV2331H -TL-00A, 2-layer PCB, 64mmx48mm. 6) The value of θJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51 -7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 4 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C (7), typical value is tested at TJ = +25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Supply current (shutdown) IIN VEN = 0V 10 μA Supply current (quiescent) IQ VEN = 2V, VFB = 0.85V 200 μA HS switch on resistance HSRDS(ON) VBST - SW = 3.3V 110 mΩ LS switch on resistance LSRDS(ON) 45 mΩ Switch leakage SWLKG VEN = 0V 1 μA Low-side switching current limit OCP ILIMIT_LS_OC 2.5 3.5 A Negative current limit (8) INC VOUT = 3.3V, L = 1.5μH -1.3 A Oscillator frequency fSW VFB = 0.75V 960 1200 1440 kHz Minimum on time (8) τON_MIN 45 ns Minimum off time (8) τOFF_MIN 190 ns Feedback voltage VREF 789 805 821 mV Feedback current IFB 10 80 nA Hiccup duty cycle (8) 25 % EN rising threshold VEN_RISING 1.16 1.23 1.29 V EN hysteresis VEN_HYS 100 mV EN input current IEN VEN = 2V 2 µA VEN = 0V 0 VIN under-voltage lockout threshold rising INUVVth 4 V VIN under-voltage lockout threshold hysteresis INUVHYS 400 mV Power good rising threshold UV PGUV_R 87 92 97 %VREF Power good falling threshold UV PGUV_F 82 87 92 %VREF Power good rising threshold OV PGOV_R 115 120 125 %VREF Power good falling threshold OV PGOV_F 102 107 112 %VREF Power good rising delay 50 μs Power good falling delay 35 μs Power good sink current capability VPG Sink 1mA 0.13 0.4 V Power good leakage current IPG_LEK 3 μA Soft-start current Iss 5.3 7.3 9.3 μA Thermal shutdown (8) 150 °C Thermal hysteresis (8) 20 °C NOTES: 7) Not tested in production. Guaranteed by over-temperature correlation. 8) Guaranteed by design and engineering sample characterization.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 5 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 19V, VOUT = 3.3V, L = 2.2µH, FSW = 1.2MHz, unless otherwise noted. Efficiency VOUT = 5V, L = 3.3μH, DCR = 17.2mΩ Efficiency VOUT = 3.3V, L = 2.2μH, DCR = 11.4mΩ 100 0 0.5 1 1.5 2 EFFICIENCY (% ) OUTPUT CURRENT (A) Vin=6.5V Vin=12V Vin=19V Vin=24V 100 0 0.5 1 1.5 2 EFFICIENCY (% ) OUTPUT CURRENT (A) Vin=5V Vin=12V Vin=19V Vin=24V Efficiency VOUT = 2.5V, L = 2.2μH, DCR = 11.4mΩ Efficiency VOUT = 1.8V, L = 1.5μH, DCR = 4.3mΩ 100 0 0.5 1 1.5 2 EFFICIENCY (% ) OUTPUT CURRENT (A) Vin=5V Vin=12V Vin=19V Vin=24V 100 0 0.5 1 1.5 2 EFFICIENCY (% ) OUTPUT CURRENT (A) Vin=5V Vin=12V Vin=19V Vin=24V Efficiency VOUT = 1.5V, L = 1.5μH, DCR = 4.3mΩ Efficiency VOUT = 1.2V, L = 1.2μH, DCR = 6.6mΩ 100 0 0.5 1 1.5 2 EFFICIENCY (% ) OUTPUT CURRENT (A) Vin=5V Vin=12V Vin=19V Vin=24V 100 0 0.5 1 1.5 2 EFFICIENCY (% ) OUTPUT CURRENT (A) Vin=5V Vin=12V Vin=19V Vin=24V
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 6 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 19V, VOUT = 3.3V, L = 2.2µH, FSW = 1.2MHz, unless otherwise noted. Efficiency VOUT = 1V, L = 1μH, DCR = 4.6mΩ Load Regulation IOUT = 0.1 - 2A 0 0.5 1 1.5 2 EFFICIENCY (% ) OUTPUT CURRENT (A) Vin=5V Vin=12V Vin=19V Vin=24V -0.3 -0.2 -0.1 0.1 0.2 0.3 0 0.5 1 1.5 2 LOAD REGULATION (% ) OUTPUT CURRENT (A) Vin=5V Vin=12V Vin=19V Vin=24V Line Regulation VIN = 5 - 24V Enabled Supply Current vs. Input Voltage -0.3 -0.2 -0.1 0.1 0.2 0.3 5 10 15 20 25 LINE REGULATION (% ) INPUT VOLTAGE (V) Io=0A Io=1A Io=2A 150 160 170 180 190 200 210 220 230 240 250 4 9 14 19 24 ENABLED SUPPLY CURRENT (μA) INPUT VOLTAGE (V) Disabled Supply Current vs. Input Voltage VIN UVLO Threshold vs. Temperature 4 9 14 19 24 DISABLED SUPPLY CURRENT (μA) INPUT VOLTAGE (V) 2.5 3.5 4.5 -40 -20 0 20 40 60 80 100 120 140 VIN UVLO THRESHOLD (V) TEMPERATURE (℃) Rising threshold Falling threshold
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 7 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 19V, VOUT = 3.3V, L = 2.2µH, FSW = 1.2MHz, unless otherwise noted. EN Threshold vs. Temperature FB Voltage vs. Temperature 0.8 0.9 1.1 1.2 1.3 1.4 1.5 1.6 -40 -20 0 20 40 60 80 100 120 140 EN THRESHOLD (V) TEMPERATURE (℃) Rising threshold Falling threshold 780 785 790 795 800 805 810 815 820 -40 -20 0 20 40 60 80 100 120 140 FB VOLTAGE (mV) TEMPERATURE (℃) Case Temperature Rise vs. Output Current VIN = 12V 0.5 1 1.5 2 CASE TEMPERATURE RISE (℃) OUTPUT CURRENT (A)
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 8 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 19V, VOUT = 3.3V, L = 2.2µH, FSW = 1.2MHz, unless otherwise noted. Input/Output Ripple IOUT = 0A Input/Output Ripple IOUT = 2A CH1: VOUT/AC 10mV/div. CH2: VIN/AC 100mV/div. CH3: VSW 10V/div. CH4: IL 1A/div. CH1: VOUT/AC 10mV/div. CH2: VIN/AC 500mV/div. CH3: VSW 10V/div. CH4: IL 1A/div. 500ns/div. 500ns/div. Start-Up through Input Voltage IOUT = 0A Start-Up through Input Voltage IOUT = 2A CH1: VOUT 2V/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 2A/div. CH1: VOUT 2V/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 2A/div. 1ms/div. 1ms/div. Shutdown through Input Voltage IOUT = 0A Shutdown through Input Voltage IOUT = 2A CH1: VOUT 2V/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 2A/div. CH1: VOUT 2V/div. CH2: VIN 10V/div. CH3: VSW 10V/div. CH4: IL 2A/div. 20ms/div. 1ms/div.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 9 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 19V, VOUT = 3.3V, L = 2.2µH, FSW = 1.2MHz, unless otherwise noted. Start-Up through EN IOUT = 0A Start-Up through EN IOUT = 2A CH1: VOUT 2V/div. CH2: VEN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH2: VEN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. 1ms/div. 1ms/div. Shutdown through EN IOUT = 0A Shutdown through EN IOUT = 2A CH1: VOUT 2V/div. CH2: VEN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH2: VEN 5V/div. CH3: VSW 10V/div. CH4: IL 5A/div. 1s/div. 50µs/div. Short-Circuit Entry IOUT = 0A Short-Circuit Recovery IOUT = 0A CH1: VOUT 2V/div. CH2: VIN 20V/div. CH3: VSW 20V/div. CH4: IL 5A/div. CH1: VOUT 2V/div. CH2: VIN 20V/div. CH3: VSW 20V/div. CH4: IL 5A/div. 2ms/div. 2ms/div.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 10 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 19V, VOUT = 3.3V, L = 2.2µH, FSW = 1.2MHz, unless otherwise noted. Load Transient IOUT = 1 - 2A, slew rate is 2.5A/μs by CCDH E-load CH1: VOUT/AC 100mV/div. CH4: IOUT 1A/div. 100µs/div.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 11 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. BLOCK DIAGRAM VCC VCC Regulator HS Driver LS Driver Current Modulator On Timer SW BST VIN EN Bias & Voltage reference FB EA COMP Logic Control Main switch(NCH) Synchronous rectifier (NCH) Bootstrap Regulator Ramp GND PWM Iss Current Sense Amplifier BUF SS OVP REF PG Figure 1: Functional Block Diagram
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 12 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. OPERATION The MP2331H is a fully integra ted, synchronous, rectified, step-down, switch-mode converter. Constant -on-time (COT) control is employed to provide fast transient response and easy loop stabilization. At the beginning of each cycle, the high -side MOSFET (HS -FET) is turned on when t he FB voltage (VFB) drops below the reference voltage (VREF). The HS -FET is turned on for a fixed interval determined by the one-shot on -timer. The on -timer is determined by both the output voltage and input voltage to make the switching frequency fairly constant over the input voltage range. After the on period elapses, the HS -FET is turned off until the next period begins. By repeating this operation, the converter regulates the output voltage. The MP2331H operates in forced continuous conduction mode (CCM). The low-side MOSFET (LS-FET) is turned on when the HS- FET is in its off state to minimize conduction loss. There is a dead short between the input and GND if both the HS-FET and LS-FET are turned on at the same time. This is called a shoot-through. To prevent shoot-through, a dead time is generated internally between the HS-FET off and LS -FET on period, or the LS- FET off and HS-FET on period. Enable Control (EN) EN is a digital control pin that turns the regulator on and off . Drive EN high to turn on the regulator . Drive EN low to turn off the regulator. EN is clamped internally using a 2.8V series Zener diode (see Figure 2). Connecting the EN input through a pull -up resistor to V IN limits the EN input current below 40μA to prevent damage to the Zener diode. For example, when connecting a 604kΩ pull-up resistor to 12V VIN, IZener = (12V - 2.8V) / (604kΩ + 35kΩ) = 14µA. EN Logic EN GND 35kΩ 2.8V Figure 2: Zener Diode between EN and GND Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The MP2331H UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 4V, while its falling threshold is 3.6V. Soft Start (SS) The MP2331H employs a soft -start (SS) mechanism to ensure smooth output ramping during power up. When the MP2331H starts up, an internal current source ( typically 7.3μA) charges up the SS capacitor to generate a soft- start voltage (V SS). When V SS/2 is below V REF, VSS/2 overrides V REF. The error amplifier (EA) uses VSS/2 as the reference. The output voltage ramps up smoothly. Once VSS/2 rises above the VREF, the EA uses VREF as the reference. At this point, the soft start finishes , and the MP2331H enters steady-state operation. The SS capacitor value can be determined with Equation (1): ss ss ss REF T (ms) I (uA)C (nF) 2V (1) Over-Current Protection (OCP) and Short - Circuit Protection (SCP) The MP2331H has a valley-limit control. The inductor current is monitored during the LS-FET on state. When the sensed inductor current reaches the valley current limit, the LS limit comparator turns over, and the MP2331H enters over -current protection (OCP) mode. The HS-FET waits until the valley current limit is removed before turning on again . Meanwhile , the output voltage drops until V FB is below the under-voltage (UV) threshold. Once UV is triggered, the MP2331H enters hiccup mode to restart the part periodically. In OCP, the device attempts to recover from the over-current fault with hiccup mode. In hiccup mode, the chip disables the output power stage, discharges the soft start, and attempts to soft start again automatically. If the over -current condition still remains after the soft start ends, the device repeats this operation cycle until the over-current condition is removed and the output rises back to the regulation level. OCP is a non-latch protection.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 13 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Power Good (PG) Power good (PG) indicates whether the output voltage is in the normal range or not compared to the internal reference voltage. PG is an open-drain structure and requires an external pull-up supply . During power -up, the power good output is pulled low. This indicates to the system to remain off and keep the load on the output to a minimum. This helps reduce inrush current during start-up. When the output voltage is higher than 9 2% and lower than 1 20% of the internal reference voltage and the soft start is finished, the power good signal is pulled high . When the output voltage is lower than 8 7% after the soft start finishes, the PG signal remains low. When the output voltage is higher than 1 20% of the internal reference, PG is switched low. The PG signal rises high again after the output voltage drops below 10 7% of the internal reference voltage. The PG output is pulled low when EN is low, or VIN UVLO, OCP, or over-temperature protection (OTP) is triggered. Pre-Bias Start-Up The MP2331H is designed for monotonic start - up into pre -biased loads. If the output is pre - biased to a certain voltage during start -up, the BST voltage is refreshed and charged, and the voltage on the soft -start is charged as well . If the BST voltage exceeds its rising threshold voltage, and VSS/2 exceeds the sensed output voltage at FB, the part begins working normally. TON Extension Operation To improve dropout, the MP233 1H is designed to extend the on time when the minimum off time is reached. The HS-FET on time extends , and the frequency drops. The typical minimum frequency is 280kHz. When the frequency drops to 280kHz, the frequency cannot reduce further, and the duty cycle reaches the max duty cycle ( Dmax). If the input voltage continues to drop, the MP2330H works at the max duty cycle , and the output voltage drops. The typical Dmax is 95%. Thermal Shutdown Thermal shutdown prevent s the chip from operating at exceedingly high temperatures. When the silicon die temperature exceeds 150°C, the entire chip shuts down . When the temperature falls below its lower threshold (typically 130°C), the chip is enabled again. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating power MOSFET driver. This floating driver has its own UVLO protection with a rising threshold of 2.2V and a hysteresis of 150mV. VIN regulates the bootstrap capacitor voltage internally through D1, M 1, R4, C3, L1, and C2 (see Figure 3). If VIN - VSW exceeds 3.3 V, U2 regulates M1 to maintain a 3.3V BST voltage across C3. 3.3V Figure 3: Internal Bootstrap Charger Start-Up and Shutdown If both V IN and EN exceed their respective thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current , and then the i nternal regulator is enabled. The regulator provides a stable supply for the remaining circuits. Three events can shut down the chip: EN low, VIN low, and thermal shutdown. The shutdown procedure starts by blocking the signaling path initially to avoid any fault triggering. The internal supply rail is then pulled down.
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APPLICATION INFORMATION
Setting the Output Voltage The external resistor divider is used to set the output voltage. First, choose a value for R2. R2 should be chosen reasonably, since a small R2 leads to considerable quiescent current loss , but a large R2 makes FB noise -sensitive. Typically, an R2 value between 5 - 30µA provides a good balance between syste m stability and no-load loss. Then determine R1 with Equation (2): OUT REF REF VVR1 R2 V (2) The feedback circuit is shown in Figure 4. MP2331H FB Vout RT Figure 4: Feedback Network Table 1 and Table 2 list the recommended parameters for common output voltages. Table 1: Parameter Selection for Common Output Voltages, VIN = 19V (9) VOUT (V) R1 (kΩ) R2 (kΩ) RT (kΩ) L (μH) 1.0 33 133 30 1 1.2 40.2 82 30 1.2 1.5 40.2 45.3 30 1.5 1.8 40.2 32.4 20 1.5 2.5 40.2 19.1 20 2.2 3.3 40.2 13 20 2.2 5 40.2 7.68 10 3.3 NOTE: 9) Different output inductor values and output capacitor values may affect the selection of R1, R2, and RT . For additional component parameters, please refer to the Typical Application Circuits on page 17 to page 19. Table 2: Parameter Selection for Common Output Voltages, VIN = 5V VOUT (V) R1 (kΩ) R2 (kΩ) RT (kΩ) L (μH) 1.0 33 133 30 0.47 1.2 40.2 82 30 0.68 1.5 40.2 45.3 30 0.68 1.8 40.2 32.4 20 0.68 2.5 40.2 19.1 20 0.68 3.3 40.2 13 40.2 0.47 5 (10) 40.2 7.68 10 0.68 NOTE: 10) For VOUT = 5V, VIN should be no lower than 6.5V. Selecting the Inductor An inductor is necessary for supplying constant current to the output load while being driven by the switched input voltage. A larger inductor value results in less ripple current and a lower output ri pple voltage but also has a larger physical footprint, higher series resistance, and lower saturation current. A good rule for determining the inductance value is to design the peak -to-peak ripple current in the inductor to be in the range of 30 - 60% of the maximum output current . The peak inductor current should be below the maximum switch current limit. The inductance value can be calculated with Equation (3): OUT OUT SW L IN Where ∆IL is the peak -to-peak inductor ripple current. The inductor should not saturate under the maximum inductor peak current, where the peak inductor current can be calculated with Equation (4): OUT OUT LP OUT SW IN VVI I (1 ) 2F L V (4) Selecting the Input Capacitor The input current to the step -down converter is discontinuous and therefore requires a capacitor to supply AC current to the step-down converter while maintaining the DC input voltage. For the best performance, use ceramic capacitors placed as close to IN as possible. Capacitors with X5R and X7R ceramic
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 15 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. dielectrics are recommended because they are fairly stable with temperature fluctuations. The capacitors must also have a ripple cur rent rating greater than the maximum input ripple current of the converter. The input ripple current can be estimated with Equation (5): OUT OUT CIN OUT IN IN VVI I (1 ) VV (5) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (6): OUT CIN II 2 (6) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitance value determines the input voltage ripple of the converter. If there is an input voltage ripple requirement in the system, choose an input capacitor that meets the specification. The input voltage ripple can be estimated with Equation (7): OUT OUT OUT IN SW IN IN IN (7) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (8): OUT IN SW IN I1V 4 F C (8) Selecting the Output Capacitor An output capacitor is required to maintain the DC output voltage. Ceramic or PO SCAP capacitors are recommended. The output voltage ripple can be estimated with Equation (9): OUT OUT OUT ESR SW IN SW OUT (9) In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage r ipple is caused mainly by the capacitance. For simplification, the output voltage ripple can be estimated with Equation (10): OUT OUT OUT 2 SW OUT IN (10) The output voltage ripple caused by the ESR is very small. In the case of POSCAP c apacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (11): OUT OUT OUT ESR SW IN (11) Choose a larger output capa citor for a better load transient response, but be sure to consider the maximum output capacitor limitation in the design application. If the output capacitor value is too high, the output voltage cannot reach the design value during the soft -start time and will fail to regulate. The maximum output capacitor value (Co_max) can be limited approximately with Equation (12): O _MAX LIM_ AVG OUT ss OUTC (I I ) T / V (12) Where ILIM_AVG is the average start -up cu rrent during the soft-start period, and Tss is the soft - start time. PCB Layout Guidelines Efficient PCB layout of the switching power supplies is critical for stable operation. A poor layout design can result in poor line or load regulation and stability issues. For best results, refer to Figure 5 and follow the guidelines below. 1. Place the high-current paths (GND, VIN , and SW) as close to the device as possible with short, direct, and wide traces. 2. Place the input capacitor as close to IN and GND as possi ble (recommended within 1mm). 3. Place the external feedback resistors next to FB. 4. Keep the switching node (SW) short and away from the feedback network.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 16 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Top Layer GND VOUT Bottom Layer Figure 5: Recommended Layout Design Example Table 3 shows a design example when ceramic capacitors are applied. Table 3: Design Example VIN 19V VOUT 3.3V IOUT 2A The detailed application schematic s are shown in Figure 6 through Figure 12 . The typical performance and waveforms are shown in the Typical Characteristics section. For more devices applications, please refer to the related evaluation board datasheet.
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER MP2331H Rev. 1.0 www.MonolithicPower.com 19 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. TYPICAL APPLICATION CIRCUITS (continued) 1µHMP2331H 10pF PG SS 6.8nF 1nF PG R1R3 1V/2A 30kΩ 604kΩ 22µF 22µF 22µF 0.1µF 20Ω 1µF 133kΩ 33kΩ Figure 12: VIN = 19V, VOUT = 1V/2A
MP2331H – 24V, 2A, SYNCHRONOUS BUCK CONVERTER NOTICE: The information in this document is subjec t to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2331H Rev. 1.0 www.MonolithicPower.com 20 10/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.
PACKAGE INFORMATION
SOT583 (1.6mmx2.1mm) FRONT VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 3) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 4) DRAWING IS NOT TO SCALE. TOP VIEW BOTTOM VIEW RECOMMENDED LAND PATTERN SIDE VIEW PIN 1 ID